December 2023 - U-Boot

[PATCH V4 0/3] doc: falcon: riscv: Falcon Mode boot on RISC-V
by Randolph 31 Jan '24

31 Jan '24

Changes in v4: - remove "Function that a board must implement" section in falcon.rst - fix compile error when config LOAD_FIT_OPENSBI_OS_BOOT not enabled. Changes in v3: - Change by suggestions in falcon.rst - Move the board-related code to arch-specific code, its the issue when enabling LOAD_FIT_OPENSBI_OS_BOOT - Add SPL_PAYLOAD_ARGS_ADDR to defconfig. This is the address that SPL copies into defconfig. Randolph (3): doc: falcon: riscv: Falcon Mode boot on RISC-V spl: riscv: falcon: move fdt blob to specified address configs: andes: add the fdt blob copy address for SPL board/AndesTech/ae350/ae350.c | 25 ---- common/spl/Kconfig | 2 +- common/spl/spl_opensbi.c | 15 +++ configs/ae350_rv32_falcon_defconfig | 1 + configs/ae350_rv32_falcon_xip_defconfig | 1 + configs/ae350_rv64_falcon_defconfig | 1 + configs/ae350_rv64_falcon_xip_defconfig | 1 + doc/develop/falcon.rst | 158 ++++++++++++++++++++++++ 8 files changed, 178 insertions(+), 26 deletions(-) -- 2.34.1

2 6

[PATCH 0/3] clk: Remove clk_free and better document clk_ops
by Sean Anderson 30 Jan '24

30 Jan '24

This series contains two unrelated changes. They are included together because they touch the same files and would otherwise conflict. The first change is to completely remove clk_free. This is because the op it calls (rfree) is completely unused. I believe the original intent of this op was to allow clock drivers to free resources allocated in request. However, no clock drivers do this, so we can remove the function and all its callers. The second change is to document the expected behavior and return codes of all clock functions. At the moment, drivers are very inconsistent. I would like to have some easily-verified expected behavior we can use when reviewing clock drivers. Existing code is not fixed, but I hope to make some conversions in the future. Sean Anderson (3): clk: Remove rfree treewide: Remove clk_free clk: Document clk_ops return codes and behavior arch/arm/mach-rockchip/rk3288/rk3288.c | 2 - arch/arm/mach-socfpga/clock_manager_agilex.c | 2 - arch/arm/mach-socfpga/clock_manager_arria10.c | 7 +- arch/arm/mach-socfpga/clock_manager_n5x.c | 2 - arch/arm/mach-zynq/clk.c | 2 - arch/mips/mach-pic32/cpu.c | 7 +- arch/sandbox/include/asm/clk.h | 8 -- board/microchip/pic32mzda/pic32mzda.c | 2 - board/sipeed/maix/maix.c | 1 - board/synopsys/hsdk/clk-lib.c | 2 - drivers/clk/aspeed/clk_ast2600.c | 2 - drivers/clk/at91/compat.c | 14 +- drivers/clk/clk-uclass.c | 40 +----- drivers/clk/clk-xlnx-clock-wizard.c | 1 - drivers/clk/clk_sandbox.c | 12 -- drivers/clk/clk_sandbox_test.c | 12 -- drivers/clk/clk_versaclock.c | 12 +- drivers/clk/clk_zynq.c | 2 - drivers/clk/clk_zynqmp.c | 2 - drivers/clk/imx/clk-imx8.c | 2 - drivers/clk/mvebu/armada-37xx-periph.c | 2 - drivers/cpu/riscv_cpu.c | 2 - drivers/dma/bcm6348-iudma.c | 2 - drivers/gpio/at91_gpio.c | 2 - drivers/gpio/atmel_pio4.c | 2 - drivers/gpio/gpio-rcar.c | 1 - drivers/hwspinlock/stm32_hwspinlock.c | 6 +- drivers/i2c/at91_i2c.c | 2 - drivers/i2c/designware_i2c.c | 2 - drivers/i2c/i2c-microchip.c | 2 - drivers/i2c/npcm_i2c.c | 1 - drivers/i2c/ocores_i2c.c | 2 - drivers/i2c/stm32f7_i2c.c | 4 +- drivers/mailbox/stm32-ipcc.c | 7 +- drivers/misc/ls2_sfp.c | 1 - drivers/mmc/arm_pl180_mmci.c | 1 - drivers/mmc/aspeed_sdhci.c | 4 +- drivers/mmc/atmel_sdhci.c | 2 - drivers/mmc/gen_atmel_mci.c | 19 +-- drivers/mmc/msm_sdhci.c | 1 - drivers/mmc/pic32_sdhci.c | 1 - drivers/mmc/renesas-sdhi.c | 21 +-- drivers/mmc/snps_dw_mmc.c | 8 +- drivers/mmc/socfpga_dw_mmc.c | 1 - drivers/mmc/stm32_sdmmc2.c | 4 +- drivers/mmc/uniphier-sd.c | 1 - drivers/mtd/nand/raw/atmel/nand-controller.c | 4 +- drivers/mtd/renesas_rpc_hf.c | 1 - drivers/net/bcm6348-eth.c | 2 - drivers/net/bcm6368-eth.c | 2 - drivers/net/designware.c | 1 - drivers/net/dwc_eth_qos.c | 43 +----- drivers/net/dwc_eth_qos_imx.c | 21 +-- drivers/net/dwc_eth_qos_qcom.c | 1 - drivers/net/dwc_eth_qos_rockchip.c | 6 +- drivers/net/sni_ave.c | 5 +- drivers/net/ti/am65-cpsw-nuss.c | 1 - drivers/phy/bcm6318-usbh-phy.c | 2 - drivers/phy/bcm6348-usbh-phy.c | 2 - drivers/phy/bcm6368-usbh-phy.c | 4 - drivers/phy/meson-axg-mipi-dphy.c | 1 - drivers/phy/meson-g12a-usb3-pcie.c | 1 - drivers/phy/meson-gxl-usb2.c | 1 - drivers/phy/phy-rcar-gen2.c | 1 - drivers/phy/phy-rcar-gen3.c | 1 - drivers/pinctrl/pinctrl-k210.c | 20 +-- drivers/power/domain/imx8mp-hsiomix.c | 4 +- drivers/rtc/stm32_rtc.c | 16 +-- drivers/serial/atmel_usart.c | 2 - drivers/serial/serial_bcm6345.c | 1 - drivers/serial/serial_msm.c | 1 - drivers/serial/serial_pic32.c | 1 - drivers/spi/atcspi200_spi.c | 1 - drivers/spi/atmel-quadspi.c | 14 +- drivers/spi/atmel_spi.c | 2 - drivers/spi/bcm63xx_hsspi.c | 4 - drivers/spi/bcm63xx_spi.c | 2 - drivers/spi/bcmbca_hsspi.c | 4 - drivers/spi/cadence_qspi.c | 1 - drivers/spi/designware_spi.c | 5 - drivers/spi/meson_spifc_a1.c | 10 -- drivers/spi/mvebu_a3700_spi.c | 10 -- drivers/spi/spi-aspeed-smc.c | 1 - drivers/spi/stm32_spi.c | 19 +-- drivers/timer/dw-apb-timer.c | 2 - drivers/timer/ostm_timer.c | 2 - drivers/usb/dwc3/dwc3-meson-g12a.c | 4 +- drivers/usb/dwc3/dwc3-meson-gxl.c | 4 +- drivers/usb/host/ehci-atmel.c | 8 +- drivers/usb/host/ohci-da8xx.c | 1 - drivers/usb/host/xhci-rcar.c | 5 +- drivers/video/atmel_hlcdfb.c | 2 - drivers/video/mali_dp.c | 11 +- drivers/video/rockchip/rk3288_hdmi.c | 4 +- drivers/video/rockchip/rk_edp.c | 8 +- drivers/watchdog/designware_wdt.c | 18 +-- drivers/watchdog/meson_gxbb_wdt.c | 4 +- include/clk-uclass.h | 123 +++++++++++++++--- include/clk.h | 31 ----- test/dm/clk.c | 9 -- 100 files changed, 174 insertions(+), 515 deletions(-) -- 2.37.1

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[PATCH v3] clk: meson: add Hardware Clock measure driver
by Neil Armstrong 30 Jan '24

30 Jan '24

Amlogic SoCs embeds an hardware clock measure block, port it from Linux and implement it as a UCLK_CLK with only the dump op and fail-only xlate. Based on the Linux driver introduced in [1]. [1] commit 2b45ebef39a2 ("soc: amlogic: Add Meson Clock Measure driver"). Reviewed-by: Sean Anderson <seanga2(a)gmail.com> Signed-off-by: Neil Armstrong <neil.armstrong(a)linaro.org> --- Changes in v3: - Fixed/extended Kconfig and commit message following Sean's advices - Link to v2: https://lore.kernel.org/r/20231212-uboot-meson-clk-msr-v2-1-1cd0addf4dda@li… Changes in v2: - remove common.h and include time.h instead - Link to v1: https://lore.kernel.org/r/20231113-uboot-meson-clk-msr-v1-1-73204d09fc0b@li… --- drivers/clk/meson/Kconfig | 10 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-measure.c | 634 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 645 insertions(+) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index cdc9d6f76c..ee33c61140 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -29,3 +29,13 @@ config CLK_MESON_A1 help Enable clock support for the Amlogic A1 SoC family, such as the A113L + +config CLK_MESON_MSR + bool "Enable clock measure driver for Amlogic SoCs" + depends on CLK && ARCH_MESON + depends on CMD_CLK + default ARCH_MESON + help + Enable measuring a set of internal Amlogic SoC clock frequencies + using the Hardware Clock Measure registers and print them using + the clk dump command. diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index d975f07aab..c7a446e86c 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_CLK_MESON_AXG) += axg-ao.o obj-$(CONFIG_CLK_MESON_G12A) += g12a.o obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o obj-$(CONFIG_CLK_MESON_A1) += a1.o +obj-$(CONFIG_CLK_MESON_MSR) += clk-measure.o diff --git a/drivers/clk/meson/clk-measure.c b/drivers/clk/meson/clk-measure.c new file mode 100644 index 0000000000..f653fc6355 --- /dev/null +++ b/drivers/clk/meson/clk-measure.c @@ -0,0 +1,634 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Based on Linux driver from: + * (C) Copyright 2018 - BayLibre, SAS + * Author: Neil Armstrong <narmstrong(a)baylibre.com> + * (C) Copyright 2023 - Neil Armstrong <neil.armstrong(a)linaro.org> + */ + +#include <log.h> +#include <clk-uclass.h> +#include <div64.h> +#include <dm.h> +#include <time.h> +#include <regmap.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/kernel.h> + +#define MSR_CLK_DUTY 0x0 +#define MSR_CLK_REG0 0x4 +#define MSR_CLK_REG1 0x8 +#define MSR_CLK_REG2 0xc + +#define MSR_DURATION GENMASK(15, 0) +#define MSR_ENABLE BIT(16) +#define MSR_CONT BIT(17) /* continuous measurement */ +#define MSR_INTR BIT(18) /* interrupts */ +#define MSR_RUN BIT(19) +#define MSR_CLK_SRC GENMASK(26, 20) +#define MSR_BUSY BIT(31) + +#define MSR_VAL_MASK GENMASK(15, 0) + +#define DIV_MIN 32 +#define DIV_STEP 32 +#define DIV_MAX 640 + +#define CLK_MSR_MAX 128 + +struct meson_msr_id { + unsigned int id; + const char *name; +}; + +struct meson_msr { + struct regmap *regmap; + struct meson_msr_id *msr_table; +}; + +#define CLK_MSR_ID(__id, __name) \ + [__id] = {.id = __id, .name = __name,} + +static struct meson_msr_id clk_msr_m8[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee0"), + CLK_MSR_ID(1, "ring_osc_out_ee1"), + CLK_MSR_ID(2, "ring_osc_out_ee2"), + CLK_MSR_ID(3, "a9_ring_osck"), + CLK_MSR_ID(6, "vid_pll"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(11, "eth_rmii"), + CLK_MSR_ID(13, "amclk"), + CLK_MSR_ID(14, "fec_clk_0"), + CLK_MSR_ID(15, "fec_clk_1"), + CLK_MSR_ID(16, "fec_clk_2"), + CLK_MSR_ID(18, "a9_clk_div16"), + CLK_MSR_ID(19, "hdmi_sys"), + CLK_MSR_ID(20, "rtc_osc_clk_out"), + CLK_MSR_ID(21, "i2s_clk_in_src0"), + CLK_MSR_ID(22, "clk_rmii_from_pad"), + CLK_MSR_ID(23, "hdmi_ch0_tmds"), + CLK_MSR_ID(24, "lvds_fifo"), + CLK_MSR_ID(26, "sc_clk_int"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(30, "mpll_clk_test_out"), + CLK_MSR_ID(31, "audac_clkpi"), + CLK_MSR_ID(32, "vdac"), + CLK_MSR_ID(33, "sdhc_rx"), + CLK_MSR_ID(34, "sdhc_sd"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "pcm_sclk"), + CLK_MSR_ID(40, "pcm_mclk"), + CLK_MSR_ID(41, "eth_rx_tx"), + CLK_MSR_ID(42, "pwm_d"), + CLK_MSR_ID(43, "pwm_c"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "pcm2_sclk"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "pwm_f"), + CLK_MSR_ID(49, "pwm_e"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(60, "usb_32k_alt"), + CLK_MSR_ID(61, "gpio"), + CLK_MSR_ID(62, "vid2_pll"), + CLK_MSR_ID(63, "mipi_csi_cfg"), +}; + +static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "a53_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "rgmii_tx"), + CLK_MSR_ID(12, "pdm"), + CLK_MSR_ID(13, "amclk"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "hdmitx_sys"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "i2s_in_src0"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "hdmi_todig"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "i958"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "pcm_sclk"), + CLK_MSR_ID(40, "pcm_mclk"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "nand_core"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "cci"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(60, "alt_32k"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevc"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(75, "aoclkx2_int"), + CLK_MSR_ID(76, "aoclk_int"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), +}; + +static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "a53_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(5, "gp1_pll"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(23, "mmc_clk"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(40, "mod_eth_tx_clk"), + CLK_MSR_ID(41, "mod_eth_rx_clk_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmm_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(66, "audio_slv_lrclk_c"), + CLK_MSR_ID(67, "audio_slv_lrclk_b"), + CLK_MSR_ID(68, "audio_slv_lrclk_a"), + CLK_MSR_ID(69, "audio_slv_sclk_c"), + CLK_MSR_ID(70, "audio_slv_sclk_b"), + CLK_MSR_ID(71, "audio_slv_sclk_a"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(74, "wifi_beacon"), + CLK_MSR_ID(75, "tdmin_lb_lrcl"), + CLK_MSR_ID(76, "tdmin_lb_sclk"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(84, "audio_resample"), + CLK_MSR_ID(85, "audio_pdm_sys"), + CLK_MSR_ID(86, "audio_spdifout"), + CLK_MSR_ID(87, "audio_spdifin"), + CLK_MSR_ID(88, "audio_lrclk_f"), + CLK_MSR_ID(89, "audio_lrclk_e"), + CLK_MSR_ID(90, "audio_lrclk_d"), + CLK_MSR_ID(91, "audio_lrclk_c"), + CLK_MSR_ID(92, "audio_lrclk_b"), + CLK_MSR_ID(93, "audio_lrclk_a"), + CLK_MSR_ID(94, "audio_sclk_f"), + CLK_MSR_ID(95, "audio_sclk_e"), + CLK_MSR_ID(96, "audio_sclk_d"), + CLK_MSR_ID(97, "audio_sclk_c"), + CLK_MSR_ID(98, "audio_sclk_b"), + CLK_MSR_ID(99, "audio_sclk_a"), + CLK_MSR_ID(100, "audio_mclk_f"), + CLK_MSR_ID(101, "audio_mclk_e"), + CLK_MSR_ID(102, "audio_mclk_d"), + CLK_MSR_ID(103, "audio_mclk_c"), + CLK_MSR_ID(104, "audio_mclk_b"), + CLK_MSR_ID(105, "audio_mclk_a"), + CLK_MSR_ID(106, "pcie_refclk_n"), + CLK_MSR_ID(107, "pcie_refclk_p"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), +}; + +static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "sys_cpu_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "eth_tx"), + CLK_MSR_ID(12, "hifi_pll"), + CLK_MSR_ID(13, "mod_tcon"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "lcd_an_ph2"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "lcd_an_ph3"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "mpll_50m"), + CLK_MSR_ID(24, "eth_125m"), + CLK_MSR_ID(25, "eth_rmii"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(27, "in_mac"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(29, "pcie_inp"), + CLK_MSR_ID(30, "pcie_inn"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(33, "sys_cpu_ring_osc_1"), + CLK_MSR_ID(34, "eth_mpll_50m"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "cdac"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "bt656"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmc_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(54, "vpu_clkc"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "wave420l_a"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevcb"), + CLK_MSR_ID(63, "dsi_meas"), + CLK_MSR_ID(64, "spicc_1"), + CLK_MSR_ID(65, "spicc_0"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(67, "dsi_phy"), + CLK_MSR_ID(68, "hdcp22_esm"), + CLK_MSR_ID(69, "hdcp22_skp"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(75, "hevcf"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(83, "co_rx"), + CLK_MSR_ID(84, "co_tx"), + CLK_MSR_ID(89, "hdmi_todig"), + CLK_MSR_ID(90, "hdmitx_sys"), + CLK_MSR_ID(91, "sys_cpub_div16"), + CLK_MSR_ID(92, "sys_pll_cpub_div16"), + CLK_MSR_ID(94, "eth_phy_rx"), + CLK_MSR_ID(95, "eth_phy_pll"), + CLK_MSR_ID(96, "vpu_b"), + CLK_MSR_ID(97, "cpu_b_tmp"), + CLK_MSR_ID(98, "ts"), + CLK_MSR_ID(99, "ring_osc_out_ee_3"), + CLK_MSR_ID(100, "ring_osc_out_ee_4"), + CLK_MSR_ID(101, "ring_osc_out_ee_5"), + CLK_MSR_ID(102, "ring_osc_out_ee_6"), + CLK_MSR_ID(103, "ring_osc_out_ee_7"), + CLK_MSR_ID(104, "ring_osc_out_ee_8"), + CLK_MSR_ID(105, "ring_osc_out_ee_9"), + CLK_MSR_ID(106, "ephy_test"), + CLK_MSR_ID(107, "au_dac_g128x"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), + CLK_MSR_ID(110, "audio_tdmout_c_sclk"), + CLK_MSR_ID(111, "audio_tdmout_b_sclk"), + CLK_MSR_ID(112, "audio_tdmout_a_sclk"), + CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), + CLK_MSR_ID(114, "audio_tdmin_c_sclk"), + CLK_MSR_ID(115, "audio_tdmin_b_sclk"), + CLK_MSR_ID(116, "audio_tdmin_a_sclk"), + CLK_MSR_ID(117, "audio_resample"), + CLK_MSR_ID(118, "audio_pdm_sys"), + CLK_MSR_ID(119, "audio_spdifout_b"), + CLK_MSR_ID(120, "audio_spdifout"), + CLK_MSR_ID(121, "audio_spdifin"), + CLK_MSR_ID(122, "audio_pdm_dclk"), +}; + +static struct meson_msr_id clk_msr_sm1[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "ring_osc_out_ee_3"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(5, "gp1_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "eth_tx"), + CLK_MSR_ID(12, "hifi_pll"), + CLK_MSR_ID(13, "mod_tcon"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "lcd_an_ph2"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "lcd_an_ph3"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "mpll_50m"), + CLK_MSR_ID(24, "eth_125m"), + CLK_MSR_ID(25, "eth_rmii"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(27, "in_mac"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(29, "pcie_inp"), + CLK_MSR_ID(30, "pcie_inn"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(34, "eth_mpll_50m"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "cdac"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "bt656"), + CLK_MSR_ID(40, "arm_ring_osc_out_4"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "sd_emmc_c"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(54, "vpu_clkc"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "wave420l_a"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(60, "arm_ring_osc_out_5"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevcb"), + CLK_MSR_ID(63, "dsi_meas"), + CLK_MSR_ID(64, "spicc_1"), + CLK_MSR_ID(65, "spicc_0"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(67, "dsi_phy"), + CLK_MSR_ID(68, "hdcp22_esm"), + CLK_MSR_ID(69, "hdcp22_skp"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(74, "arm_ring_osc_out_6"), + CLK_MSR_ID(75, "hevcf"), + CLK_MSR_ID(76, "arm_ring_osc_out_7"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), + CLK_MSR_ID(83, "co_rx"), + CLK_MSR_ID(84, "co_tx"), + CLK_MSR_ID(85, "arm_ring_osc_out_8"), + CLK_MSR_ID(86, "arm_ring_osc_out_9"), + CLK_MSR_ID(87, "mipi_dsi_phy"), + CLK_MSR_ID(88, "cis2_adapt"), + CLK_MSR_ID(89, "hdmi_todig"), + CLK_MSR_ID(90, "hdmitx_sys"), + CLK_MSR_ID(91, "nna_core"), + CLK_MSR_ID(92, "nna_axi"), + CLK_MSR_ID(93, "vad"), + CLK_MSR_ID(94, "eth_phy_rx"), + CLK_MSR_ID(95, "eth_phy_pll"), + CLK_MSR_ID(96, "vpu_b"), + CLK_MSR_ID(97, "cpu_b_tmp"), + CLK_MSR_ID(98, "ts"), + CLK_MSR_ID(99, "arm_ring_osc_out_10"), + CLK_MSR_ID(100, "arm_ring_osc_out_11"), + CLK_MSR_ID(101, "arm_ring_osc_out_12"), + CLK_MSR_ID(102, "arm_ring_osc_out_13"), + CLK_MSR_ID(103, "arm_ring_osc_out_14"), + CLK_MSR_ID(104, "arm_ring_osc_out_15"), + CLK_MSR_ID(105, "arm_ring_osc_out_16"), + CLK_MSR_ID(106, "ephy_test"), + CLK_MSR_ID(107, "au_dac_g128x"), + CLK_MSR_ID(108, "audio_locker_out"), + CLK_MSR_ID(109, "audio_locker_in"), + CLK_MSR_ID(110, "audio_tdmout_c_sclk"), + CLK_MSR_ID(111, "audio_tdmout_b_sclk"), + CLK_MSR_ID(112, "audio_tdmout_a_sclk"), + CLK_MSR_ID(113, "audio_tdmin_lb_sclk"), + CLK_MSR_ID(114, "audio_tdmin_c_sclk"), + CLK_MSR_ID(115, "audio_tdmin_b_sclk"), + CLK_MSR_ID(116, "audio_tdmin_a_sclk"), + CLK_MSR_ID(117, "audio_resample"), + CLK_MSR_ID(118, "audio_pdm_sys"), + CLK_MSR_ID(119, "audio_spdifout_b"), + CLK_MSR_ID(120, "audio_spdifout"), + CLK_MSR_ID(121, "audio_spdifin"), + CLK_MSR_ID(122, "audio_pdm_dclk"), + CLK_MSR_ID(123, "audio_resampled"), + CLK_MSR_ID(124, "earcrx_pll"), + CLK_MSR_ID(125, "earcrx_pll_test"), + CLK_MSR_ID(126, "csi_phy0"), + CLK_MSR_ID(127, "csi2_data"), +}; + +static int meson_clk_msr_measure_id(struct meson_msr *priv, unsigned int id, + unsigned int duration) +{ + unsigned int val; + int ret; + + regmap_write(priv->regmap, MSR_CLK_REG0, 0); + + /* Set measurement duration */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_DURATION, + FIELD_PREP(MSR_DURATION, duration - 1)); + + /* Set ID */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_CLK_SRC, + FIELD_PREP(MSR_CLK_SRC, id)); + + /* Enable & Start */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, + MSR_RUN | MSR_ENABLE, + MSR_RUN | MSR_ENABLE); + + ret = regmap_read_poll_timeout(priv->regmap, MSR_CLK_REG0, + val, !(val & MSR_BUSY), 10, 10000); + if (ret) + return ret; + + /* Disable */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_ENABLE, 0); + + /* Get the value in multiple of gate time counts */ + regmap_read(priv->regmap, MSR_CLK_REG2, &val); + + if (val >= MSR_VAL_MASK) + return -EINVAL; + + return DIV_ROUND_CLOSEST_ULL((val & MSR_VAL_MASK) * 1000000ULL, + duration); +} + +static int meson_clk_msr_best_id(struct meson_msr *priv, unsigned int id, + unsigned int *precision) +{ + unsigned int duration = DIV_MAX; + int ret; + + /* Start from max duration and down to min duration */ + do { + ret = meson_clk_msr_measure_id(priv, id, duration); + if (ret >= 0) + *precision = (2 * 1000000) / duration; + else + duration -= DIV_STEP; + } while (duration >= DIV_MIN && ret == -EINVAL); + + return ret; +} + +static void meson_clk_msr_dump(struct udevice *dev) +{ + struct meson_msr *priv = dev_get_priv(dev); + unsigned int precision = 0; + int val, i; + + printf(" clock rate precision\n"); + printf("---------------------------------------------\n"); + + for (i = 0 ; i < CLK_MSR_MAX ; ++i) { + if (!priv->msr_table[i].name) + continue; + + val = meson_clk_msr_best_id(priv, i, &precision); + if (val < 0) + return; + + printf(" %-20s %10d +/-%dHz\n", + priv->msr_table[i].name, val, precision); + } +} + +static int meson_clk_msr_xlate(struct clk *clk, struct ofnode_phandle_args *args) +{ + /* This driver doesn't expose any clocks */ + return -EINVAL; +} + +static int meson_clk_msr_probe(struct udevice *dev) +{ + struct meson_msr *priv = dev_get_priv(dev); + int ret; + + priv->msr_table = (struct meson_msr_id *)dev_get_driver_data(dev); + + ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap); + if (ret) + return ret; + + return 0; +} + +static struct clk_ops meson_clk_msr_ops = { + .of_xlate = meson_clk_msr_xlate, + .dump = meson_clk_msr_dump, +}; + +static const struct udevice_id meson_clk_msr_ids[] = { + { + .compatible = "amlogic,meson-gx-clk-measure", + .data = (ulong)clk_msr_gx, + }, + { + .compatible = "amlogic,meson8-clk-measure", + .data = (ulong)clk_msr_m8, + }, + { + .compatible = "amlogic,meson8b-clk-measure", + .data = (ulong)clk_msr_m8, + }, + { + .compatible = "amlogic,meson-axg-clk-measure", + .data = (ulong)clk_msr_axg, + }, + { + .compatible = "amlogic,meson-g12a-clk-measure", + .data = (ulong)clk_msr_g12a, + }, + { + .compatible = "amlogic,meson-sm1-clk-measure", + .data = (ulong)clk_msr_sm1, + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(meson_clk_msr) = { + .name = "meson_clk_msr", + .id = UCLASS_CLK, + .of_match = meson_clk_msr_ids, + .priv_auto = sizeof(struct meson_msr), + .ops = &meson_clk_msr_ops, + .probe = meson_clk_msr_probe, +}; --- base-commit: e1b7717928eff69178604a400fe40dbf3287d9a1 change-id: 20231113-uboot-meson-clk-msr-21cf9101278b Best regards, -- Neil Armstrong <neil.armstrong(a)linaro.org>

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[PATCH v2] clk: fix clk_get_rate() always return ulong
by Julien Masson 30 Jan '24

30 Jan '24

When we call clk_get_rate(), we expect to get clock rate value as ulong. In that case we should not use log_ret() macro since it use internally an int. Otherwise we may return an invalid/truncated clock rate value. Signed-off-by: Julien Masson <jmasson(a)baylibre.com> --- Changes in v2: - remove local var ret (fix warning) - Link to v1: https://lore.kernel.org/all/871qcj5frz.fsf@baylibre.com --- drivers/clk/clk-uclass.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 3b5e3f9c86..3cbcb2d033 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -478,7 +478,6 @@ void clk_free(struct clk *clk) ulong clk_get_rate(struct clk *clk) { const struct clk_ops *ops; - ulong ret; debug("%s(clk=%p)\n", __func__, clk); if (!clk_valid(clk)) @@ -488,11 +487,7 @@ ulong clk_get_rate(struct clk *clk) if (!ops->get_rate) return -ENOSYS; - ret = ops->get_rate(clk); - if (ret) - return log_ret(ret); - - return 0; + return ops->get_rate(clk); } struct clk *clk_get_parent(struct clk *clk) -- 2.43.0

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[PATCH] sunxi: add defconfig for nanopi_duo2
by Chuanhong Guo 30 Jan '24

30 Jan '24

FriendlyElec NanoPi Duo2 is a tiny SBC with Allwinner H3 and Ampak AP6212 WiFi module. The device-tree for it is already available in u-boot source tree. Add a default config for it. Signed-off-by: Chuanhong Guo <gch981213(a)gmail.com> --- configs/nanopi_duo2_defconfig | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 configs/nanopi_duo2_defconfig diff --git a/configs/nanopi_duo2_defconfig b/configs/nanopi_duo2_defconfig new file mode 100644 index 0000000000..5a2069789f --- /dev/null +++ b/configs/nanopi_duo2_defconfig @@ -0,0 +1,11 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-nanopi-duo2" +CONFIG_SPL=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=408 +# CONFIG_VIDEO_DE2 is not set +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y -- 2.43.0

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[PATCH v5 0/8] Move framebuffer reservation for SPL to RAM end
by Devarsh Thakkar 30 Jan '24

30 Jan '24

Move video memory reservation for SPL at end of RAM so that it does not interefere with reservations for next stage so that the next stage need not have holes in between for passed regions and instead it can maintain continuity in reservations. Also catch the bloblist before starting reservations to avoid the same problem. While at it, also fill missing fields in video handoff struct before passing it to next stage. This is as per discussions at : For moving SPL framebuffer reservation at end of RAM: https://lore.kernel.org/all/CAPnjgZ3xSoe_G3yrqwuAvoiVjUfZ+YQgkOR0ZTVXGT9VK8… For filling missing video handoff fields : https://lore.kernel.org/all/CAPnjgZ1Hs0rNf0JDirp6YPsOQ5=QqQSP9g9qRwLoOASUV8… Changelog: V2: - Make a generic function to reserve video memory at SPL stage. - Add debug prints while skipping framebuffer allocation at uboot. - Correct commenting style as suggested. V3: - Change spl_reserve_video to spl_reserve_video_from_ram_top which enforce framebuffer reservation from end of RAM. - Use gd->ram_top instead of local ram_top and update gd->reloc_addr after each reservation. - Print error message on framebuffer reservation. - Update SPL doc with spl splash screen specific info. V4: - Split patches into atomic commits. - Remove duplicate check for video blob passed addresses and error out if invalid address/size received from blob. - Improve SPL documentation memory reservation scheme and print message for video memory reservation from bloblist. - Add Reviewed-By. V5: - Add comment for filling video handoff size with aligned size - Use PHASE_BOARD_F while checking for U-boot proper stage - Add Reviewed-by Test logs: https://gist.github.com/devarsht/30a3c1591270c9ebae00714b48d33058 Devarsh Thakkar (8): spl: Enforce framebuffer reservation from end of RAM arm: mach-k3: common: Reserve video memory from end of the RAM board: ti: am62x: evm: Remove video_setup from spl_board_init common/board_f: Catch bloblist before starting reservations video: Skip framebuffer reservation if already reserved video: Fill video handoff in video post probe doc: spl: Add info for missing Kconfigs doc: spl: Add info regarding memory reservation arch/arm/mach-k3/common.c | 17 ++++++++++----- board/ti/am62x/evm.c | 18 ---------------- common/board_f.c | 41 +++++++++++++++++++++++++++++++----- common/spl/spl.c | 19 +++++++++++++++++ doc/develop/spl.rst | 37 ++++++++++++++++++++++++++++++++ drivers/video/video-uclass.c | 40 ++++++++++++++++++++++++----------- include/spl.h | 10 +++++++++ 7 files changed, 142 insertions(+), 40 deletions(-) -- 2.34.1

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[PATCH 0/5] sunxi: Control USB VBUS supplies via DT regulators
by Samuel Holland 30 Jan '24

30 Jan '24

This series converts sunxi boards from controlling VBUS suppllies using GPIO name strings in Kconfig to using regulator devices probed via the devicetree. ARCH_SUNXI already implies DM_REGULATOR_FIXED, so the only new driver needed is for the AXP PMIC drivevbus regulator. This is part 2 of 3 for removing the PHY driver's GPIO Kconfig options. Part 1 was here[1]. Part 3 will finish converting the VBUS/ID detection GPIOs; it requires adding some missing DT properties to a couple of boards, so it will have to wait for at least the next DT sync from Linux. I tried to verify (by inspection) every board affected by this change, but there is some possibility that this could break some boards. See the commit message for patch 3. I have CCed some relevant board maintaners; please test this patch series if you have the opportunity. [1]: https://lore.kernel.org/u-boot/20230122234623.1636-1-samuel@sholland.org/ Samuel Holland (5): power: regulator: Add a driver for the AXP PMIC drivevbus sunxi: Enable PMIC drivevbus regulator support for USB supplies phy: sun4i-usb: Control supplies via the regulator uclass sunxi: Remove obsolete USBx_VBUS_PIN Kconfig symbols gpio: axp: Remove virtual VBUS enable GPIO arch/arm/mach-sunxi/Kconfig | 29 -------- configs/A10s-OLinuXino-M_defconfig | 1 - configs/A13-OLinuXinoM_defconfig | 1 - configs/A13-OLinuXino_defconfig | 1 - configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 - configs/A20-OLinuXino-Lime2_defconfig | 1 - configs/A20-Olimex-SOM-EVB_defconfig | 1 - configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 - configs/A20-Olimex-SOM204-EVB_defconfig | 1 - configs/A33-OLinuXino_defconfig | 2 +- configs/Ainol_AW1_defconfig | 1 - configs/Ampe_A76_defconfig | 1 - configs/Auxtek-T003_defconfig | 1 - configs/Auxtek-T004_defconfig | 1 - configs/Bananapi_M2_Ultra_defconfig | 2 - configs/Bananapro_defconfig | 2 - configs/CHIP_defconfig | 1 - configs/CHIP_pro_defconfig | 1 - configs/CSQ_CS908_defconfig | 2 - configs/Chuwi_V7_CW0825_defconfig | 1 - configs/Colombus_defconfig | 1 - configs/Cubieboard4_defconfig | 4 +- configs/Cubietruck_defconfig | 1 - configs/Cubietruck_plus_defconfig | 4 +- configs/Empire_electronix_d709_defconfig | 1 - configs/Empire_electronix_m712_defconfig | 1 - configs/Hummingbird_A31_defconfig | 2 - configs/Hyundai_A7HD_defconfig | 3 - configs/Linksprite_pcDuino3_Nano_defconfig | 1 - configs/Linksprite_pcDuino_defconfig | 2 - configs/MSI_Primo81_defconfig | 2 +- configs/Mele_A1000G_quad_defconfig | 2 - configs/Mele_I7_defconfig | 2 - configs/Mele_M9_defconfig | 2 - configs/Merrii_A80_Optimus_defconfig | 4 +- configs/Mini-X_defconfig | 1 - configs/Orangepi_defconfig | 2 - configs/Orangepi_mini_defconfig | 2 - configs/Sinlinx_SinA31s_defconfig | 2 - configs/Sinovoip_BPI_M2_defconfig | 2 - configs/Sinovoip_BPI_M3_defconfig | 3 +- configs/Sunchip_CX-A99_defconfig | 3 - configs/UTOO_P66_defconfig | 1 - configs/Wexler_TAB7200_defconfig | 1 - configs/Wobo_i5_defconfig | 1 - configs/Yones_Toptech_BD1078_defconfig | 1 - configs/Yones_Toptech_BS1078_V2_defconfig | 2 +- configs/ba10_tv_box_defconfig | 2 - configs/bananapi_m2_berry_defconfig | 1 - configs/colorfly_e708_q1_defconfig | 2 +- configs/difrnce_dit4350_defconfig | 1 - configs/dserve_dsrv9703c_defconfig | 1 - configs/ga10h_v1_1_defconfig | 2 +- configs/gt90h_v4_defconfig | 2 +- configs/h8_homlet_v2_defconfig | 2 - configs/iNet_3F_defconfig | 1 - configs/iNet_3W_defconfig | 1 - configs/iNet_86VS_defconfig | 1 - configs/iNet_D978_rev2_defconfig | 2 +- configs/icnova-a20-swac_defconfig | 2 - configs/inet1_defconfig | 1 - configs/inet86dz_defconfig | 2 +- configs/inet97fv2_defconfig | 1 - configs/inet98v_rev2_defconfig | 1 - configs/inet9f_rev03_defconfig | 1 - configs/inet_q972_defconfig | 2 +- configs/jesurun_q5_defconfig | 1 - configs/mixtile_loftq_defconfig | 2 - configs/mk802_a10s_defconfig | 1 - configs/mk802_defconfig | 1 - configs/orangepi_2_defconfig | 1 - configs/orangepi_plus_defconfig | 2 - configs/parrot_r16_defconfig | 1 - configs/pine_h64_defconfig | 1 - configs/polaroid_mid2407pxe03_defconfig | 2 +- configs/polaroid_mid2809pxe04_defconfig | 2 +- configs/pov_protab2_ips9_defconfig | 1 - configs/q8_a13_tablet_defconfig | 1 - configs/q8_a23_tablet_800x480_defconfig | 2 +- configs/q8_a33_tablet_1024x600_defconfig | 2 +- configs/q8_a33_tablet_800x480_defconfig | 2 +- configs/r7-tv-dongle_defconfig | 1 - configs/sun8i_a23_evb_defconfig | 2 - configs/tbs_a711_defconfig | 2 +- configs/teres_i_defconfig | 1 - drivers/gpio/axp_gpio.c | 75 ++++++-------------- drivers/gpio/sunxi_gpio.c | 8 --- drivers/phy/allwinner/phy-sun4i-usb.c | 41 +++++------ drivers/power/pmic/axp.c | 1 + drivers/power/regulator/Kconfig | 7 ++ drivers/power/regulator/Makefile | 1 + drivers/power/regulator/axp_drivevbus.c | 57 +++++++++++++++ include/axp221.h | 4 -- include/axp809.h | 4 -- include/axp818.h | 4 -- include/sunxi_gpio.h | 8 --- 96 files changed, 125 insertions(+), 246 deletions(-) create mode 100644 drivers/power/regulator/axp_drivevbus.c -- 2.41.0

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[PATCH v3 0/4] sunxi: SPL FIT support for 32-bit sunxi SoCs
by Samuel Holland 29 Jan '24

29 Jan '24

This series makes the necessary changes so 32-bit sunxi SoCs can load additional device trees or firmware from SPL along with U-Boot proper. Crust (SCP firmware) has support for A33 and H3, and H3 also needs to load an eGon blob to support CPU 0 hotplug (a silicon bug workaround). FIT unlocks more features (signatures, multiple DTBs, etc.), so enable it by default. A10 (sun4i) only has 24 KiB of SRAM A1, so it needs SPL_FIT_IMAGE_TINY. For consistency, enable that option everywhere. After this series is applied, we can increase SPL_MAX_SIZE for H6 and newer SoCs, both 32-bit (e.g. A50, T113) and 64-bit. I did not do that yet because there is some discussion to be had about the correct value: it must be adjusted to guarantee return-to-FEL functionality, and the exact adjustment depends on the sunxi-fel tool implementation. Changes in v3: - Rebased and collected tags Changes in v2: - Disable padding from SPL_PAD_TO - Rely on binman min-size instead of using explicit offsets - Use Kconfig for firmware addresses instead of an #ifdef staircase Samuel Holland (4): sunxi: spl: Disable padding from SPL_PAD_TO sunxi: binman: Move BL31 and SCP firmware addresses to Kconfig sunxi: binman: Support FIT generation for 32-bit SoCs sunxi: Enable SPL FIT loading for 32-bit SoCs arch/arm/Kconfig | 1 + arch/arm/dts/sunxi-u-boot.dtsi | 39 ++++++++++++++++++---------------- arch/arm/mach-sunxi/Kconfig | 17 +++++++++++++++ common/spl/Kconfig | 6 ++---- 4 files changed, 41 insertions(+), 22 deletions(-) -- 2.41.0

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[PATCH v2 00/30] Fix issues with QSPI and OSPI compare failures
by Tejas Bhumkar 29 Jan '24

29 Jan '24

A set of patches has been developed to resolve concerns regarding data integrity failures in QSPI and OSPI for the Versal, Versal NET, Zynq, and ZynqMP platforms. The series has undergone testing with flashes on the default setup, and comprehensive testing is currently underway to test the series with all available flash parts. These patches are built upon the v5 series, which can be found at the following link: https://lore.kernel.org/all/20231201031839.239567-1-venkatesh.abbarapu@amd.… Changes in v2: - Removed the SPI_NOR_HAS_TB flag for gd25lx256e and is25wx256 flashes since it already exists in a tree. Algapally Santosh Sagar (1): mtd: spi-nor-ids: Add support for W25Q02NW Ashok Reddy Soma (10): mtd: spi-nor: Enable mt35xu512aba_fixups for all mt35xx flashes mtd: spi-nor: Add support for cross die read in dual flash configuration mtd: spi-nor: Enable DTR octal flash program mtd: spi-nor: Send write disable cmd after every write enable mtd: spi-nor: Check SNOR_F_IO_MODE_EN_VOLATILE only if SFDP is enabled spi: cadence_qspi: Set tshsl_ns to at least one sclk_ns spi: cadence_qspi: Clean up registers in init spi: cadence_qspi: Initialize read and write watermark registers spi: cadence_qspi: Enable ECO bit for higher frequencies spi: cadence_qspi: Write aligned byte length to ahbbase T Karthik Reddy (9): mtd: spi-nor: Add config to enable flash DTR mtd: spi-nor-core: Set dummy buswidth equal to data buswidth spi: mtd: Use split reads if multi-die flag is set mtd: spi-nor: program quad enable bit for winbond flashes spi: cadence_qspi: Setup ddr mode in cadence qspi driver spi: cadence-qspi: Switch SDR/DTR using SPI_FLASH_DTR_ENABLE config spi: cadence_ospi_versal: ospi ddr changes in cadence ospi versal driver spi: cadence_qspi: Add spi mem dtr support ops mtd: spi-nor: Add block protection support for micron flashes Tejas Bhumkar (5): arm64: versal: Enable defconfig for Micron octal flashes mtd: spi-nor: Update erase operation function spi: cadence_qspi: Fix versal ospi indirect write timed out issue arm64: versal: Enable soft reset support for xspi flashes arm64: versal: Enable octal DTR mode Venkatesh Yadav Abbarapu (5): mtd: spi-nor: Update block protection flags for flash parts mtd: spi-nor: Add support for locking on Macronix nor flashes mtd: spi-nor: Add support for locking on ISSI nor flashes mtd: spi-nor: Add support for locking on GIGADEVICE nor flashes mtd: spi-nor: Add support for locking on Spansion nor flashes configs/xilinx_versal_virt_defconfig | 4 + drivers/mtd/spi/Kconfig | 7 + drivers/mtd/spi/sf_internal.h | 8 + drivers/mtd/spi/spi-nor-core.c | 2028 +++++++++++++++++++++++--- drivers/mtd/spi/spi-nor-ids.c | 34 +- drivers/spi/cadence_ospi_versal.c | 77 +- drivers/spi/cadence_qspi.c | 403 ++++- drivers/spi/cadence_qspi.h | 71 + drivers/spi/cadence_qspi_apb.c | 107 +- include/linux/mtd/spi-nor.h | 22 + include/spi.h | 4 +- 11 files changed, 2541 insertions(+), 224 deletions(-) -- 2.27.0

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[PATCH v2 0/9] mtd: spi-nor: Add support for Infineon S28HS02GT
by tkuw584924＠gmail.com 29 Jan '24

29 Jan '24

From: Takahiro Kuwano <Takahiro.Kuwano(a)infineon.com> Infineon S28HS02GT is 1.8V, 2Gb (256MB) NOR Flash memory with Octal interface. It is a dual-die package parts and has same features with existing S28 series. The goal of this series of patches is to add S28HS02GT support. Before adding device ID to the table, some reworks are done to simplify the support structure for all other S25Hx-T and S28Hx-T families. Tested newly added S28HS02GT and other S25Hx-T and S28Hx-T devices on Zynq-7000 platform with Infineon SPI controller. Only summary datasheet is available on web. https://www.infineon.com/dgdl/Infineon-S28HS02GT_S28HS04GT_S28HL02GT_S28HL0… Please send an email to me for full version of the datasheet. Changes in v2: - Rebased Takahiro Kuwano (9): mtd: spi-nor-core: Clean up macros for Infineon(Cypress) S25 and S28 mtd: spi-nor-core: Consolidate non-uniform erase helpers for S25 and S28 mtd: spi-nor-core: Rework spansion_read_any_reg() to support Octal DTR mode mtd: spi-nor-core: Use CLPEF(0x82) as alternative to CLSR(0x30) for S25 and S28 mtd: spi-nor-core: Rework s25_mdp_ready() to support Octal DTR mode mtd: spi-nor-core: Consolidate setup() hook for Infineon(Cypress) S25 and S28 mtd: spi-nor-core: Consolidate post_bfpt_fixup() for Infineon(Cypress) S25 and S28 mtd: spi-nor-core: Rework spi_nor_cypress_octal_dtr_enable() mtd: spi-nor-ids: Add Infineon(Cypress) s28hs02gt ID drivers/mtd/spi/spi-nor-core.c | 224 +++++++++++++-------------------- drivers/mtd/spi/spi-nor-ids.c | 1 + include/linux/mtd/spi-nor.h | 14 +-- 3 files changed, 91 insertions(+), 148 deletions(-) -- 2.34.1

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