September 2022 - U-Boot

[PATCH] xilinx: versal: Remove unused comments from xilinx_versal.h
by Michal Simek 21 Sep '22

21 Sep '22

Couple of options have been moved to Kconfig but comments stayed in header that's why remove them. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- include/configs/xilinx_versal.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 971bd69dec8d..8caf5394ed46 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -23,10 +23,6 @@ EFI_GUID(0x20c5fba5, 0x0171, 0x457f, 0xb9, 0xcd, \ 0xf5, 0x12, 0x9c, 0xd0, 0x72, 0x28) -/* Miscellaneous configurable options */ - -/* Console I/O Buffer Size */ - #if defined(CONFIG_CMD_DFU) #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_THOR_RESET_OFF -- 2.36.1

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[PATCH] cmd: pxe: add alias devicetree-overlay for fdtoverlays
by Edoardo Tomelleri 21 Sep '22

21 Sep '22

This adds keyword devicetree-overlay as an alias for fdtoverlays in extlinux (sysboot) and pxe to better follow the Boot Loader Specification, improves documentation around them by adding an example for both fdtoverlays and devicetree-overlay and the environment variable required for this feature. Signed-off-by: Edoardo Tomelleri <e.tomell(a)gmail.com> --- boot/pxe_utils.c | 2 ++ doc/README.pxe | 4 ++++ doc/develop/distro.rst | 26 ++++++++++++++++++++++++++ 3 files changed, 32 insertions(+) diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index a364fa8bb5..d5c215ae2c 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -380,6 +380,7 @@ err: /** * label_boot_fdtoverlay() - Loads fdt overlays specified in 'fdtoverlays' + * or 'devicetree-overlay' * * @ctx: PXE context * @label: Label to process @@ -809,6 +810,7 @@ static const struct token keywords[] = { {"devicetreedir", T_FDTDIR}, {"fdtdir", T_FDTDIR}, {"fdtoverlays", T_FDTOVERLAYS}, + {"devicetree-overlay", T_FDTOVERLAYS}, {"ontimeout", T_ONTIMEOUT,}, {"ipappend", T_IPAPPEND,}, {"background", T_BACKGROUND,}, diff --git a/doc/README.pxe b/doc/README.pxe index 75caa01c4a..14aa078d52 100644 --- a/doc/README.pxe +++ b/doc/README.pxe @@ -163,6 +163,8 @@ fdtoverlays <path> [...] - if this label is chosen, use tftp to retrieve the DT and then applied in the load order to the fdt blob stored at the address indicated in the fdt_addr_r environment variable. +devicetree-overlay <path> [...] - alias for fdtoverlays, see above. + kaslrseed - set this label to request random number from hwrng as kaslr seed. append <string> - use <string> as the kernel command line when booting this @@ -178,6 +180,8 @@ fdt <path> - if this label is chosen, use tftp to retrieve the fdt blob the fdt_addr_r environment variable, and that address will be passed to bootm. +devicetree <path> - alias for fdt, see above. + fdtdir <path> - if this label is chosen, use tftp to retrieve a fdt blob relative to <path>. If the fdtfile environment variable is set, <path>/<fdtfile> is retrieved. Otherwise, the diff --git a/doc/develop/distro.rst b/doc/develop/distro.rst index 3ee3dac6a2..920e173548 100644 --- a/doc/develop/distro.rst +++ b/doc/develop/distro.rst @@ -81,6 +81,8 @@ as specified at BootLoaderSpec_: * Does not document the fdtdir option, which automatically selects the DTB to pass to the kernel. +See also doc/README.pxe under 'pxe file format'. + One example extlinux.conf generated by the Fedora installer is:: # extlinux.conf generated by anaconda @@ -115,6 +117,25 @@ One example extlinux.conf generated by the Fedora installer is:: fdtdir /boot/dtb-3.16.0-0.rc6.git1.1.fc22.armv7hl+lpae +One example of hand-crafted extlinux.conf:: + + menu title Select kernel + timeout 100 + + label Arch with uart devicetree overlay + kernel /arch/Image.gz + initrd /arch/initramfs-linux.img + fdt /dtbs/arch/board.dtb + fdtoverlays /dtbs/arch/overlay/uart0-gpio0-1.dtbo + append console=ttyS0,115200 console=tty1 rw root=UUID=fc0d0284-ca84-4194-bf8a-4b9da8d66908 + + label Arch with uart devicetree overlay but with Boot Loader Specification keys + kernel /arch/Image.gz + initrd /arch/initramfs-linux.img + devicetree /dtbs/arch/board.dtb + devicetree-overlay /dtbs/arch/overlay/uart0-gpio0-1.dtbo + append console=ttyS0,115200 console=tty1 rw root=UUID=fc0d0284-ca84-4194-bf8a-4b9da8d66908 + Another hand-crafted network boot configuration file is:: TIMEOUT 100 @@ -214,6 +235,11 @@ fdt_addr_r: A size of 1MB for the FDT/DTB seems reasonable. +fdtoverlay_addr_r: + Mandatory. The location in RAM where DTB overlays will be temporarily + stored and then applied in the load order to the fdt blob stored at the + address indicated in the fdt_addr_r environment variable. + fdtfile: Mandatory. the name of the DTB file for the specific board for instance the espressobin v5 board the value is "marvell/armada-3720-espressobin.dtb" -- 2.37.3

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[PATCH] configs: imx8mm*: Enable CONFIG_ARMV8_CRYPTO support
by Loic Poulain 21 Sep '22

21 Sep '22

Which speed up sha1/sha256 operations, about 10x faster with a imx8mm evk for a 20MiB kernel hash verification (12ms vs 165ms). Signed-off-by: Loic Poulain <loic.poulain(a)linaro.org> --- configs/imx8mm-cl-iot-gate-optee_defconfig | 1 + configs/imx8mm-cl-iot-gate_defconfig | 1 + configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 + configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 + configs/imx8mm-mx8menlo_defconfig | 1 + configs/imx8mm_beacon_defconfig | 1 + configs/imx8mm_data_modul_edm_sbc_defconfig | 1 + configs/imx8mm_evk_defconfig | 1 + configs/imx8mm_evk_fspi_defconfig | 1 + configs/imx8mm_venice_defconfig | 1 + 10 files changed, 10 insertions(+) diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index 9ab2173..b222756 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index 73d9388..6186cad 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_ARMV8_CRYPTO=y CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index d3e0b05..6dfe027 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 29addb5..b47773f 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index 702162f..e3b94dc 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 CONFIG_SPL=y +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0xFFFFDE00 CONFIG_SYS_LOAD_ADDR=0x40480000 diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index e37ce01..467e7d2 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_LTO=y CONFIG_FIT=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index b246fbd..deca8f6 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x30370090 CONFIG_SPL=y +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0xFFFC0000 CONFIG_IMX_BOOTAUX=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 7bcedcd..1f30467 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index 21fd7e0..3331c1a 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_ARMV8_CRYPTO=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 2a44bf6..7bf805f 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_ARMV8_CRYPTO=y CONFIG_ENV_OFFSET_REDUND=0xff8000 CONFIG_SYS_LOAD_ADDR=0x48200000 CONFIG_SYS_MEMTEST_START=0x40000000 -- 2.7.4

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Please pull u-boot-marvell/next
by Stefan Roese 20 Sep '22

20 Sep '22

Hi Tom, please pull these Marvell patches into next: ---------------------------------------------------------------- - Enable CONFIG_TIMER for all Kirkwood / MVEBU boards (Stefan) - u-boot-spl.kwb/SPL: Add / improve size limit setup / detection (Pali) - mvebu: theadorable: Misc updates in defconfig und dts (Stefan) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=264&view=results Thanks, Stefan The following changes since commit e9a1ff9724348408144c7f1c5b5cc26130ba46e5: Merge branch 'master' into next (2022-09-19 16:07:12 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-marvell.git next for you to fetch changes up to 7a6102a6133a1f7a368c91626bb1707bed2bac45: kirkwood: lsxl: Sync defconfigs (2022-09-20 06:39:43 +0200) ---------------------------------------------------------------- Pali Rohár (3): Makefile: Add missing CONFIG_BOARD_SIZE_LIMIT check for u-boot-spl.kwb arm: mvebu: turris_omnia: Add CONFIG_BOARD_SIZE_LIMIT arm: mvebu: Add default SPL_SIZE_LIMIT for 32-bit SoCs Stefan Roese (9): arm: mvebu: theadorable: Misc defconfig changes arm: mvebu: theadorable: Update eth & mdio DT nodes timer: orion-timer: Add support for other Armada SoC's timer: orion-timer: Add timer_get_boot_us() for BOOTSTAGE support arm: mvebu: Use CONFIG_TIMER on all MVEBU & KIRKWOOD platforms arm: mvebu: dts: Makefile: Compile Armada 375 dtb in a separate step arm: mvebu: dts: armada-375.dtsi: Add timer0 & timer1 arm: mvebu: dts: mvebu-u-boot.dtsi: Add "u-boot, dm-pre-reloc" to timer DT node kirkwood: lsxl: Sync defconfigs Makefile | 1 + arch/arm/Kconfig | 4 ++ arch/arm/dts/Makefile | 6 +- arch/arm/dts/armada-375.dtsi | 4 +- arch/arm/dts/armada-xp-theadorable.dts | 27 ++++---- arch/arm/dts/mvebu-u-boot.dtsi | 11 ++++ arch/arm/mach-mvebu/include/mach/config.h | 5 -- common/spl/Kconfig | 1 + configs/lschlv2_defconfig | 2 - configs/lsxhl_defconfig | 2 - configs/theadorable_debug_defconfig | 3 + configs/turris_omnia_defconfig | 2 + drivers/timer/Kconfig | 5 +- drivers/timer/orion-timer.c | 103 ++++++++++++++++++++++++++---- 14 files changed, 137 insertions(+), 39 deletions(-)

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[PULL next] u-boot-at91-2023.01-a
by Eugen.Hristev＠microchip.com 20 Sep '22

20 Sep '22

Hello Tom, Please pull tag u-boot-2023.01-a , the first set of new at91 features for the next cycle 2023.01 . This feature set includes the important update on PIO4 pinctrl driver that solves a long time mismatch between Linux and U-boot, related on the unification of pinctrl and gpio driver support, now respecting the pinctrl bindings ABI; and also support for pinctrl subnodes. The feature set also adds support for PDA screen detection for sam9x60_curiosity board , one fix for SD-Card reinsertion and one fix for sam9x60 clocks. Thanks, Eugen The following changes since commit b6c50e5831f6ce3800d4b3cf3c7aa35dde8c48d9: Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-watchdog into next (2022-09-18 08:34:31 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-at91.git tags/u-boot-at91-2023.01-a for you to fetch changes up to 7086defa048cc5303291b592192a18d69c6510cf: pinctrl: at91-pio4: Add support for pinctrl config subnodes (2022-09-19 09:51:04 +0300) ---------------------------------------------------------------- First set of u-boot-at91 features for the 2023.01 cycle ---------------------------------------------------------------- Durai Manickam KR (3): configs: sama9x60_curiosity: add onewire and eeprom drivers board: sam9x60_curiosity: add pda detect call at init time ARM: dts: at91: sam9x60_curiosity: add onewire support Mihai Sain (1): clk: at91: sam9x60: change parent clock from mck_pres to mck_div Sergiu Moga (5): mmc: atmel_sdhci: re-enable sdhci after SD Card re-insertion ARM: dts: at91: sama5: Align with Linux Devicetree ARM: dts: at91: sama7: Align with Linux Devicetree pinctrl: at91-pio4: Bind GPIO driver to the pinctrl DT node pinctrl: at91-pio4: Add support for pinctrl config subnodes arch/arm/dts/at91-sam9x60_curiosity.dts | 17 ++ arch/arm/dts/at91-sama5d27_giantboard.dts | 59 +++---- arch/arm/dts/at91-sama5d27_som1_ek.dts | 80 +++++---- arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi | 6 +- arch/arm/dts/at91-sama5d27_wlsom1_ek.dts | 92 +++++----- arch/arm/dts/at91-sama5d2_icp.dts | 134 +++++++------- arch/arm/dts/at91-sama5d2_ptc_ek.dts | 98 ++++++----- arch/arm/dts/at91-sama5d2_xplained.dts | 204 +++++++++++----------- arch/arm/dts/at91-sama7g5ek-u-boot.dtsi | 2 +- arch/arm/dts/at91-sama7g5ek.dts | 85 +++++---- arch/arm/dts/sama5d2.dtsi | 9 +- arch/arm/dts/sama5d27_som1.dtsi | 94 +++++----- arch/arm/dts/sama5d27_wlsom1.dtsi | 54 +++--- arch/arm/dts/sama7g5.dtsi | 16 +- board/atmel/sam9x60_curiosity/sam9x60_curiosity.c | 4 + configs/sam9x60_curiosity_mmc_defconfig | 4 + drivers/clk/at91/sam9x60.c | 4 +- drivers/gpio/atmel_pio4.c | 2 - drivers/mmc/atmel_sdhci.c | 12 ++ drivers/pinctrl/pinctrl-at91-pio4.c | 138 +++++++++++++-- 20 files changed, 631 insertions(+), 483 deletions(-)

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Pull request: u-boot-imx u-boot-imx-20220919
by Stefano Babic 20 Sep '22

20 Sep '22

Hi Tom, please pull from u-boot-imx, thanks! The following changes since commit 1977d72a69f3c8d97bd25a86a6be4da27cde3724: Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2022-09-18 08:27:23 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-20220919 for you to fetch changes up to cc74cab86a5f32db93a9f0dc7bc46fa5e83f4f3e: bsh: imx6ulz_smm_m2: Add imx6ulz BSH SMM M2 boards (2022-09-18 22:56:18 +0200) ---------------------------------------------------------------- u-boot-imx-20220919 ------------------- CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13500 - Fix imx8mn-beacon-kit-u-boot - Merged Purism - imxrt1170 (already merged in u-boot-imx) - Fixes in crypto FSL - Toradex : fixes Verdin - Serial Driver: fixes when not used as console - DH Boards : fixes + USB - Fix CONFIG_SYS_MALLOC_F_LEN (Kconfig) - Add imx6ulz_smm_m2 ---------------------------------------------------------------- Adam Ford (1): arm: dts: imx8mn-beacon-kit-u-boot: Fix broken booting Angus Ainslie (1): board: purism: add the Purism Librem5 phone Denys Drozdov (2): verdin-imx8mm: do not save environment when it's nowhere verdin-imx8mp: do not save environment when it's nowhere Fabio Estevam (1): MAINTAINERS: imx: Add an entry for the serial driver Gaurav Jain (1): crypto/fsl: fsl_hash: Fix crash in flush dcache Jesse Taube (8): imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header ARM: dts: imx: add i.MXRT1170-EVK support dt-bindings: imx: Add clock binding for i.MXRT1170 clk: imx: Add i.MXRT11xx pllv3 variant clk: imx: Add initial support for i.MXRT1170 clock driver RAM: Add changes for i.MXRT11xx series ARM: imxrt1170_defconfig: Add i.MXRT1170 defconfig Johannes Schneider (2): serial: mxc: enable the RX pipeline serial: mxc: have putc use the TXFIFO Marcel Ziswiler (5): imx: romapi: fix spurious ampersand in address print verdin-imx8mm: verdin-imx8mp: update env memory layout verdin-imx8mm: prepare for optional job ring driver model verdin-imx8mm: improve and extend boot devices verdin-imx8mm: various config additions and improvements Marek Vasut (13): doc: imx: habv4: Add Secure Boot guide for i.MX8M SPL targets ARM: imx: Enable USB ethernet on i.MX8M Plus DHCOM ARM: dts: imx: Add HW variant details to i.MX8M Plus DHCOM PDK2 ARM: dts: imx: Drop Atheros PHY header from i.MX8M Plus DHCOM PDK2 ARM: dts: imx: Add SoM compatible to i.MX8M Plus DHCOM PDK2 ARM: dts: imx: Rename imx8mp-dhcom{-pdk2,}-boot.dtsi ARM: dts: imx: Adjust ECSPI1 pinmux on i.MX8M Plus DHCOM ARM: dts: imx: Fix I2C5 GPIO assignment on i.MX8M Plus DHCOM ARM: imx: dh-imx6: Increase SF erase area for u-boot update imx8m: ddrphy_utils: Remove unused file ARM: imx: Update DDR frequency on i.MX8M Plus DHCOM ARM: imx: Enable SPL GPIO hog on i.MX8M Plus DHCOM ARM: imx: Update Data Modul i.MX8M Mini eDM SBC DRAM timing Michael Trimarchi (1): bsh: imx6ulz_smm_m2: Add imx6ulz BSH SMM M2 boards Peng Fan (1): Kconfig: enlarge CONFIG_SYS_MALLOC_F_LEN Tim Harvey (1): board: gateworks: venice: add fixup for GW73xx-C+ Kconfig | 3 +- MAINTAINERS | 1 + arch/arm/dts/Makefile | 7 +- arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi | 35 +++ arch/arm/dts/imx6ulz-bsh-smm-m2.dts | 146 +++++++++ arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 4 + arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi | 137 +------- arch/arm/dts/imx8mp-dhcom-pdk2.dts | 9 +- arch/arm/dts/imx8mp-dhcom-som.dtsi | 14 +- arch/arm/dts/imx8mp-dhcom-u-boot.dtsi | 141 +++++++++ arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi | 24 ++ arch/arm/dts/imx8mq-librem5-r4.dts | 35 +++ arch/arm/dts/imx8mq-librem5.dtsi | 1255 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imxrt1170-evk-u-boot.dtsi | 94 ++++++ arch/arm/dts/imxrt1170-evk.dts | 250 +++++++++++++++ arch/arm/dts/imxrt1170-pinfunc.h | 1561 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imxrt1170.dtsi | 257 +++++++++++++++ arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/mach-imx/imx8m/Kconfig | 9 + arch/arm/mach-imx/imxrt/Kconfig | 9 + arch/arm/mach-imx/imxrt/soc.c | 2 + arch/arm/mach-imx/mx6/Kconfig | 12 + arch/arm/mach-imx/spl_imx_romapi.c | 2 +- board/bsh/imx6ulz_smm_m2/Kconfig | 12 + board/bsh/imx6ulz_smm_m2/MAINTAINERS | 6 + board/bsh/imx6ulz_smm_m2/Makefile | 6 + board/bsh/imx6ulz_smm_m2/README | 67 ++++ board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c | 53 ++++ board/bsh/imx6ulz_smm_m2/spl.c | 130 ++++++++ board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c | 45 +-- board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c | 40 +-- board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c | 10 +- board/freescale/imxrt1170-evk/Kconfig | 22 ++ board/freescale/imxrt1170-evk/MAINTAINERS | 7 + board/freescale/imxrt1170-evk/Makefile | 6 + board/freescale/imxrt1170-evk/imximage.cfg | 31 ++ board/freescale/imxrt1170-evk/imxrt1170-evk.c | 80 +++++ board/gateworks/venice/eeprom.c | 7 + board/gateworks/venice/eeprom.h | 3 + board/gateworks/venice/venice.c | 43 ++- board/purism/librem5/Kconfig | 15 + board/purism/librem5/MAINTAINERS | 8 + board/purism/librem5/Makefile | 13 + board/purism/librem5/imximage-8mq-lpddr4.cfg | 9 + board/purism/librem5/librem5.c | 425 +++++++++++++++++++++++++ board/purism/librem5/librem5.h | 181 +++++++++++ board/purism/librem5/lpddr4_timing.c | 1324 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/purism/librem5/lpddr4_timing_b0.c | 1191 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/purism/librem5/spl.c | 592 +++++++++++++++++++++++++++++++++++ board/toradex/verdin-imx8mm/spl.c | 17 +- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 3 - board/toradex/verdin-imx8mp/verdin-imx8mp.c | 3 - configs/imx6ulz_smm_m2_defconfig | 80 +++++ configs/imx8mp_dhcom_pdk2_defconfig | 9 +- configs/imxrt1170-evk_defconfig | 70 +++++ configs/librem5_defconfig | 152 +++++++++ configs/verdin-imx8mm_defconfig | 38 ++- configs/verdin-imx8mp_defconfig | 2 +- doc/board/index.rst | 1 + doc/board/purism/index.rst | 9 + doc/board/purism/librem5.rst | 60 ++++ doc/imx/habv4/csf_examples/mx8m/csf.sh | 77 +++++ doc/imx/habv4/csf_examples/mx8m/csf_fit.txt | 36 +++ doc/imx/habv4/csf_examples/mx8m/csf_spl.txt | 33 ++ doc/imx/habv4/guides/mx8m_spl_secure_boot.txt | 265 ++++++++++++++++ drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imxrt1170.c | 221 +++++++++++++ drivers/clk/imx/clk-pllv3.c | 56 +++- drivers/clk/imx/clk.h | 1 + drivers/crypto/fsl/fsl_hash.c | 22 +- drivers/ddr/imx/imx8m/ddrphy_utils.c | 369 ---------------------- drivers/ram/imxrt_sdram.c | 9 + drivers/serial/serial_mxc.c | 15 +- include/configs/dh_imx6.h | 2 +- include/configs/imx6ulz_smm_m2.h | 78 +++++ include/configs/imxrt1170-evk.h | 29 ++ include/configs/librem5.h | 95 ++++++ include/configs/verdin-imx8mm.h | 10 +- include/configs/verdin-imx8mp.h | 10 +- include/dt-bindings/clock/imxrt1170-clock.h | 48 +++ include/dt-bindings/memory/imxrt-sdram.h | 1 + 82 files changed, 9561 insertions(+), 611 deletions(-) create mode 100644 arch/arm/dts/imx6ulz-bsh-smm-m2-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ulz-bsh-smm-m2.dts create mode 100644 arch/arm/dts/imx8mp-dhcom-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mq-librem5-r4-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mq-librem5-r4.dts create mode 100644 arch/arm/dts/imx8mq-librem5.dtsi create mode 100644 arch/arm/dts/imxrt1170-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imxrt1170-evk.dts create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h create mode 100644 arch/arm/dts/imxrt1170.dtsi create mode 100644 board/bsh/imx6ulz_smm_m2/Kconfig create mode 100644 board/bsh/imx6ulz_smm_m2/MAINTAINERS create mode 100644 board/bsh/imx6ulz_smm_m2/Makefile create mode 100644 board/bsh/imx6ulz_smm_m2/README create mode 100644 board/bsh/imx6ulz_smm_m2/imx6ulz_smm_m2.c create mode 100644 board/bsh/imx6ulz_smm_m2/spl.c create mode 100644 board/freescale/imxrt1170-evk/Kconfig create mode 100644 board/freescale/imxrt1170-evk/MAINTAINERS create mode 100644 board/freescale/imxrt1170-evk/Makefile create mode 100644 board/freescale/imxrt1170-evk/imximage.cfg create mode 100644 board/freescale/imxrt1170-evk/imxrt1170-evk.c create mode 100644 board/purism/librem5/Kconfig create mode 100644 board/purism/librem5/MAINTAINERS create mode 100644 board/purism/librem5/Makefile create mode 100644 board/purism/librem5/imximage-8mq-lpddr4.cfg create mode 100644 board/purism/librem5/librem5.c create mode 100644 board/purism/librem5/librem5.h create mode 100644 board/purism/librem5/lpddr4_timing.c create mode 100644 board/purism/librem5/lpddr4_timing_b0.c create mode 100644 board/purism/librem5/spl.c create mode 100644 configs/imx6ulz_smm_m2_defconfig create mode 100644 configs/imxrt1170-evk_defconfig create mode 100644 configs/librem5_defconfig create mode 100644 doc/board/purism/index.rst create mode 100644 doc/board/purism/librem5.rst create mode 100644 doc/imx/habv4/csf_examples/mx8m/csf.sh create mode 100644 doc/imx/habv4/csf_examples/mx8m/csf_fit.txt create mode 100644 doc/imx/habv4/csf_examples/mx8m/csf_spl.txt create mode 100644 doc/imx/habv4/guides/mx8m_spl_secure_boot.txt create mode 100644 drivers/clk/imx/clk-imxrt1170.c delete mode 100644 drivers/ddr/imx/imx8m/ddrphy_utils.c create mode 100644 include/configs/imx6ulz_smm_m2.h create mode 100644 include/configs/imxrt1170-evk.h create mode 100644 include/configs/librem5.h create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, 82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

3 2

[PATCH 00/12] Puma RK3399 migration to TPL and numerous fixes
by Quentin Schulz 20 Sep '22

20 Sep '22

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> Puma RK3399 SoM struggled for a few releases already to boot because the SPL was too big. Therefore, let's migrate to TPL like most RK3399-boards already did a few releases ago. This also fixes numerous issues around fallback booting (U-Boot proper corrupted on the storage medium from where TPL/SPL was loaded) and default order of boot targets. It also forces the environment storage medium to be the same as the one from which U-Boot proper was loaded, for a more consistent user experience. The environment can also be stored on SPI flash now. Finally some cleanup and the migration of the flashing instructions to u-boot-rockchip.bin and u-boot-rockchip-spi.bin. A small patch for Lion RK3368 also, for migrating the flashing instructions to u-boot-rockchip.bin. Patch 1/12 rockchip: puma-rk3399: fix boot_targets swap depending on U-Boot proper load medium depends on https://lore.kernel.org/u-boot/20220715151552.953654-1-foss+uboot@0leil.net/ https://lore.kernel.org/u-boot/20220715151552.953654-2-foss+uboot@0leil.net/ Patch 2/12 rockchip: puma-rk3399: use gpio-hog instead of fixed-regulator for enabling eMMC/SPI-NOR depends on https://lore.kernel.org/u-boot/20220712154422.265925-2-foss+uboot@0leil.net/ Patch 5/12 rockchip: puma-rk3399: load environment from same MMC as used for loading U-Boot proper depends on https://lore.kernel.org/u-boot/20220715151552.953654-1-foss+uboot@0leil.net/ Patch 7/12 rockchip: puma-rk3399: load environment from same medium as one used to load U-Boot proper depends on https://lore.kernel.org/u-boot/20220715151552.953654-1-foss+uboot@0leil.net/ https://lore.kernel.org/u-boot/20220715151552.953654-2-foss+uboot@0leil.net/ Patches {10,11,12}/12 depend on the following patch series: https://lore.kernel.org/u-boot/20220722113505.3875669-1-foss+uboot@0leil.ne… Cheers, Quentin Quentin Schulz (12): rockchip: puma-rk3399: fix boot_targets swap depending on U-Boot proper load medium rockchip: puma-rk3399: use gpio-hog instead of fixed-regulator for enabling eMMC/SPI-NOR rockchip: puma-rk3399: allow non-SD-Card-loaded SPL to load U-Boot proper from SD-Card rockchip: puma-rk3399: remove unused default ENV_OFFSET for SPI flashes rockchip: puma-rk3399: load environment from same MMC as used for loading U-Boot proper rockchip: puma-rk3399: allow loading environment from SPI-NOR flash rockchip: puma-rk3399: load environment from same medium as one used to load U-Boot proper rockchip: puma-rk3399: remove useless CONFIG_SYS_SPI_U_BOOT_OFFS rockchip: puma-rk3399: migrate to TPL rockchip: puma-rk3399: migrate to u-boot-rockchip.bin rockchip: lion-rk3368: migrate to u-boot-rockchip.bin rockchip: puma-rk3399: migrate to u-boot-rockchip-spi.bin arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 69 ++++++++++----- board/theobroma-systems/lion_rk3368/README | 9 +- board/theobroma-systems/puma_rk3399/Kconfig | 3 - board/theobroma-systems/puma_rk3399/README | 22 ++--- .../puma_rk3399/puma-rk3399.c | 84 ++++++++++++++++--- configs/puma-rk3399_defconfig | 16 ++-- 6 files changed, 139 insertions(+), 64 deletions(-) -- 2.37.1

4 30

u-boot 2022-07 on STM32F746G-DISCO
by Waldemar Brodkorb 20 Sep '22

20 Sep '22

Hi, I am trying to run u-boot on a STM32F746G-DISCO device. I am configuring u-boot with stm32f746-disco_spl_defconfig. I use following openocd command to flash the output of the build: openocd \ -f interface/stlink.cfg -f board/stm32f7discovery.cfg \ -c "init" \ -c "reset init" \ -c "flash probe 0" \ -c "flash info 0" \ -c "flash write_image erase u-boot-spl.bin 0x08000000" \ -c "flash write_image erase u-boot-dtb.bin 0x08008000" \ -c "reset run" \ -c "shutdown" The output looks like: Open On-Chip Debugger 0.11.0 Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Warn : Interface already configured, ignoring Error: already specified hl_layout stlink Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD Info : clock speed 2000 kHz Info : STLINK V2J25M14 (API v2) VID:PID 0483:374B Info : Target voltage: 3.240633 Warn : Silicon bug: single stepping may enter pending exception handler! Info : stm32f7x.cpu: hardware has 8 breakpoints, 4 watchpoints Info : starting gdb server for stm32f7x.cpu on 3333 Info : Listening on port 3333 for gdb connections Info : Unable to match requested speed 2000 kHz, using 1800 kHz Info : Unable to match requested speed 2000 kHz, using 1800 kHz target halted due to debug-request, current mode: Thread xPSR: 0x01000000 pc: 0x080003fc msp: 0x20050000 Info : Unable to match requested speed 8000 kHz, using 4000 kHz Info : Unable to match requested speed 8000 kHz, using 4000 kHz Info : device id = 0x10016449 Info : flash size = 1024 kbytes flash 'stm32f2x' found at 0x08000000 #0 : stm32f2x at 0x08000000, size 0x00100000, buswidth 0, chipwidth 0 # 0: 0x00000000 (0x8000 32kB) not protected # 1: 0x00008000 (0x8000 32kB) not protected # 2: 0x00010000 (0x8000 32kB) not protected # 3: 0x00018000 (0x8000 32kB) not protected # 4: 0x00020000 (0x20000 128kB) not protected # 5: 0x00040000 (0x40000 256kB) not protected # 6: 0x00080000 (0x40000 256kB) not protected # 7: 0x000c0000 (0x40000 256kB) not protected STM32F7[4|5]x - Rev: Z auto erase enabled wrote 32768 bytes from file u-boot-spl.bin in 0.802971s (39.852 KiB/s) auto erase enabled wrote 491520 bytes from file u-boot-dtb.bin in 8.638284s (55.567 KiB/s) Info : Unable to match requested speed 2000 kHz, using 1800 kHz Info : Unable to match requested speed 2000 kHz, using 1800 kHz shutdown command invoked But nothing happens on the LCD nor on the serial console. I use screen /dev/ttyACM0 115200 under Linux to connect. Is ttyACM0 the wrong device to get u-boots serial output? I have only one USB cable connected between USB ST-Link and my laptop. What I am doing wrong? best regards Waldemar

3 13

[PATCH 0/4] addition of configs for rockchip based roc-pc-rk3399 board
by Manoj Sai 20 Sep '22

20 Sep '22

Patch 1/4 use preboot configuration to enable usb devices Patch 2/4 fix up USB support which can recognize any USB1.1 devices Patch 3/4 Enable crypto RNG support Patch 4/4 Set the maximum slave SPI speed to 30MHz Manoj Sai (4): configs: roc-pc-rk3399 :Enable preboot config . configs: roc-pc-rk3399:fix up USB support . configs: roc-pc-rk3399 :Enable crypto RNG support. configs: roc-pc-rk3399:Set the maximum slave SPI speed and spi flash max frequency for environment to 30MHz. configs/roc-pc-rk3399_defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.25.1

2 8

[PATCH] rockchip: rk3399: Add EAIDK-610 support
by andyshrk＠163.com 20 Sep '22

20 Sep '22

From: Andy Yan <andyshrk(a)163.com> Specification - Rockchip RK3399 - LPDDR3 4GB - TF sd scard slot - eMMC - AP6255 for WiFi + BT - Gigabit ethernet - HDMI out - 40 pin header - USB 2.0 x 2 - USB 3.0 x 1 - USB 3.0 Type-C x 1 work in otg mode - 12V DC Power supply The dts file is sync from linux-next[0]. [0]:https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree… Signed-off-by: Andy Yan <andyshrk(a)163.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi | 18 + arch/arm/dts/rk3399-eaidk-610.dts | 939 ++++++++++++++++++++++ board/rockchip/evb_rk3399/MAINTAINERS | 6 + configs/eaidk-610-rk3399_defconfig | 61 ++ 5 files changed, 1025 insertions(+) create mode 100644 arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi create mode 100644 arch/arm/dts/rk3399-eaidk-610.dts create mode 100644 configs/eaidk-610-rk3399_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7330121dba..98a336e88e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -137,6 +137,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3368) += \ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ rk3399-evb.dtb \ + rk3399-eaidk-610.dtb \ rk3399-ficus.dtb \ rk3399-firefly.dtb \ rk3399-gru-bob.dtb \ diff --git a/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi b/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi new file mode 100644 index 0000000000..a3f27566e4 --- /dev/null +++ b/arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Andy Yan <andy.yan(a)gmail.com> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; + }; +}; + +&vdd_log { + regulator-init-microvolt = <950000>; +}; diff --git a/arch/arm/dts/rk3399-eaidk-610.dts b/arch/arm/dts/rk3399-eaidk-610.dts new file mode 100644 index 0000000000..d1f343345f --- /dev/null +++ b/arch/arm/dts/rk3399-eaidk-610.dts @@ -0,0 +1,939 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "OPEN AI LAB EAIDK-610"; + compatible = "openailab,eaidk-610", "rockchip,rk3399"; + + aliases { + mmc0 = &sdio0; + mmc1 = &sdmmc; + mmc2 = &sdhci; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + key-power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = <KEY_POWER>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_pin>, <&user_led_pin>, + <&heartbeat_led_pin>, <&wlan_active_led_pin>, + <&bt_active_led_pin>; + + work_led: led-0 { + label = "blue:work"; + default-state = "on"; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + + user_led: led-1 { + label = "read:user"; + default-state = "off"; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + }; + + heartbeat_led: led-2 { + label = "green:heartbeat"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + }; + + wlan_active_led: led-3 { + label = "yellow:wlan"; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led: led-4 { + label = "blue:bt"; + gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; + + rt5651-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "realtek,rt5651-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&rt5651>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + /* For USB3.0 Port1/2 */ + vcc5v0_host1: vcc5v0-host1-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host1_en>; + regulator-name = "vcc5v0_host1"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + /* For USB2.0 Port1/2 */ + vcc5v0_host3: vcc5v0-host3-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host3_en>; + regulator-name = "vcc5v0_host3"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG2 { + regulator-name = "vcc2v8_dvp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; + + rt5651: audio-codec@1a { + compatible = "rockchip,rt5651"; + reg = <0x1a>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + hp-det-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; + spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; + +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_typec>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc_hs: endpoint { + remote-endpoint = <&u2phy0_typec_hs>; + }; + }; + + port@1 { + reg = <1>; + + usbc_ss: endpoint { + remote-endpoint = <&tcphy0_typec_ss>; + }; + }; + }; + }; + }; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vcca1v8_codec>; + bt656-supply = <&vcc_3v0>; + gpio1830-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; +}; + +&pmu_io_domains { + status = "okay"; + + pmu1830-supply = <&vcc_3v0>; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + work_led_pin: work-led-pin { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led_pin: user-led-pin { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + heartbeat_led_pin: heartbeat-led-pin { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_active_led_pin: wlan-led-pin { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_active_led_pin: bt-led-pin { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rt5651 { + rt5651_hpcon: rt5640-hpcon { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host3_en: vcc5v0-host3-en { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host1_en: vcc5v0-host1-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdio0 { + /* WiFi & BT combo module AMPAK AP6255 */ + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy0_usb3 { + orientation-switch; + port { + tcphy0_typec_ss: endpoint { + remote-endpoint = <&usbc_ss>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host3>; + status = "okay"; + }; + + port { + u2phy0_typec_hs: endpoint { + remote-endpoint = <&usbc_hs>; + }; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host3>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + usb-role-switch; + + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index 25e308d186..5be58f80f9 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -6,6 +6,12 @@ F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig +EAIDK-610 +M: Andy Yan <andy.yan(a)rock-chips.com> +S: Maintained +F: configs/eaidk-610-rk3399_defconfig +F: arch/arm/dts/rk3399-eaidk-610-u-boot.dtsi + KHADAS-EDGE M: Nick Xie <nick(a)khadas.com> S: Maintained diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig new file mode 100644 index 0000000000..b41a66fe53 --- /dev/null +++ b/configs/eaidk-610-rk3399_defconfig @@ -0,0 +1,61 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0x3F8000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-eaidk-610" +CONFIG_ROCKCHIP_RK3399=y +CONFIG_TARGET_EVB_RK3399=y +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x800800 +CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-eaidk-610.dtb" +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x2e000 +CONFIG_SPL_PAD_TO=0x7f8000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x400000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_STACK=0x400000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 +CONFIG_TPL=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y -- 2.34.1

2 1