September 2022 - U-Boot

[PATCH v2] ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlock
by Marek Vasut 22 Sep '22

22 Sep '22

Pull this LPGPR unlock into common code, since it is used in multiple systems already. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Fabio Estevam <festevam(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Ye Li <ye.li(a)nxp.com> Cc: uboot-imx <uboot-imx(a)nxp.com> --- V2: Reinstate empty board_init() in DM eDM SBC board to fix build error --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 5 +++++ arch/arm/mach-imx/imx8m/soc.c | 12 ++++++++++++ .../imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c | 17 ----------------- .../dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c | 17 ----------------- board/menlo/mx8menlo/mx8menlo.c | 17 ----------------- 5 files changed, 17 insertions(+), 51 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index ff3b9ddd9f7..29d5baaab8b 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -27,6 +27,7 @@ #define IOMUXC_GPR_BASE_ADDR 0x30340000 #define OCOTP_BASE_ADDR 0x30350000 #define ANATOP_BASE_ADDR 0x30360000 +#define SNVS_BASE_ADDR 0x30370000 #define CCM_BASE_ADDR 0x30380000 #define SRC_BASE_ADDR 0x30390000 #define GPC_BASE_ADDR 0x303A0000 @@ -113,6 +114,10 @@ #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) +#define SNVS_LPSR 0x4c +#define SNVS_LPLVDR 0x64 +#define SNVS_LPPGDR_INIT 0x41736166 + struct iomuxc_gpr_base_regs { u32 gpr[47]; }; diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index d115b25a5b6..5739546c022 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -544,6 +544,16 @@ static int imx8m_check_clock(void *ctx, struct event *event) } EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock); +static void imx8m_setup_snvs(void) +{ + /* Enable SNVS clock */ + clock_enable(CCGR_SNVS, 1); + /* Initialize glitch detect */ + writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); + /* Clear interrupt status */ + writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); +} + int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -594,6 +604,8 @@ int arch_cpu_init(void) writel(0x200, &ocotp->ctrl_clr); } + imx8m_setup_snvs(); + return 0; } diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index 6dc4e6a9a2b..dc0883002c8 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -34,22 +34,6 @@ int board_phys_sdram_size(phys_size_t *size) return 0; } -/* IMX8M SNVS registers needed for the bootcount functionality */ -#define SNVS_BASE_ADDR 0x30370000 -#define SNVS_LPSR 0x4c -#define SNVS_LPLVDR 0x64 -#define SNVS_LPPGDR_INIT 0x41736166 - -static void setup_snvs(void) -{ - /* Enable SNVS clock */ - clock_enable(CCGR_SNVS, 1); - /* Initialize glitch detect */ - writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); - /* Clear interrupt status */ - writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); -} - static void setup_mac_address(void) { unsigned char enetaddr[6]; @@ -99,7 +83,6 @@ static void setup_boot_device(void) int board_init(void) { - setup_snvs(); return 0; } diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 6f06daf86f7..9d8e19d994a 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -37,22 +37,6 @@ int board_phys_sdram_size(phys_size_t *size) return 0; } -/* IMX8M SNVS registers needed for the bootcount functionality */ -#define SNVS_BASE_ADDR 0x30370000 -#define SNVS_LPSR 0x4c -#define SNVS_LPLVDR 0x64 -#define SNVS_LPPGDR_INIT 0x41736166 - -static void setup_snvs(void) -{ - /* Enable SNVS clock */ - clock_enable(CCGR_SNVS, 1); - /* Initialize glitch detect */ - writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); - /* Clear interrupt status */ - writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); -} - static void setup_eqos(void) { struct iomuxc_gpr_base_regs *gpr = @@ -145,7 +129,6 @@ int board_init(void) { setup_eqos(); setup_fec(); - setup_snvs(); return 0; } diff --git a/board/menlo/mx8menlo/mx8menlo.c b/board/menlo/mx8menlo/mx8menlo.c index 9d3708a3637..61fc4ec85f0 100644 --- a/board/menlo/mx8menlo/mx8menlo.c +++ b/board/menlo/mx8menlo/mx8menlo.c @@ -12,24 +12,7 @@ #include <asm/mach-imx/iomux-v3.h> #include <spl.h> -#define SNVS_BASE_ADDR 0x30370000 -#define SNVS_LPSR 0x4c -#define SNVS_LPLVDR 0x64 -#define SNVS_LPPGDR_INIT 0x41736166 - -static void setup_snvs(void) -{ - /* Enable SNVS clock */ - clock_enable(CCGR_SNVS, 1); - /* Initialize glitch detect */ - writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR); - /* Clear interrupt status */ - writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR); -} - void board_early_init(void) { init_uart_clk(1); - - setup_snvs(); } -- 2.35.1

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[PATCH v9 00/15] FWU: Add FWU Multi Bank Update feature support
by Sughosh Ganu 22 Sep '22

22 Sep '22

The patchset adds support for the FWU Multi Bank Update[1] feature. Certain aspects of the Dependable Boot[2] specification have also been implemented. The FWU multi bank update feature is used for supporting multiple sets(also called banks) of firmware image(s), allowing the platform to boot from a different bank, in case it fails to boot from the active bank. This functionality is supported by keeping the relevant information in a structure called metadata, which provides information on the images. Among other parameters, the metadata structure contains information on the currect active bank that is being used to boot image(s). Functionality is being added to work with the UEFI capsule driver in u-boot. The metadata is read to gather information on the update bank, which is the bank to which the firmware images would be flashed to. On a successful completion of the update of all components, the active bank field in the metadata is updated, to reflect the bank from which the platform will boot on the subsequent boots. Currently, the feature is being enabled on the STM32MP157C-DK2 and Synquacer boards. The DK2 board boots a FIP image from a uSD card partitioned with the GPT partioning scheme, while the Synquacer board boots a FIP image from a MTD partitioned SPI NOR flash device. This feature also requires changes in a previous stage of bootloader, which parses the metadata and selects the bank to boot the image(s) from. Support has being added in tf-a(BL2 stage) for the STM32MP157C-DK2 board to boot the active bank images. These changes have been merged to the upstream tf-a repository. The patch for adding a python test for the feature has been developed, and was sent in the version 5 of the patches[3]. However, the test script depends on adding support for the feature on MTD SPI NOR devices, and that is being done as part of the Synquacer patches. Hence these set of patches do not have the test script for the feature. That will be added through the patches for adding support for the feauture on Synquacer platform. [1] - https://developer.arm.com/documentation/den0118/a [2] - https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24… [3] - https://lists.denx.de/pipermail/u-boot/2022-June/485992.html Changes since V8: * Declare the metadata struct on the stack rather than heap * Move the API's to fwu.c and only keep the DM ops in the uclass driver * Fix return codes as suggested by Simon * Change log_err to log_debug as suggested by Simon * Remove the __packed attribute on the metadata structures as suggested by Simon * Add comments to the API functions * Rename fwu_mdata_gpt_blk.c as gpt_blk.c as suggested by Simon * Use natural integer types instead of specific width integers as suggested by Simon * Fix return codes as suggested by Simon * Code cleanup of some superfluous error checks, like for dev_get_uclass_plat() function * Use blk_get_from_parent() for getting the parent of the block device containing the FWU metadata * Use STM32MP_FIP_IMAGE_GUID for the FIP GUID value as suggested by Yann * Update the logic to get the update index as suggested by Jassi * Call fwu_boottime_checks through the event interface * Move addition of the FWU Kconfig symbols and Makefile to this patch * Fixed spelling mistake in the commit message Sughosh Ganu (15): dt/bindings: Add bindings for GPT based FWU Metadata storage device FWU: Add FWU metadata structure and driver for accessing metadata FWU: Add FWU metadata access driver for GPT partitioned block devices stm32mp1: dk2: Add a node for the FWU metadata device stm32mp1: dk2: Add image information for capsule updates FWU: Add helper functions for accessing FWU metadata FWU: STM32MP1: Add support to read boot index from backup register event: Add an event for main_loop FWU: Add boot time checks as highlighted by the FWU specification FWU: Add support for the FWU Multi Bank Update feature FWU: cmd: Add a command to read FWU metadata test: dm: Add test cases for FWU Metadata uclass mkeficapsule: Add support for generating empty capsules mkeficapsule: Add support for setting OEM flags in capsule header FWU: doc: Add documentation for the FWU feature arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi | 7 + arch/arm/mach-stm32mp/include/mach/stm32.h | 5 + arch/sandbox/Kconfig | 6 + arch/sandbox/dts/test.dts | 7 +- board/sandbox/sandbox.c | 10 + board/st/stm32mp1/stm32mp1.c | 46 ++ cmd/Kconfig | 6 + cmd/Makefile | 1 + cmd/fwu_mdata.c | 79 +++ common/board_r.c | 3 + common/event.c | 3 + configs/sandbox64_defconfig | 5 +- doc/develop/uefi/fwu_updates.rst | 165 +++++ doc/develop/uefi/index.rst | 1 + doc/develop/uefi/uefi.rst | 2 + .../firmware/fwu-mdata-gpt.yaml | 32 + doc/mkeficapsule.1 | 33 +- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/fwu-mdata/Kconfig | 16 + drivers/fwu-mdata/Makefile | 8 + drivers/fwu-mdata/fwu-mdata-uclass.c | 107 ++++ drivers/fwu-mdata/gpt_blk.c | 378 +++++++++++ include/configs/stm32mp15_common.h | 4 + include/dm/uclass-id.h | 1 + include/event.h | 3 + include/fwu.h | 298 +++++++++ include/fwu_mdata.h | 67 ++ lib/Kconfig | 6 + lib/Makefile | 1 + lib/efi_loader/efi_capsule.c | 213 ++++++- lib/efi_loader/efi_setup.c | 4 +- lib/fwu_updates/Kconfig | 32 + lib/fwu_updates/Makefile | 7 + lib/fwu_updates/fwu.c | 600 ++++++++++++++++++ lib/fwu_updates/fwu_gpt.c | 115 ++++ test/dm/Makefile | 1 + test/dm/fwu_mdata.c | 149 +++++ test/dm/fwu_mdata_disk_image.h | 112 ++++ .../test_capsule_firmware_fit.py | 1 - .../test_capsule_firmware_signed_fit.py | 1 - tools/Makefile | 2 +- tools/eficapsule.h | 8 + tools/mkeficapsule.c | 109 +++- 44 files changed, 2631 insertions(+), 26 deletions(-) create mode 100644 cmd/fwu_mdata.c create mode 100644 doc/develop/uefi/fwu_updates.rst create mode 100644 doc/device-tree-bindings/firmware/fwu-mdata-gpt.yaml create mode 100644 drivers/fwu-mdata/Kconfig create mode 100644 drivers/fwu-mdata/Makefile create mode 100644 drivers/fwu-mdata/fwu-mdata-uclass.c create mode 100644 drivers/fwu-mdata/gpt_blk.c create mode 100644 include/fwu.h create mode 100644 include/fwu_mdata.h create mode 100644 lib/fwu_updates/Kconfig create mode 100644 lib/fwu_updates/Makefile create mode 100644 lib/fwu_updates/fwu.c create mode 100644 lib/fwu_updates/fwu_gpt.c create mode 100644 test/dm/fwu_mdata.c create mode 100644 test/dm/fwu_mdata_disk_image.h -- 2.34.1

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[PATCH 0/3] arm: mvebu: Add support for programming LD eFuse on Armada 385
by Pali Rohár 22 Sep '22

22 Sep '22

This patch series add support for programming LD eFuse on Armada 385. I tested it on Turris Omnia board. Armada 385 LD1 eFuse is for General Purpose Data and is already mapped to U-Boot fuse word 65. Pali Rohár (3): arm: mvebu: Add support for programming LD0 and LD1 eFuse arm: mvebu: Add support for specifying VHV_Enable GPIO arm: mvebu: turris_omnia: Specify VHV gpio for eFUSE programming arch/arm/mach-mvebu/Kconfig | 15 +++++ arch/arm/mach-mvebu/efuse.c | 83 +++++++++++++++++++++++- arch/arm/mach-mvebu/include/mach/efuse.h | 4 ++ configs/turris_omnia_defconfig | 2 + 4 files changed, 102 insertions(+), 2 deletions(-) -- 2.20.1

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[PATCH 1/2] riscv: Introduce AVAILABLE_HARTS
by Andes 22 Sep '22

22 Sep '22

From: Rick Chen <rick(a)andestech.com> In SMP all harts will register themself in available_hart during start up. Then main hart will send IPI to other harts according to this variables. But this mechanism may not guarantee that all other harts can jump to next stage. When main hart is sending IPI to other hart according to available_harts, but other harts maybe still not finish the registration. Then the SMP booting will miss some harts finally. So let it become an option and it will be enabled by default. Please refer to the discussion: https://www.mail-archive.com/u-boot@lists.denx.de/msg449997.html Signed-off-by: Rick Chen <rick(a)andestech.com> --- arch/riscv/Kconfig | 7 +++++++ arch/riscv/cpu/cpu.c | 2 ++ arch/riscv/cpu/start.S | 13 ++++++++----- arch/riscv/include/asm/global_data.h | 2 ++ arch/riscv/lib/asm-offsets.c | 2 ++ arch/riscv/lib/smp.c | 2 ++ 6 files changed, 23 insertions(+), 5 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c042506a64..32a90b83b5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -276,6 +276,13 @@ config SPL_XIP rely on lock variables (for example hart_lottery and available_harts_lock), this affects only SPL, other stages should proceed as non-XIP. +config AVAILABLE_HARTS + bool "Send IPI by available harts" + default y + help + By default, IPI sending mechanism will depend on available_harts. + If disable this, it will send IPI by CPUs node numbers of device tree. + config SHOW_REGS bool "Show registers on unhandled exception" diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 0f323b26b3..52ab02519f 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -22,12 +22,14 @@ #if !CONFIG_IS_ENABLED(XIP) u32 hart_lottery __section(".data") = 0; +#ifdef CONFIG_AVAILABLE_HARTS /* * The main hart running U-Boot has acquired available_harts_lock until it has * finished initialization of global data. */ u32 available_harts_lock = 1; #endif +#endif static inline bool supports_extension(char ext) { diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index de9d078da1..4687bca3c9 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -153,21 +153,23 @@ call_harts_early_init: SREG tp, GD_BOOT_HART(gp) #if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS la t0, available_harts_lock amoswap.w.rl zero, zero, 0(t0) +#endif wait_for_gd_init: - la t0, available_harts_lock - li t1, 1 -1: amoswap.w.aq t1, t1, 0(t0) - bnez t1, 1b - /* * Set the global data pointer only when gd_t has been initialized. * This was already set by arch_setup_gd on the boot hart, but all other * harts' global data pointers gets set here. */ mv gp, s0 +#ifdef CONFIG_AVAILABLE_HARTS + la t0, available_harts_lock + li t1, 1 +1: amoswap.w.aq t1, t1, 0(t0) + bnez t1, 1b /* register available harts in the available_harts mask */ li t1, 1 @@ -177,6 +179,7 @@ wait_for_gd_init: SREG t2, GD_AVAILABLE_HARTS(gp) amoswap.w.rl zero, zero, 0(t0) +#endif /* * Continue on hart lottery winner, others branch to diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index b3c79e1760..858594a191 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -28,8 +28,10 @@ struct arch_global_data { struct ipi_data ipi[CONFIG_NR_CPUS]; #endif #if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS ulong available_harts; #endif +#endif }; #include <asm-generic/global_data.h> diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index c4f48c8373..452dfcea97 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -17,7 +17,9 @@ int main(void) DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart)); DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr)); #if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts)); +#endif #endif return 0; diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index f8b756291f..c0f65af191 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -46,9 +46,11 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) } #if !CONFIG_IS_ENABLED(XIP) +#ifdef CONFIG_AVAILABLE_HARTS /* skip if hart is not available */ if (!(gd->arch.available_harts & (1 << reg))) continue; +#endif #endif gd->arch.ipi[reg].addr = ipi->addr; -- 2.17.1

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[PATCH v2 0/6] arm: mvebu: Support for 98DX25xx/98DX35xx (AlleyCat5)
by Chris Packham 22 Sep '22

22 Sep '22

These patches are based on Marvell's bootloader for the AlleyCat5/5X which was based on u-boot 2018.03. I've split that code into consumable chunks and dropped as much unnecessary stuff as I can. I've also tried to sync the device trees as much as possible with the support that will land in Linux 6.0 although there are still some differences Changes in v2: - Use distro boot by default - remove unnecessary SPI-NOR partitions Chris Packham (6): net: mvneta: Add support for AlleyCat5 usb: ehci: ehci-marvell: Support for marvell,ac5-ehci pinctrl: mvebu: Add AlleyCat5 support misc: mvebu: Add sample at reset driver arm: mvebu: Support for 98DX25xx/98DX35xx SoC arm: mvebu: Add RD-AC5X board arch/arm/dts/Makefile | 3 +- arch/arm/dts/ac5-98dx25xx.dtsi | 292 +++++++++++++++++++++ arch/arm/dts/ac5-98dx35xx-rd.dts | 140 ++++++++++ arch/arm/dts/ac5-98dx35xx.dtsi | 17 ++ arch/arm/mach-mvebu/Kconfig | 14 +- arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/alleycat5/Makefile | 9 + arch/arm/mach-mvebu/alleycat5/clock.c | 49 ++++ arch/arm/mach-mvebu/alleycat5/cpu.c | 129 +++++++++ arch/arm/mach-mvebu/alleycat5/soc.c | 229 ++++++++++++++++ arch/arm/mach-mvebu/arm64-common.c | 15 ++ arch/arm/mach-mvebu/include/mach/clock.h | 11 + arch/arm/mach-mvebu/include/mach/cpu.h | 4 + arch/arm/mach-mvebu/include/mach/soc.h | 4 + board/Marvell/mvebu_alleycat-5/MAINTAINERS | 6 + board/Marvell/mvebu_alleycat-5/Makefile | 3 + board/Marvell/mvebu_alleycat-5/board.c | 35 +++ configs/mvebu_ac5_rd_defconfig | 88 +++++++ drivers/misc/Kconfig | 6 + drivers/misc/Makefile | 1 + drivers/misc/mvebu_sar/Makefile | 4 + drivers/misc/mvebu_sar/ac5_sar.c | 119 +++++++++ drivers/misc/mvebu_sar/sar-uclass.c | 146 +++++++++++ drivers/net/Kconfig | 2 +- drivers/net/mvneta.c | 66 ++++- drivers/pinctrl/mvebu/Kconfig | 2 +- drivers/usb/host/Kconfig | 1 + drivers/usb/host/ehci-marvell.c | 57 +++- include/configs/mvebu_alleycat-5.h | 71 +++++ include/dm/uclass-id.h | 1 + include/fdtdec.h | 4 + include/mvebu/mvebu_chip_sar.h | 73 ++++++ include/mvebu/sar.h | 57 ++++ include/mvebu/var.h | 28 ++ include/sar-uclass.h | 23 ++ lib/fdtdec.c | 6 +- 36 files changed, 1698 insertions(+), 18 deletions(-) create mode 100644 arch/arm/dts/ac5-98dx25xx.dtsi create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts create mode 100644 arch/arm/dts/ac5-98dx35xx.dtsi create mode 100644 arch/arm/mach-mvebu/alleycat5/Makefile create mode 100644 arch/arm/mach-mvebu/alleycat5/clock.c create mode 100644 arch/arm/mach-mvebu/alleycat5/cpu.c create mode 100644 arch/arm/mach-mvebu/alleycat5/soc.c create mode 100644 arch/arm/mach-mvebu/include/mach/clock.h create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile create mode 100644 board/Marvell/mvebu_alleycat-5/board.c create mode 100644 configs/mvebu_ac5_rd_defconfig create mode 100644 drivers/misc/mvebu_sar/Makefile create mode 100644 drivers/misc/mvebu_sar/ac5_sar.c create mode 100644 drivers/misc/mvebu_sar/sar-uclass.c create mode 100644 include/configs/mvebu_alleycat-5.h create mode 100644 include/mvebu/mvebu_chip_sar.h create mode 100644 include/mvebu/sar.h create mode 100644 include/mvebu/var.h create mode 100644 include/sar-uclass.h -- 2.37.3

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Please pull u-boot-dm
by Simon Glass 21 Sep '22

21 Sep '22

Hi Tom, https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/13541 The following changes since commit 12ed6d4911ced1df099a365e0a994b54211b60f3: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb (2022-09-19 16:49:18 -0400) are available in the Git repository at: git://git.denx.de/u-boot-dm.git tags/dm-pull-21sep22 for you to fetch changes up to d64af08f19132c85422b442657920f4024b5caf7: binman: Get futility by building it (2022-09-21 10:37:47 +0200) ---------------------------------------------------------------- Fix futility bintool to run on newer distros Apply a lost patch ---------------------------------------------------------------- Marek Vasut (1): cmd: fdt: Add support for reading stringlist property values Simon Glass (1): binman: Get futility by building it cmd/fdt.c | 34 ++++++++++++++++++++++++++++------ tools/binman/bintool.py | 10 +++++++--- tools/binman/btool/futility.py | 17 +++++++++++++---- 3 files changed, 48 insertions(+), 13 deletions(-) Regards, Simon

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[PATCH] dt-bindings: nvmem: u-boot, env: add Broadcom's variant binding
by Rafał Miłecki 21 Sep '22

21 Sep '22

From: Rafał Miłecki <rafal(a)milecki.pl> Broadcom uses U-Boot for some of their recent platforms like BCM4908. They decided to use modified environment variables variables format though. Their header includes 2 extra 32 b fields at the beginning. The first field meaning is unknown, the second one stores length of env data block. Example (length 0x4000): $ hexdump -n 32 -C -s 0x40000 /dev/mtdblock0 00040000 76 6e 45 75 00 40 00 00 34 89 7a 82 49 4d 41 47 |vnEu.@..4.z.IMAG| 00040010 45 3d 4e 41 4e 44 3a 31 4d 2c 31 30 32 34 4d 00 |E=NAND:1M,1024M.| Add a custom "compatible" value to allow describing Broadcom devices properly. Signed-off-by: Rafał Miłecki <rafal(a)milecki.pl> --- Documentation/devicetree/bindings/nvmem/u-boot,env.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml b/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml index e70b2a60cb9a..6a6b223be4a0 100644 --- a/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml +++ b/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml @@ -36,6 +36,8 @@ properties: const: u-boot,env-redundant-bool - description: Two redundant blocks with active having higher counter const: u-boot,env-redundant-count + - description: Broadcom's variant with custom header + const: brcm,env reg: maxItems: 1 -- 2.34.1

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[PATCH 0/7] Use logging feature instead of FPGA_DEBUG
by Alexander Dahl 21 Sep '22

21 Sep '22

Hei hei, while working on FPGA support for a new device I discovered logging in some FPGA drivers is still done as in the old days. Bring that to what I thougt would be the currently preferred approach? Notes: Adding those Kconfig symbols in patch 3 is just to be able to build those two drivers. All drivers touched were build tested with the gcc-11.1.0-nolibc/m68k-linux toolchain. Lines with other possibly questionable output were not touched, only what seemed to be designated debug output. Greets Alex Alexander Dahl (7): fpga: altera: Use logging feature instead of FPGA_DEBUG fpga: cyclon2: Use logging feature instead of FPGA_DEBUG fpga: Add missing Kconfig symbols for old FPGA drivers fpga: ACEX1K: Use logging feature instead of FPGA_DEBUG fpga: spartan2: Use logging feature instead of FPGA_DEBUG fpga: spartan3: Use logging feature instead of FPGA_DEBUG fpga: virtex2: Use logging feature instead of FPGA_DEBUG drivers/fpga/ACEX1K.c | 22 +++++++++------------- drivers/fpga/Kconfig | 12 ++++++++++++ drivers/fpga/altera.c | 13 ++++++------- drivers/fpga/cyclon2.c | 24 ++++++++++-------------- drivers/fpga/spartan2.c | 34 +++++++++++++++------------------- drivers/fpga/spartan3.c | 34 +++++++++++++++------------------- drivers/fpga/virtex2.c | 37 +++++++++++++++---------------------- 7 files changed, 82 insertions(+), 94 deletions(-) base-commit: 0b3fe2b9777eff12ffd6735fc00291616b407622 -- 2.30.2

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[PATCH v3] binman: Get futility by building it
by Simon Glass 21 Sep '22

21 Sep '22

A binary download is not great, since it depends on libraries being present in the system. Build futility from source instead. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v3: - Drop the branch, just use master instead - Explain why we are using a mirror - Drop mention of upstream patches as they are applied Changes in v2: - Pull from github instead, to avoid needing to login / gitcookies tools/binman/bintool.py | 10 +++++++--- tools/binman/btool/futility.py | 17 +++++++++++++---- 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/tools/binman/bintool.py b/tools/binman/bintool.py index 032179a99de..a582d9d3446 100644 --- a/tools/binman/bintool.py +++ b/tools/binman/bintool.py @@ -319,7 +319,7 @@ class Bintool: return result.stdout @classmethod - def build_from_git(cls, git_repo, make_target, bintool_path): + def build_from_git(cls, git_repo, make_target, bintool_path, flags=None): """Build a bintool from a git repo This clones the repo in a temporary directory, builds it with 'make', @@ -330,6 +330,7 @@ class Bintool: make_target (str): Target to pass to 'make' to build the tool bintool_path (str): Relative path of the tool in the repo, after build is complete + flags (list of str): Flags or variables to pass to make, or None Returns: tuple: @@ -341,8 +342,11 @@ class Bintool: print(f"- clone git repo '{git_repo}' to '{tmpdir}'") tools.run('git', 'clone', '--depth', '1', git_repo, tmpdir) print(f"- build target '{make_target}'") - tools.run('make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}', - make_target) + cmd = ['make', '-C', tmpdir, '-j', f'{multiprocessing.cpu_count()}', + make_target] + if flags: + cmd += flags + tools.run(*cmd) fname = os.path.join(tmpdir, bintool_path) if not os.path.exists(fname): print(f"- File '{fname}' was not produced") diff --git a/tools/binman/btool/futility.py b/tools/binman/btool/futility.py index 75a05c2ac66..04c9aefe9b4 100644 --- a/tools/binman/btool/futility.py +++ b/tools/binman/btool/futility.py @@ -160,8 +160,17 @@ class Bintoolfutility(bintool.Bintool): Raises: Valuerror: Fetching could not be completed """ - if method != bintool.FETCH_BIN: + if method != bintool.FETCH_BUILD: return None - fname, tmpdir = self.fetch_from_drive( - '1hdsInzsE4aJbmBeJ663kYgjOQyW1I-E0') - return fname, tmpdir + + # The Chromium OS repo is here: + # https://chromium.googlesource.com/chromiumos/platform/vboot_reference/ + # + # Unfortunately this requires logging in and obtaining a line for the + # .gitcookies file. So use a mirror instead. + result = self.build_from_git( + 'https://github.com/sjg20/vboot_reference.git', + 'all', + 'build/futility/futility', + flags=['USE_FLASHROM=0']) + return result -- 2.37.3.968.ga6b4b080e4-goog

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[PATCH 1/2] arm64: zynqmp: Describe TI phy as ethernet-phy-id
by Michal Simek 21 Sep '22

21 Sep '22

TI DP83867 is using strapping based on MIO pins. Tristate setup can influce PHY address. That's why switch description with ethernet-phy-id compatible string which enable calling reset. PHY itself setups phy address after power up or reset. Reset description will be added in separate commit. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-zcu102-revA.dts | 20 +++++++++++++------- arch/arm/dts/zynqmp-zcu104-revA.dts | 18 ++++++++++++------ arch/arm/dts/zynqmp-zcu104-revC.dts | 18 ++++++++++++------ arch/arm/dts/zynqmp-zcu111-revA.dts | 18 ++++++++++++------ arch/arm/dts/zynqmp-zcu208-revA.dts | 18 ++++++++++++------ arch/arm/dts/zynqmp-zcu216-revA.dts | 19 ++++++++++++------- 6 files changed, 73 insertions(+), 38 deletions(-) diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 71c3dde4bf21..f04bc9969bd0 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -217,13 +217,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@21 { - reg = <21>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@21 { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 1418cffb2042..6df9a1343859 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -109,12 +109,18 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 7fd19ca3a8c0..0721516bd109 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -114,12 +114,18 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index e412992ff1bd..c37c4b8b6177 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -172,12 +172,18 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index c5cdd58af6ed..3e8ee429eb79 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -169,12 +169,18 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index caae16965d6f..80e7ddb97080 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -176,15 +176,20 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; - &gpio { status = "okay"; gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ -- 2.36.1

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