September 2022 - U-Boot

[PATCH] configs: stm32mp1: cleanup config file
by Patrick Delaunay 23 Sep '22

23 Sep '22

Remove the unnecessary comment after the CONFIG_SYS_BOOTM_LEN migration to Kconfig. Fixes: c45568cc4e51 ("Convert CONFIG_SYS_BOOTM_LEN to Kconfig") Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- include/configs/stm32mp13_common.h | 2 -- include/configs/stm32mp15_common.h | 2 -- 2 files changed, 4 deletions(-) diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index 3ca65ea2a37..78089b965ae 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -21,8 +21,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ SZ_256M -/* Extend size of kernel image for uncompression */ - /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 2 diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index c5412ffeb31..bd8e16bc1b9 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -21,8 +21,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ SZ_256M -/* Extend size of kernel image for uncompression */ - /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 -- 2.25.1

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[PATCH 0/4] arm: stm32mp: adapt the command stm32key for STM32MP13x
by Patrick Delaunay 23 Sep '22

23 Sep '22

And support the 2 keys for STM32MP13x - PKHTH : Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) - EDMK : Encryption/Decryption Master Key Only one key is supported for STM32MP15x - PKH : Hash of the ECC Public Key (ECDSA is the authentication algorithm) This STM32KEY command is used in STM32MP SoCs to provision the keys in the correct OTP needed to activate secure boot features: authentication and encryption. See [1] for details [1] STM32 MPU wiki https://wiki.st.com/stm32mpu/wiki/How_to_use_U-Boot_stm32key_command Patrick Delaunay (4): arm: stm32mp: add defines for BSEC_LOCK status in stm32key command arm: stm32mp: introduced read_close_status function in stm32key command arm: stm32mp: support several key in command stm32key arm: stm32mp: adapt the command stm32key for STM32MP13x arch/arm/mach-stm32mp/cmd_stm32key.c | 331 ++++++++++++++++++++------- 1 file changed, 249 insertions(+), 82 deletions(-) -- 2.25.1

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[PATCH] board: st: stm32mp1: use of correct compatible string to add partitions
by Patrick Delaunay 23 Sep '22

23 Sep '22

From: Christophe Kerello <christophe.kerello(a)foss.st.com> Current compatible string used to update SPI NAND and SPI NOR devices can lead to a wrong partitions update (for example, SPI NAND partitions added to SPI NOR node in the device tree). To avoid this wrong behavior, use jedec,spi-nor compatible string for SPI NOR devices and spi-nand compatible string for SPI NAND devices. Signed-off-by: Christophe Kerello <christophe.kerello(a)foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- board/st/stm32mp1/stm32mp1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 8c162b42a59..7dc26f850ff 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -898,8 +898,8 @@ int mmc_get_env_dev(void) int ft_board_setup(void *blob, struct bd_info *bd) { static const struct node_info nodes[] = { - { "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, }, - { "st,stm32f469-qspi", MTD_DEV_TYPE_SPINAND}, + { "jedec,spi-nor", MTD_DEV_TYPE_NOR, }, + { "spi-nand", MTD_DEV_TYPE_SPINAND}, { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, }, { "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, }, }; -- 2.25.1

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[PATCH] stm32mp: stm32prog: improve the partitioning trace
by Patrick Delaunay 23 Sep '22

23 Sep '22

Improve the partitioning trace done in command stm32prog: - remove the trace "partition: Done" when the GPT partitioning is not done - indicate the mmc instance used for each 'gpt write' command Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index c391b6c7abb..7ee4590ef26 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1090,7 +1090,6 @@ static int create_gpt_partitions(struct stm32prog_data *data) if (!buf) return -ENOMEM; - puts("partitions : "); /* initialize the selected device */ for (i = 0; i < data->dev_nb; i++) { /* create gpt partition support only for full update on MMC */ @@ -1098,6 +1097,7 @@ static int create_gpt_partitions(struct stm32prog_data *data) !data->dev[i].full_update) continue; + printf("partitions on mmc%d: ", data->dev[i].dev_id); offset = 0; rootfs_found = false; memset(buf, 0, buflen); @@ -1197,8 +1197,8 @@ static int create_gpt_partitions(struct stm32prog_data *data) sprintf(buf, "part list mmc %d", data->dev[i].dev_id); run_command(buf, 0); #endif + puts("done\n"); } - puts("done\n"); #ifdef DEBUG run_command("mtd list", 0); -- 2.25.1

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[PATCH] ARM: dts: stm32mp: alignment with v6.0-rc3
by Patrick Delaunay 23 Sep '22

23 Sep '22

Device tree alignment with Linux kernel v6.0-rc3: - ARM: dts: stm32: add support for USB2514B onboard hub on stm32mp15xx-dkx - ARM: dts: stm32: Add alternate pinmux for RCC pin - ARM: dts: stm32: Add alternate pinmux for DCMI pins - ARM: dts: stm32: Add alternate pinmux for SPI2 pins - ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15 - ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk - ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13 - ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151 Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp13-u-boot.dtsi | 10 +++-- arch/arm/dts/stm32mp131.dtsi | 28 ++++++------- arch/arm/dts/stm32mp135f-dk.dts | 4 +- arch/arm/dts/stm32mp15-pinctrl.dtsi | 64 ++++++++++++++++++++++++++--- arch/arm/dts/stm32mp151.dtsi | 7 ++-- arch/arm/dts/stm32mp15xx-dkx.dtsi | 8 ++++ 6 files changed, 91 insertions(+), 30 deletions(-) diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index 01552adb7c4..47a43649bbb 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -17,6 +17,12 @@ pinctrl0 = &pinctrl; }; + firmware { + optee { + u-boot,dm-pre-reloc; + }; + }; + /* need PSCI for sysreset during board_f */ psci { u-boot,dm-pre-proper; @@ -82,10 +88,6 @@ u-boot,dm-pre-reloc; }; -&optee { - u-boot,dm-pre-reloc; -}; - &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 84e16bb2f2b..a1c6d0d00b5 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -27,21 +27,8 @@ interrupt-parent = <&intc>; }; - scmi_sram: sram@2ffff000 { - compatible = "mmio-sram"; - reg = <0x2ffff000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2ffff000 0x1000>; - - scmi_shm: scmi_shm@0 { - compatible = "arm,scmi-shmem"; - reg = <0 0x80>; - }; - }; - firmware { - optee: optee { + optee { method = "smc"; compatible = "linaro,optee-tz"; }; @@ -151,6 +138,19 @@ interrupt-parent = <&intc>; ranges; + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index f436ffab998..e6b8ffd332c 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -31,8 +31,8 @@ #size-cells = <1>; ranges; - optee@de000000 { - reg = <0xde000000 0x2000000>; + optee@dd000000 { + reg = <0xdd000000 0x3000000>; no-map; }; }; diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index d3ed10335df..2cc9341d43d 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -151,6 +151,43 @@ }; }; + dcmi_pins_c: dcmi-2 { + pins { + pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ + <STM32_PINMUX('E', 0, AF13)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ + <STM32_PINMUX('I', 6, AF13)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, AF13)>;/* DCMI_D9 */ + bias-pull-up; + }; + }; + + dcmi_sleep_pins_c: dcmi-sleep-2 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ + <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ + <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ + <STM32_PINMUX('E', 0, ANALOG)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ + <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ + <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ + <STM32_PINMUX('I', 6, ANALOG)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ + <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ + <STM32_PINMUX('H', 7, ANALOG)>;/* DCMI_D9 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -923,6 +960,21 @@ }; }; + mco1_pins_a: mco1-0 { + pins { + pinmux = <STM32_PINMUX('A', 13, AF2)>; /* MCO1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + mco1_sleep_pins_a: mco1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 13, ANALOG)>; /* MCO1 */ + }; + }; + mco2_pins_a: mco2-0 { pins { pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ @@ -1814,30 +1866,30 @@ spi2_pins_a: spi2-0 { pins1 { - pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */ - <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */ + pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ + <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { - pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */ + pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ bias-disable; }; }; spi2_pins_b: spi2-1 { pins1 { - pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI1_SCK */ - <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */ + pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ + <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { - pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */ + pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ bias-disable; }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 767a06ef684..f0fb022fc63 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1143,10 +1143,9 @@ reg = <0x4c001000 0x400>; st,proc-id = <0>; interrupts-extended = - <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <&exti 61 1>; - interrupt-names = "rx", "tx", "wakeup"; + <&exti 61 1>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; clocks = <&rcc IPCC>; wakeup-source; status = "disabled"; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 3d36cac9ed0..5a045d7156b 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -685,6 +685,14 @@ &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3>; + }; }; &usbotg_hs { -- 2.25.1

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[PATCH 1/4] stm32mp: stm32prog: support empty flashlayout
by Patrick Delaunay 23 Sep '22

23 Sep '22

When the STM32CubeProgrammer sent a empty flashlayout.tsv file, the command stm32prog correctly parse the file but data->dev_nb = 0 and the stm32prog_devices_init operations should be skipped. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index c391b6c7abb..65e32288af7 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -1884,6 +1884,10 @@ static void stm32prog_devices_init(struct stm32prog_data *data) if (ret) goto error; + /* empty flashlayout */ + if (!data->dev_nb) + return; + /* initialize the selected device */ for (i = 0; i < data->dev_nb; i++) { ret = init_device(data, &data->dev[i]); -- 2.25.1

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[PATCH] arm: amlogic: add setbrg op to serial device
by Edoardo Tomelleri 23 Sep '22

23 Sep '22

Implement setbrg in amlogic/meson serial device with driver model similar to how the meson_uart.c driver does it in Linux. Also configure (probe) the serial device with the new reg5 register. Signed-off-by: Edoardo Tomelleri <e.tomell(a)gmail.com> --- drivers/serial/serial_meson.c | 70 +++++++++++++++++++++++++++++++++++ include/configs/meson64.h | 7 ++++ 2 files changed, 77 insertions(+) diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c index d69ec221..90c370cf 100644 --- a/drivers/serial/serial_meson.c +++ b/drivers/serial/serial_meson.c @@ -7,9 +7,11 @@ #include <dm.h> #include <errno.h> #include <fdtdec.h> +#include <linux/kernel.h> #include <linux/bitops.h> #include <linux/compiler.h> #include <serial.h> +#include <clk.h> struct meson_uart { u32 wfifo; @@ -17,6 +19,7 @@ struct meson_uart { u32 control; u32 status; u32 misc; + u32 reg5; /* New baud control register */ }; struct meson_serial_plat { @@ -42,6 +45,35 @@ struct meson_serial_plat { #define AML_UART_RX_RST BIT(23) #define AML_UART_CLR_ERR BIT(24) +/* AML_UART_REG5 bits */ +#define AML_UART_REG5_XTAL_DIV2 BIT(27) +#define AML_UART_REG5_XTAL_CLK_SEL BIT(26) /* default 0 (div by 3), 1 for no div */ +#define AML_UART_REG5_USE_XTAL_CLK BIT(24) /* default 1 (use crystal as clock source) */ +#define AML_UART_REG5_USE_NEW_BAUD BIT(23) /* default 1 (use new baud rate register) */ +#define AML_UART_REG5_BAUD_MASK 0x7fffff + +static u32 meson_calc_baud_divisor(ulong src_rate, u32 baud) +{ + /* + * Usually src_rate is 24 MHz (from crystal) as clock source for serial + * device. Since 8 Mb/s is the maximum supported baud rate, use div by 3 + * to derive baud rate. This choice is used also in meson_serial_setbrg. + */ + return DIV_ROUND_CLOSEST(src_rate / 3, baud) - 1; +} + +static void meson_serial_set_baud(struct meson_uart *uart, ulong src_rate, u32 baud) +{ + /* + * Set crystal divided by 3 (regardless of device tree clock property) + * as clock source and the corresponding divisor to approximate baud + */ + u32 divisor = meson_calc_baud_divisor(src_rate, baud); + u32 val = AML_UART_REG5_USE_XTAL_CLK | AML_UART_REG5_USE_NEW_BAUD | + (divisor & AML_UART_REG5_BAUD_MASK); + writel(val, &uart->reg5); +} + static void meson_serial_init(struct meson_uart *uart) { u32 val; @@ -59,7 +91,14 @@ static int meson_serial_probe(struct udevice *dev) { struct meson_serial_plat *plat = dev_get_plat(dev); struct meson_uart *const uart = plat->reg; + struct clk per_clk; + int ret = clk_get_by_name(dev, "baud", &per_clk); + + if (ret) + return ret; + ulong rate = clk_get_rate(&per_clk); + meson_serial_set_baud(uart, rate, CONFIG_BAUDRATE); meson_serial_init(uart); return 0; @@ -111,6 +150,36 @@ static int meson_serial_putc(struct udevice *dev, const char ch) return 0; } +static int meson_serial_setbrg(struct udevice *dev, const int baud) +{ + /* + * Change device baud rate if baud is reasonable (considering a 23 bit + * counter with an 8 MHz clock input) and the actual baud + * rate is within 2% of the requested value (2% is arbitrary). + */ + if (baud < 1 || baud > 8000000) + return -EINVAL; + + struct meson_serial_plat *const plat = dev_get_plat(dev); + struct meson_uart *const uart = plat->reg; + struct clk per_clk; + int ret = clk_get_by_name(dev, "baud", &per_clk); + + if (ret) + return ret; + ulong rate = clk_get_rate(&per_clk); + u32 divisor = meson_calc_baud_divisor(rate, baud); + u32 calc_baud = (rate / 3) / (divisor + 1); + u32 calc_err = baud > calc_baud ? baud - calc_baud : calc_baud - baud; + + if (((calc_err * 100) / baud) > 2) + return -EINVAL; + + meson_serial_set_baud(uart, rate, baud); + + return 0; +} + static int meson_serial_pending(struct udevice *dev, bool input) { struct meson_serial_plat *plat = dev_get_plat(dev); @@ -154,6 +223,7 @@ static const struct dm_serial_ops meson_serial_ops = { .putc = meson_serial_putc, .pending = meson_serial_pending, .getc = meson_serial_getc, + .setbrg = meson_serial_setbrg, }; static const struct udevice_id meson_serial_ids[] = { diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 196e58ed..01413a02 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -16,6 +16,13 @@ #define GICC_BASE 0xc4302000 #endif +/* Serial drivers */ +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, \ + 230400, 250000, 460800, 500000, 1000000, 2000000, 4000000, \ + 8000000 } + /* For splashscreen */ #ifdef CONFIG_DM_VIDEO #define STDOUT_CFG "vidconsole,serial" -- 2.37.3

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Re: [PATCH] arm: amlogic: add setbrg op to serial device
by Neil Armstrong 23 Sep '22

23 Sep '22

On 23/09/2022 10:23, Neil Armstrong via groups.io wrote: > Hi, > > On 22/09/2022 20:51, Edoardo Tomelleri wrote: >> Hello, >> Il giorno gio 22 set 2022 alle ore 18:51 Neil Armstrong >> <neil.armstrong(a)linaro.org> ha scritto: >>> >>> Hi, >>> >>> Sorry for the delay... >> No problem, don't worry >> >>> Looks good ! >>> >>> If someone can test it ? otherwise I'll take it for next release. >> ...does it count if I've tested it? I have a radxa zero board (S905Y2 >> chip), this started as an experimentation >> with editing register values in memory "for fun" and I decided to try >> to make a patch out of it. > > Yes it's perfect, thanks a lot for the test results ! > >> I do not have an oscilloscope so I can not accurately measure the baud >> rate, but the logic is the same as >> in linux and using an USB to UART (PL2303) adapter console input and >> loady command work fine. >> I've just repeated a small test: I'm using picocom and lrzsz in ymodem >> mode under WSL, the usb adapter >> is forwarded to WSL using usbip, but this should not change anything >> at this kind of speed (I hope). >> Here are some results sending a 1 MB test file (created once from /dev/urandom): >> picocom v3.1 >> >> port is : /dev/ttyUSB0 >> flowcontrol : none >> baudrate is : 115200 >> parity is : none >> databits are : 8 >> stopbits are : 1 >> [...] >> send_cmd is : sz --ymodem -vv >> receive_cmd is : rz -vv -E >> [...] >> @115200 >> Bytes Sent:1048576 BPS:7762 >> @230400 >> Bytes Sent:1048576 BPS:16372 >> @460800 >> Bytes Sent:1048576 BPS:26681 >> @500000 >> Bytes Sent:1048576 BPS:27689 >> @500000 (2nd run) >> Bytes Sent:1048576 BPS:27207 >> >> At this point I stopped testing, I think my adapter is not good enough >> and that the logic >> is correct (I've read amlogic's public datasheets [1], but I've not >> found a formula specified there), >> Reading address (for hardware device UARTAO1, that _of course_ is not >> listed there) >> md.l 0xff803014 1 >> ff803014: 0180000f >> This corresponds to REG5 of device UARTAO1, with bits 24 (USE_XTAL_CLK), 23 >> (use new baud rate) set, and bits 27 and 26 clear (so 24 MHz crystal >> clock is divided by 3), >> NEW_BAUD_RATE is f, so baud rate should be (8 MHz / (15 + 1)) = 500K. >> >> Other than that, I noticed that setting the env variable baudrate is >> restricted to values allowed >> in a compile time config, loady is not and loady ignores the return >> value of meson_serial_setbrg >> (it returns -EINVAL if for example a baudrate higher than 8'000'000 is >> requested), here's a test >> (with env variable baudrate=500000): >> => loady 0x01000000 8000001 >> ## Switch baudrate to 8000001 bps and press ENTER ... >> ## Ready for binary (ymodem) download to 0x01000000 at 8000001 bps... >> C >> *** file: ./dest >> $ sz --ymodem -vv ./dest >> Sending: dest >> Bytes Sent:1048576 BPS:27781 >> Sending: >> Ymodem sectors/kbytes sent: 0/ 0k >> Transfer complete >> >> *** exit status: 0 *** >> ## Total Size = 0x00100000 = 1048576 Bytes >> ## Start Addr = 0x01000000 >> ## Switch baudrate to 500000 bps and press ESC ... >> => >> >> setbrg fails, the baud rate register is left at the 500'000 setting >> and that's it. >> I think the "for fun" experiment has gone a bit too far. >> >> Edoardo >> [1] https://dl.radxa.com/zero/docs/hw/IO%20Interface%ef%bc%8dS905Y2%20Datasheet… > > I'll apply it then. > > Acked-by: Neil Armstrong <narmstrong(a)baylibre.com> Oops : Acked-by: Neil Armstrong <neil.armstrong(a)linaro.org> > > Please send more patches with such quality ! > > Thanks, > Neil > > > -=-=-=-=-=-=-=-=-=-=-=- > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#1349): https://groups.io/g/u-boot-amlogic/message/1349 > Mute This Topic: https://groups.io/mt/93775646/900740 > Group Owner: u-boot-amlogic+owner(a)groups.io > Unsubscribe: https://groups.io/g/u-boot-amlogic/unsub [neil.armstrong(a)linaro.org] > -=-=-=-=-=-=-=-=-=-=-=- > >

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ASIX AX88179A USB Ethernet dongle
by Boris Kolpackov 23 Sep '22

23 Sep '22

Hello, I am trying to figure out whether ASIX AX88179A-based Ethernet dongles are supported by U-Boot. There is a driver for AX88179 (note: without 'A') and it seems to recognize the dongle but that's as far as it gets. Specifically, when I boot, it is recognized as Ethernet controller and ethact is set to axg0: => print ethact ethact=axg0 But running bootp or dhcp results in the "unable to connect" error: => dhcp Waiting for Ethernet connection... unable to connect. Reset Ethernet Device Waiting for Ethernet connection... unable to connect. => I can also see there is no led activity of any kind on the dongle. Has anyone had any success with AX88179A? I am using U-Boot 2022.07. Thanks, Boris

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[PATCH v4 0/3] Add riscv semihosting support in u-boot
by Kautuk Consul 23 Sep '22

23 Sep '22

Semihosting is a mechanism that enables code running on a target to communicate and use the Input/Output facilities on a host computer that is running a debugger. This patchset adds support for semihosting in u-boot for RISCV64 targets. CHANGES since v2 and v3: - v2: Move the arch/arm/Kconfig common *SEMIHOSTING* config options from arch/arm/Kconfig to lib/Kconfig. - v2: Improve the *SEMIHOSTING_FALLBACK config options in lib/Kconfig to depend on RISCV or ARM64. - v2: Remove the arch/riscv/include/asm/semhosting.h file. - v2: Improve the arch/riscv/lib/semihosting.c by removing the jump statement and moving the .align 4 to before the 2 .option directives. - v3: Additionally check for the RISCV config option in the "depends" of the SPL_SEMIHOSTING_FALLBACK config option in lib/Kconfig. Compilation and test commands for SPL and S-mode configurations ================================================================= U-Boot S-mode on QEMU virt ---------------------------- // Compilation of S-mode u-boot ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_smode_defconfig make // Run riscv 64-bit u-boot with opensbi on qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\ u-boot/u-boot.bin U-Boot SPL on QEMU virt ------------------------ // Compilation of u-boot-spl ARCH=riscv CROSS_COMPILE=riscv64-unknown-linux-gnu- make qemu-riscv64_spl_defconfig make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin // Run 64-bit u-boot-spl in qemu qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ u-boot/spl/u-boot-spl.bin -device\ loader,file=u-boot/u-boot.itb,addr=0x80200000 Kautuk Consul (3): lib: Add common semihosting library arch/riscv: add semihosting support for RISC-V board: qemu-riscv: enable semihosting arch/arm/Kconfig | 46 ------- arch/arm/lib/semihosting.c | 181 +------------------------- arch/riscv/include/asm/spl.h | 1 + arch/riscv/lib/Makefile | 2 + arch/riscv/lib/interrupts.c | 11 ++ arch/riscv/lib/semihosting.c | 24 ++++ configs/qemu-riscv32_defconfig | 4 + configs/qemu-riscv32_smode_defconfig | 4 + configs/qemu-riscv32_spl_defconfig | 7 + configs/qemu-riscv64_defconfig | 4 + configs/qemu-riscv64_smode_defconfig | 4 + configs/qemu-riscv64_spl_defconfig | 7 + include/semihosting.h | 11 ++ lib/Kconfig | 46 +++++++ lib/Makefile | 2 + lib/semihosting.c | 186 +++++++++++++++++++++++++++ 16 files changed, 314 insertions(+), 226 deletions(-) create mode 100644 arch/riscv/lib/semihosting.c create mode 100644 lib/semihosting.c -- 2.34.1

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