August 2022 - U-Boot

[PATCH 1/2] doc: Drop a reference to travis
by Simon Glass 08 Aug '22

08 Aug '22

This was widely used by U-Boot for a long time, but is not used anymore, with Gitlab and Azure taking over. Drop the text. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- doc/develop/codingstyle.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst index a6bc37bbb44..3aa10dd99f0 100644 --- a/doc/develop/codingstyle.rst +++ b/doc/develop/codingstyle.rst @@ -248,5 +248,5 @@ will be much faster (10-100x or more) if they can directly call run_command() and ut_check_console_line() instead of using Python to send commands over a pipe to U-Boot. -Tests run all supported CI systems (gitlab, travis, azure) using scripts in the -root of the U-Boot tree. +Tests run all supported CI systems (gitlab, azure) using scripts in the root of +the U-Boot tree. -- 2.37.1.559.g78731f0fdb-goog

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[PATCH 1/2] net: dwc_eth_qos: Add eqos_get_enetaddr callback for tegra186
by Patrice Chotard 08 Aug '22

08 Aug '22

Add .eqos_get_enetaddr callback defined as eqos_null_ops() to avoid illegal access. Fixes: a624251461bf ("net: dwc_eth_qos: introduce eqos hook eqos_get_enetaddr") Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- drivers/net/dwc_eth_qos.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index c1f2391d63..09d95e4bc3 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1609,6 +1609,7 @@ static struct eqos_ops eqos_tegra186_ops = { .eqos_calibrate_pads = eqos_calibrate_pads_tegra186, .eqos_disable_calibration = eqos_disable_calibration_tegra186, .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186, + .eqos_get_enetaddr = eqos_null_ops, .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186 }; -- 2.25.1

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[PATCH 0/2] Add RGMII-ID phy-mode support for AVE ethernet controller
by Kunihiko Hayashi 08 Aug '22

08 Aug '22

This series adds support for RGMII-ID phy-mode for the SoCs that implement AVE ethernet controller. Some SoCs need to enable delay pins as default. Kunihiko Hayashi (2): net: ave: Add capability of rgmii-id mode ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins arch/arm/dts/uniphier-ld20.dtsi | 2 +- arch/arm/dts/uniphier-pxs2.dtsi | 2 +- arch/arm/dts/uniphier-pxs3.dtsi | 4 ++-- drivers/net/sni_ave.c | 14 +++++++++++++- 4 files changed, 17 insertions(+), 5 deletions(-) -- 2.7.4

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[PATCH 1/1] net: phy: possible NULL dereference in fixed_phy_create()
by Heinrich Schuchardt 08 Aug '22

08 Aug '22

We check if phydev is NULL. Only but if it is non-NULL we set one component of phydev. But even if it is NULL we set another. We should not dereference NULL in either case. Fixes: e24b58f5ed4f ("net: phy: don't require PHY interface mode during PHY creation") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- drivers/net/phy/phy.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 1121b99abf..945642ed93 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -984,10 +984,10 @@ struct phy_device *fixed_phy_create(ofnode node) } phydev = phy_device_create(NULL, 0, PHY_FIXED_ID, false); - if (phydev) + if (phydev) { phydev->node = subnode; - - phydev->interface = ofnode_read_phy_mode(node); + phydev->interface = ofnode_read_phy_mode(node); + } return phydev; } -- 2.36.1

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[PATCH 1/2] net: dwc_eth_qos: restore support of not cache-aligned descriptor
by Patrick Delaunay 08 Aug '22

08 Aug '22

Solve an issue with AXI_WIDTH_32 on a the 64 bytes cache line platform; in this case the requested descriptor padding length should be 12 but the associated parameter EQOS_DMA_CH0_CONTROL.DSL is limited to 3bits = 7. As the DMA descriptor can't be correctly aligned with the cache line, the maintenance of each descriptor can't be guaranteed by a simple cache line operation: flush or invalid. To avoid all the maintenance issues, these descriptors need to be allocated in a NOT CACHEABLE memory by noncached_alloc() when CONFIG_SYS_NONCACHED_MEMORY is enable. This patch doesn't change the current behavior when the descriptors can be cache-aligned with the field "Descriptor Skip Length" of the DMA channel control register, when eqos->desc_pad = true. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- This patch is required for ETH support on STM32MP13x family with AXI_WIDTH_32 value. This patch doesn't change the behavior for other parameters, tested on STM32MP15x boards. drivers/net/dwc_eth_qos.c | 79 ++++++++++++++++++++++++++++----------- 1 file changed, 57 insertions(+), 22 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 9d255cf95ff..0c2ba206056 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -51,6 +51,7 @@ #include <asm/arch/clock.h> #include <asm/mach-imx/sys_proto.h> #endif +#include <dm/device_compat.h> #include <linux/bitops.h> #include <linux/delay.h> @@ -210,6 +211,7 @@ struct eqos_dma_regs { #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1) #define EQOS_DMA_CH0_CONTROL_DSL_SHIFT 18 +#define EQOS_DMA_CH0_CONTROL_DSL_MAX 7 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16) #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 @@ -274,9 +276,11 @@ struct eqos_config { struct eqos_ops *ops; }; +struct eqos_priv; + struct eqos_ops { - void (*eqos_inval_desc)(void *desc); - void (*eqos_flush_desc)(void *desc); + void (*eqos_inval_desc)(struct eqos_priv *eqos, void *desc); + void (*eqos_flush_desc)(struct eqos_priv *eqos, void *desc); void (*eqos_inval_buffer)(void *buf, size_t size); void (*eqos_flush_buffer)(void *buf, size_t size); int (*eqos_probe_resources)(struct udevice *dev); @@ -319,6 +323,7 @@ struct eqos_priv { bool started; bool reg_access_ok; bool clk_ck_enabled; + bool use_cached_mem; }; /* @@ -341,15 +346,38 @@ struct eqos_priv { */ static void *eqos_alloc_descs(struct eqos_priv *eqos, unsigned int num) { + void *descs = NULL; + ulong desc_pad; + + /* + * if descriptors can to be cache-line aligned with the DSL = + * "Descriptor Skip Length" field of the DMA channel control register + */ eqos->desc_size = ALIGN(sizeof(struct eqos_desc), (unsigned int)ARCH_DMA_MINALIGN); + desc_pad = (eqos->desc_size - sizeof(struct eqos_desc)) / + eqos->config->axi_bus_width; + if (desc_pad <= EQOS_DMA_CH0_CONTROL_DSL_MAX) { + eqos->use_cached_mem = true; + descs = memalign(eqos->desc_size, num * eqos->desc_size); + } else { + eqos->use_cached_mem = false; + eqos->desc_size = sizeof(struct eqos_desc); +#ifdef CONFIG_SYS_NONCACHED_MEMORY + descs = (void *)noncached_alloc(num * eqos->desc_size, ARCH_DMA_MINALIGN); +#else + log_err("DMA descriptors with cached memory."); +#endif + } - return memalign(eqos->desc_size, num * eqos->desc_size); + return descs; } -static void eqos_free_descs(void *descs) +static void eqos_free_descs(struct eqos_priv *eqos) { - free(descs); + if (eqos->use_cached_mem) + free(eqos->descs); + /* memory allocated by noncached_alloc() can't be freed */ } static struct eqos_desc *eqos_get_desc(struct eqos_priv *eqos, @@ -359,22 +387,24 @@ static struct eqos_desc *eqos_get_desc(struct eqos_priv *eqos, ((rx ? EQOS_DESCRIPTORS_TX : 0) + num) * eqos->desc_size; } -static void eqos_inval_desc_generic(void *desc) +static void eqos_inval_desc_generic(struct eqos_priv *eqos, void *desc) { unsigned long start = (unsigned long)desc; unsigned long end = ALIGN(start + sizeof(struct eqos_desc), ARCH_DMA_MINALIGN); - invalidate_dcache_range(start, end); + if (eqos->use_cached_mem) + invalidate_dcache_range(start, end); } -static void eqos_flush_desc_generic(void *desc) +static void eqos_flush_desc_generic(struct eqos_priv *eqos, void *desc) { unsigned long start = (unsigned long)desc; unsigned long end = ALIGN(start + sizeof(struct eqos_desc), ARCH_DMA_MINALIGN); - flush_dcache_range(start, end); + if (eqos->use_cached_mem) + flush_dcache_range(start, end); } static void eqos_inval_buffer_tegra186(void *buf, size_t size) @@ -1262,12 +1292,17 @@ static int eqos_start(struct udevice *dev) EQOS_MAX_PACKET_SIZE << EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT); - desc_pad = (eqos->desc_size - sizeof(struct eqos_desc)) / - eqos->config->axi_bus_width; + setbits_le32(&eqos->dma_regs->ch0_control, EQOS_DMA_CH0_CONTROL_PBLX8); - setbits_le32(&eqos->dma_regs->ch0_control, - EQOS_DMA_CH0_CONTROL_PBLX8 | - (desc_pad << EQOS_DMA_CH0_CONTROL_DSL_SHIFT)); + /* "Descriptor Skip Length" field of the DMA channel control register */ + if (eqos->use_cached_mem) { + desc_pad = (eqos->desc_size - sizeof(struct eqos_desc)) / + eqos->config->axi_bus_width; + setbits_le32(&eqos->dma_regs->ch0_control, + desc_pad << EQOS_DMA_CH0_CONTROL_DSL_SHIFT); + if (desc_pad > EQOS_DMA_CH0_CONTROL_DSL_MAX) + dev_dbg(dev, "DMA_CH0_CONTROL.DSL overflow"); + } /* * Burst length must be < 1/2 FIFO size. @@ -1300,7 +1335,7 @@ static int eqos_start(struct udevice *dev) for (i = 0; i < EQOS_DESCRIPTORS_TX; i++) { struct eqos_desc *tx_desc = eqos_get_desc(eqos, i, false); - eqos->config->ops->eqos_flush_desc(tx_desc); + eqos->config->ops->eqos_flush_desc(eqos, tx_desc); } for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) { @@ -1309,7 +1344,7 @@ static int eqos_start(struct udevice *dev) (i * EQOS_MAX_PACKET_SIZE)); rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; mb(); - eqos->config->ops->eqos_flush_desc(rx_desc); + eqos->config->ops->eqos_flush_desc(eqos, rx_desc); eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE), EQOS_MAX_PACKET_SIZE); @@ -1437,13 +1472,13 @@ static int eqos_send(struct udevice *dev, void *packet, int length) */ mb(); tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length; - eqos->config->ops->eqos_flush_desc(tx_desc); + eqos->config->ops->eqos_flush_desc(eqos, tx_desc); writel((ulong)eqos_get_desc(eqos, eqos->tx_desc_idx, false), &eqos->dma_regs->ch0_txdesc_tail_pointer); for (i = 0; i < 1000000; i++) { - eqos->config->ops->eqos_inval_desc(tx_desc); + eqos->config->ops->eqos_inval_desc(eqos, tx_desc); if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN)) return 0; udelay(1); @@ -1463,7 +1498,7 @@ static int eqos_recv(struct udevice *dev, int flags, uchar **packetp) debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags); rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true); - eqos->config->ops->eqos_inval_desc(rx_desc); + eqos->config->ops->eqos_inval_desc(eqos, rx_desc); if (rx_desc->des3 & EQOS_DESC3_OWN) { debug("%s: RX packet not available\n", __func__); return -EAGAIN; @@ -1501,7 +1536,7 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) rx_desc->des0 = 0; mb(); - eqos->config->ops->eqos_flush_desc(rx_desc); + eqos->config->ops->eqos_flush_desc(eqos, rx_desc); eqos->config->ops->eqos_inval_buffer(packet, length); rx_desc->des0 = (u32)(ulong)packet; rx_desc->des1 = 0; @@ -1512,7 +1547,7 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) */ mb(); rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; - eqos->config->ops->eqos_flush_desc(rx_desc); + eqos->config->ops->eqos_flush_desc(eqos, rx_desc); writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); @@ -1587,7 +1622,7 @@ static int eqos_remove_resources_core(struct udevice *dev) free(eqos->rx_pkt); free(eqos->rx_dma_buf); free(eqos->tx_dma_buf); - eqos_free_descs(eqos->descs); + eqos_free_descs(eqos); debug("%s: OK\n", __func__); return 0; -- 2.25.1

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[PATCH] net: phy: Remove inline definitions from convinience functions
by Ramon Fried 08 Aug '22

08 Aug '22

The convinience functions are not that small and they caused bloated text segments because of their usage. There was no need to inline them in the first place, as they're not part of a fastpath. Signed-off-by: Ramon Fried <rfried.dev(a)gmail.com> --- drivers/net/phy/phy.c | 174 ++++++++++++++++++++++++++++++++++++++ include/phy.h | 189 ++---------------------------------------- 2 files changed, 183 insertions(+), 180 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 1121b99abf..e6e1755518 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -1101,3 +1101,177 @@ int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask, return phy_write(phydev, devad, regnum, (ret & ~mask) | set); } + +/** + * phy_read - Convenience function for reading a given PHY register + * @phydev: the phy_device struct + * @devad: The MMD to read from + * @regnum: register number to read + * @return: value for success or negative errno for failure + */ +int phy_read(struct phy_device *phydev, int devad, int regnum) +{ + struct mii_dev *bus = phydev->bus; + + if (!bus || !bus->read) { + debug("%s: No bus configured\n", __func__); + return -1; + } + + return bus->read(bus, phydev->addr, devad, regnum); +} + +/** + * phy_write - Convenience function for writing a given PHY register + * @phydev: the phy_device struct + * @devad: The MMD to read from + * @regnum: register number to write + * @val: value to write to @regnum + * @return: 0 for success or negative errno for failure + */ +int phy_write(struct phy_device *phydev, int devad, int regnum, u16 val) +{ + struct mii_dev *bus = phydev->bus; + + if (!bus || !bus->write) { + debug("%s: No bus configured\n", __func__); + return -1; + } + + return bus->write(bus, phydev->addr, devad, regnum, val); +} + +/** + * phy_mmd_start_indirect - Convenience function for writing MMD registers + * @phydev: the phy_device struct + * @devad: The MMD to read from + * @regnum: register number to write + * @return: None + */ +void phy_mmd_start_indirect(struct phy_device *phydev, int devad, int regnum) +{ + /* Write the desired MMD Devad */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, + (devad | MII_MMD_CTRL_NOINCR)); +} + +/** + * phy_read_mmd - Convenience function for reading a register + * from an MMD on a given PHY. + * @phydev: The phy_device struct + * @devad: The MMD to read from + * @regnum: The register on the MMD to read + * @return: Value for success or negative errno for failure + */ +int phy_read_mmd(struct phy_device *phydev, int devad, int regnum) +{ + struct phy_driver *drv = phydev->drv; + + if (regnum > (u16)~0 || devad > 32) + return -EINVAL; + + /* driver-specific access */ + if (drv->read_mmd) + return drv->read_mmd(phydev, devad, regnum); + + /* direct C45 / C22 access */ + if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES || + devad == MDIO_DEVAD_NONE || !devad) + return phy_read(phydev, devad, regnum); + + /* indirect C22 access */ + phy_mmd_start_indirect(phydev, devad, regnum); + + /* Read the content of the MMD's selected register */ + return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA); +} + +/** + * phy_write_mmd - Convenience function for writing a register + * on an MMD on a given PHY. + * @phydev: The phy_device struct + * @devad: The MMD to read from + * @regnum: The register on the MMD to read + * @val: value to write to @regnum + * @return: 0 for success or negative errno for failure + */ +int phy_write_mmd(struct phy_device *phydev, int devad, int regnum, u16 val) +{ + struct phy_driver *drv = phydev->drv; + + if (regnum > (u16)~0 || devad > 32) + return -EINVAL; + + /* driver-specific access */ + if (drv->write_mmd) + return drv->write_mmd(phydev, devad, regnum, val); + + /* direct C45 / C22 access */ + if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES || + devad == MDIO_DEVAD_NONE || !devad) + return phy_write(phydev, devad, regnum, val); + + /* indirect C22 access */ + phy_mmd_start_indirect(phydev, devad, regnum); + + /* Write the data into MMD's selected register */ + return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val); +} + +/** + * phy_set_bits_mmd - Convenience function for setting bits in a register + * on MMD + * @phydev: the phy_device struct + * @devad: the MMD containing register to modify + * @regnum: register number to modify + * @val: bits to set + * @return: 0 for success or negative errno for failure + */ +int phy_set_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) +{ + int value, ret; + + value = phy_read_mmd(phydev, devad, regnum); + if (value < 0) + return value; + + value |= val; + + ret = phy_write_mmd(phydev, devad, regnum, value); + if (ret < 0) + return ret; + + return 0; +} + +/** + * phy_clear_bits_mmd - Convenience function for clearing bits in a register + * on MMD + * @phydev: the phy_device struct + * @devad: the MMD containing register to modify + * @regnum: register number to modify + * @val: bits to clear + * @return: 0 for success or negative errno for failure + */ +int phy_clear_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val) +{ + int value, ret; + + value = phy_read_mmd(phydev, devad, regnum); + if (value < 0) + return value; + + value &= ~val; + + ret = phy_write_mmd(phydev, devad, regnum, value); + if (ret < 0) + return ret; + + return 0; +} diff --git a/include/phy.h b/include/phy.h index b329595710..ad2096ca84 100644 --- a/include/phy.h +++ b/include/phy.h @@ -177,186 +177,6 @@ struct fixed_link { int asym_pause; }; -/** - * phy_read - Convenience function for reading a given PHY register - * @phydev: the phy_device struct - * @devad: The MMD to read from - * @regnum: register number to read - * @return: value for success or negative errno for failure - */ -static inline int phy_read(struct phy_device *phydev, int devad, int regnum) -{ - struct mii_dev *bus = phydev->bus; - - if (!bus || !bus->read) { - debug("%s: No bus configured\n", __func__); - return -1; - } - - return bus->read(bus, phydev->addr, devad, regnum); -} - -/** - * phy_write - Convenience function for writing a given PHY register - * @phydev: the phy_device struct - * @devad: The MMD to read from - * @regnum: register number to write - * @val: value to write to @regnum - * @return: 0 for success or negative errno for failure - */ -static inline int phy_write(struct phy_device *phydev, int devad, int regnum, - u16 val) -{ - struct mii_dev *bus = phydev->bus; - - if (!bus || !bus->write) { - debug("%s: No bus configured\n", __func__); - return -1; - } - - return bus->write(bus, phydev->addr, devad, regnum, val); -} - -/** - * phy_mmd_start_indirect - Convenience function for writing MMD registers - * @phydev: the phy_device struct - * @devad: The MMD to read from - * @regnum: register number to write - * @return: None - */ -static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad, - int regnum) -{ - /* Write the desired MMD Devad */ - phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad); - - /* Write the desired MMD register address */ - phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum); - - /* Select the Function : DATA with no post increment */ - phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, - (devad | MII_MMD_CTRL_NOINCR)); -} - -/** - * phy_read_mmd - Convenience function for reading a register - * from an MMD on a given PHY. - * @phydev: The phy_device struct - * @devad: The MMD to read from - * @regnum: The register on the MMD to read - * @return: Value for success or negative errno for failure - */ -static inline int phy_read_mmd(struct phy_device *phydev, int devad, - int regnum) -{ - struct phy_driver *drv = phydev->drv; - - if (regnum > (u16)~0 || devad > 32) - return -EINVAL; - - /* driver-specific access */ - if (drv->read_mmd) - return drv->read_mmd(phydev, devad, regnum); - - /* direct C45 / C22 access */ - if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES || - devad == MDIO_DEVAD_NONE || !devad) - return phy_read(phydev, devad, regnum); - - /* indirect C22 access */ - phy_mmd_start_indirect(phydev, devad, regnum); - - /* Read the content of the MMD's selected register */ - return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA); -} - -/** - * phy_write_mmd - Convenience function for writing a register - * on an MMD on a given PHY. - * @phydev: The phy_device struct - * @devad: The MMD to read from - * @regnum: The register on the MMD to read - * @val: value to write to @regnum - * @return: 0 for success or negative errno for failure - */ -static inline int phy_write_mmd(struct phy_device *phydev, int devad, - int regnum, u16 val) -{ - struct phy_driver *drv = phydev->drv; - - if (regnum > (u16)~0 || devad > 32) - return -EINVAL; - - /* driver-specific access */ - if (drv->write_mmd) - return drv->write_mmd(phydev, devad, regnum, val); - - /* direct C45 / C22 access */ - if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES || - devad == MDIO_DEVAD_NONE || !devad) - return phy_write(phydev, devad, regnum, val); - - /* indirect C22 access */ - phy_mmd_start_indirect(phydev, devad, regnum); - - /* Write the data into MMD's selected register */ - return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val); -} - -/** - * phy_set_bits_mmd - Convenience function for setting bits in a register - * on MMD - * @phydev: the phy_device struct - * @devad: the MMD containing register to modify - * @regnum: register number to modify - * @val: bits to set - * @return: 0 for success or negative errno for failure - */ -static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad, - u32 regnum, u16 val) -{ - int value, ret; - - value = phy_read_mmd(phydev, devad, regnum); - if (value < 0) - return value; - - value |= val; - - ret = phy_write_mmd(phydev, devad, regnum, value); - if (ret < 0) - return ret; - - return 0; -} - -/** - * phy_clear_bits_mmd - Convenience function for clearing bits in a register - * on MMD - * @phydev: the phy_device struct - * @devad: the MMD containing register to modify - * @regnum: register number to modify - * @val: bits to clear - * @return: 0 for success or negative errno for failure - */ -static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad, - u32 regnum, u16 val) -{ - int value, ret; - - value = phy_read_mmd(phydev, devad, regnum); - if (value < 0) - return value; - - value &= ~val; - - ret = phy_write_mmd(phydev, devad, regnum, value); - if (ret < 0) - return ret; - - return 0; -} - #ifdef CONFIG_PHYLIB_10G extern struct phy_driver gen10g_driver; #endif @@ -508,6 +328,15 @@ static inline ofnode phy_get_ofnode(struct phy_device *phydev) return ofnode_null(); } #endif + +int phy_read(struct phy_device *phydev, int devad, int regnum); +int phy_write(struct phy_device *phydev, int devad, int regnum, u16 val); +void phy_mmd_start_indirect(struct phy_device *phydev, int devad, int regnum); +int phy_read_mmd(struct phy_device *phydev, int devad, int regnum); +int phy_write_mmd(struct phy_device *phydev, int devad, int regnum, u16 val); +int phy_set_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); +int phy_clear_bits_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val); + int phy_startup(struct phy_device *phydev); int phy_config(struct phy_device *phydev); int phy_shutdown(struct phy_device *phydev); -- 2.30.2

5 5

[PATCH] net: ftgmac100: use bus name in mdio error messages
by Zev Weiss 08 Aug '22

08 Aug '22

Previously we'd been using a device name retrieved via ftgmac100_data->phydev, but the mdio read/write functions may be called before that member is initialized in ftgmac100_phy_init(), leading to a NULL pointer dereference while printing the error message issued if the mdio access fails. We can instead use bus->name, which is already available at that point. Signed-off-by: Zev Weiss <zev(a)bewilderbeest.net> Fixes: 538e75d3fc54 ("net: ftgmac100: add MDIO bus and phylib support") --- drivers/net/ftgmac100.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c index 78779d7d60b9..74261d14e548 100644 --- a/drivers/net/ftgmac100.c +++ b/drivers/net/ftgmac100.c @@ -119,7 +119,7 @@ static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr, FTGMAC100_MDIO_TIMEOUT_USEC); if (ret) { pr_err("%s: mdio read failed (phy:%d reg:%x)\n", - priv->phydev->dev->name, phy_addr, reg_addr); + bus->name, phy_addr, reg_addr); return ret; } @@ -151,7 +151,7 @@ static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr, FTGMAC100_MDIO_TIMEOUT_USEC); if (ret) { pr_err("%s: mdio write failed (phy:%d reg:%x)\n", - priv->phydev->dev->name, phy_addr, reg_addr); + bus->name, phy_addr, reg_addr); } return ret; -- 2.36.1

3 2

[PATCH v1] net: nuvoton : Add NPCM7xx EMAC driver
by Jim Liu 08 Aug '22

08 Aug '22

NPCM750 provides identical ethernet MAC controllers for WAN/LAN applications. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/net/Kconfig | 5 + drivers/net/Makefile | 1 + drivers/net/npcm750_eth.c | 745 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 751 insertions(+) create mode 100644 drivers/net/npcm750_eth.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7fe0e00649..34cd48648a 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -496,6 +496,11 @@ config MT7628_ETH The MediaTek MT7628 ethernet interface is used on MT7628 and MT7688 based boards. +config NET_NPCM750 + bool "Nuvoton NPCM750 Ethernet MAC" + help + support NPCM750 EMAC + config NET_OCTEON bool "MIPS Octeon ethernet support" depends on ARCH_OCTEON diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 69fb3bbbf7..345d0904ea 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_MVMDIO) += mvmdio.o obj-$(CONFIG_MVNETA) += mvneta.o obj-$(CONFIG_MVPP2) += mvpp2.o obj-$(CONFIG_NETCONSOLE) += netconsole.o +obj-$(CONFIG_NET_NPCM750) += npcm750_eth.o obj-$(CONFIG_NET_OCTEON) += octeon/ obj-$(CONFIG_NET_OCTEONTX) += octeontx/ obj-$(CONFIG_NET_OCTEONTX2) += octeontx2/ diff --git a/drivers/net/npcm750_eth.c b/drivers/net/npcm750_eth.c new file mode 100644 index 0000000000..409d5cce4a --- /dev/null +++ b/drivers/net/npcm750_eth.c @@ -0,0 +1,745 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology Corp. + */ + +#include <common.h> +#include <cpu_func.h> +#include <dm.h> +#include <errno.h> +#include <miiphy.h> +#include <malloc.h> +#include <net.h> +#include <regmap.h> +#include <serial.h> +#include <syscon.h> +#include <asm/io.h> +#include <linux/err.h> +#include <linux/iopoll.h> + +#define MAC_ADDR_SIZE 6 +#define CONFIG_TX_DESCR_NUM 32 +#define CONFIG_RX_DESCR_NUM 32 + +#define TX_TOTAL_BUFSIZE \ + ((CONFIG_TX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN) +#define RX_TOTAL_BUFSIZE \ + ((CONFIG_RX_DESCR_NUM + 1) * PKTSIZE_ALIGN + PKTALIGN) + +#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) + +struct npcm750_rxbd { + unsigned int sl; + unsigned int buffer; + unsigned int reserved; + unsigned int next; +} __aligned(ARCH_DMA_MINALIGN); + +struct npcm750_txbd { + unsigned int mode; + unsigned int buffer; + unsigned int sl; + unsigned int next; +} __aligned(ARCH_DMA_MINALIGN); + +struct emc_regs { + u32 camcmr; /* 0x00 */ + u32 camen; /* 0x04 */ + u32 cam0m; /* 0x08 */ + u32 cam0l; /* 0x0c */ + u32 cam1m; /* 0x10 */ + u32 cam1l; /* 0x14 */ + u32 cam2m; /* 0x18 */ + u32 cam2l; /* 0x1c */ + u32 cam3m; /* 0x20 */ + u32 cam3l; /* 0x24 */ + u32 cam4m; /* 0x28 */ + u32 cam4l; /* 0x2c */ + u32 cam5m; /* 0x30 */ + u32 cam5l; /* 0x34 */ + u32 cam6m; /* 0x38 */ + u32 cam6l; /* 0x3c */ + u32 cam7m; /* 0x40 */ + u32 cam7l; /* 0x44 */ + u32 cam8m; /* 0x48 */ + u32 cam8l; /* 0x4c */ + u32 cam9m; /* 0x50 */ + u32 cam9l; /* 0x54 */ + u32 cam10m; /* 0x58 */ + u32 cam10l; /* 0x5c */ + u32 cam11m; /* 0x60 */ + u32 cam11l; /* 0x64 */ + u32 cam12m; /* 0x68 */ + u32 cam12l; /* 0x6c */ + u32 cam13m; /* 0x70 */ + u32 cam13l; /* 0x74 */ + u32 cam14m; /* 0x78 */ + u32 cam14l; /* 0x7c */ + u32 cam15m; /* 0x80 */ + u32 cam15l; /* 0x84 */ + u32 txdlsa; /* 0x88 */ + u32 rxdlsa; /* 0x8c */ + u32 mcmdr; /* 0x90 */ + u32 miid; /* 0x94 */ + u32 miida; /* 0x98 */ + u32 fftcr; /* 0x9c */ + u32 tsdr; /* 0xa0 */ + u32 rsdr; /* 0xa4 */ + u32 dmarfc; /* 0xa8 */ + u32 mien; /* 0xac */ + u32 mista; /* 0xb0 */ + u32 mgsta; /* 0xb4 */ + u32 mpcnt; /* 0xb8 */ + u32 mrpc; /* 0xbc */ + u32 mrpcc; /* 0xc0 */ + u32 mrepc; /* 0xc4 */ + u32 dmarfs; /* 0xc8 */ + u32 ctxdsa; /* 0xcc */ + u32 ctxbsa; /* 0xd0 */ + u32 crxdsa; /* 0xd4 */ + u32 crxbsa; /* 0xd8 */ +}; + +struct npcm750_eth_dev { + struct npcm750_txbd tdesc[CONFIG_TX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN); + struct npcm750_rxbd rdesc[CONFIG_RX_DESCR_NUM] __aligned(ARCH_DMA_MINALIGN); + u8 txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + u8 rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + struct emc_regs *emc_regs_p; + struct phy_device *phydev; + struct mii_dev *bus; + struct npcm750_txbd *curr_txd; + struct npcm750_rxbd *curr_rxd; + u32 interface; + u32 max_speed; + u32 idx; + struct regmap *gcr_regmap; +}; + +struct npcm750_eth_pdata { + struct eth_pdata eth_pdata; +}; + +/* mac controller bit */ +#define MCMDR_RXON BIT(0) +#define MCMDR_ACP BIT(3) +#define MCMDR_SPCRC BIT(5) +#define MCMDR_TXON BIT(8) +#define MCMDR_NDEF BIT(9) +#define MCMDR_FDUP BIT(18) +#define MCMDR_ENMDC BIT(19) +#define MCMDR_OPMOD BIT(20) +#define MCMDR_SWR BIT(24) + +/* cam command regiser */ +#define CAMCMR_AUP 0x01 +#define CAMCMR_AMP BIT(1) +#define CAMCMR_ABP BIT(2) +#define CAMCMR_CCAM BIT(3) +#define CAMCMR_ECMP BIT(4) +#define CAM0EN 0x01 + +/* mac mii controller bit */ +#define MDCON BIT(19) +#define PHYAD BIT(8) +#define PHYWR BIT(16) +#define PHYBUSY BIT(17) +#define PHYPRESP BIT(18) +#define CAM_ENTRY_SIZE 0x08 + +/* rx and tx status */ +#define TXDS_TXCP BIT(19) +#define RXDS_CRCE BIT(17) +#define RXDS_PTLE BIT(19) +#define RXDS_RXGD BIT(20) +#define RXDS_ALIE BIT(21) +#define RXDS_RP BIT(22) + +/* mac interrupt status*/ +#define MISTA_RXINTR BIT(0) +#define MISTA_CRCE BIT(1) +#define MISTA_RXOV BIT(2) +#define MISTA_PTLE BIT(3) +#define MISTA_RXGD BIT(4) +#define MISTA_ALIE BIT(5) +#define MISTA_RP BIT(6) +#define MISTA_MMP BIT(7) +#define MISTA_DFOI BIT(8) +#define MISTA_DENI BIT(9) +#define MISTA_RDU BIT(10) +#define MISTA_RXBERR BIT(11) +#define MISTA_CFR BIT(14) +#define MISTA_TXINTR BIT(16) +#define MISTA_TXEMP BIT(17) +#define MISTA_TXCP BIT(18) +#define MISTA_EXDEF BIT(19) +#define MISTA_NCS BIT(20) +#define MISTA_TXABT BIT(21) +#define MISTA_LC BIT(22) +#define MISTA_TDU BIT(23) +#define MISTA_TXBERR BIT(24) + +#define ENSTART 0x01 +#define ENRXINTR BIT(0) +#define ENCRCE BIT(1) +#define EMRXOV BIT(2) +#define ENPTLE BIT(3) +#define ENRXGD BIT(4) +#define ENALIE BIT(5) +#define ENRP BIT(6) +#define ENMMP BIT(7) +#define ENDFO BIT(8) +#define ENDENI BIT(9) +#define ENRDU BIT(10) +#define ENRXBERR BIT(11) +#define ENCFR BIT(14) +#define ENTXINTR BIT(16) +#define ENTXEMP BIT(17) +#define ENTXCP BIT(18) +#define ENTXDEF BIT(19) +#define ENNCS BIT(20) +#define ENTXABT BIT(21) +#define ENLC BIT(22) +#define ENTDU BIT(23) +#define ENTXBERR BIT(24) + +#define RX_STAT_RBC 0xffff +#define RX_STAT_RXINTR BIT(16) +#define RX_STAT_CRCE BIT(17) +#define RX_STAT_PTLE BIT(19) +#define RX_STAT_RXGD BIT(20) +#define RX_STAT_ALIE BIT(21) +#define RX_STAT_RP BIT(22) +#define RX_STAT_OWNER (BIT(30) | BIT(31)) + +#define TX_STAT_TBC 0xffff +#define TX_STAT_TXINTR BIT(16) +#define TX_STAT_DEF BIT(17) +#define TX_STAT_TXCP BIT(19) +#define TX_STAT_EXDEF BIT(20) +#define TX_STAT_NCS BIT(21) +#define TX_STAT_TXBT BIT(22) +#define TX_STAT_LC BIT(23) +#define TX_STAT_TXHA BIT(24) +#define TX_STAT_PAU BIT(25) +#define TX_STAT_SQE BIT(26) + +/* rx and tx owner bit */ +#define RX_OWEN_DMA BIT(31) +#define RX_OWEN_CPU 0x00 //bit 30 & bit 31 +#define TX_OWEN_DMA BIT(31) +#define TX_OWEN_CPU (~(BIT(31))) + +/* tx frame desc controller bit */ +#define MACTXINTEN 0x04 +#define CRCMODE 0x02 +#define PADDINGMODE 0x01 + +/* fftcr controller bit */ +#define RXTHD 0x03 +#define TXTHD (BIT(8) | BIT(9)) +#define BLENGTH BIT(21) + +/* global setting for driver */ +#define RX_DESC_SIZE 128 +#define TX_DESC_SIZE 64 +#define MAX_RBUFF_SZ 0x600 +#define MAX_TBUFF_SZ 0x600 +#define TX_TIMEOUT 50 +#define DELAY 1000 +#define CAM0 0x0 +#define RX_POLL_SIZE (RX_DESC_SIZE / 2) +#define MII_TIMEOUT 100 +#define GCR_INTCR 0x3c +#define INTCR_R1EN BIT(5) + +enum MIIDA_MDCCR_T { + MIIDA_MDCCR_4 = 0x00, + MIIDA_MDCCR_6 = 0x01, + MIIDA_MDCCR_8 = 0x02, + MIIDA_MDCCR_12 = 0x03, + MIIDA_MDCCR_16 = 0x04, + MIIDA_MDCCR_20 = 0x05, + MIIDA_MDCCR_24 = 0x06, + MIIDA_MDCCR_28 = 0x07, + MIIDA_MDCCR_30 = 0x08, + MIIDA_MDCCR_32 = 0x09, + MIIDA_MDCCR_36 = 0x0A, + MIIDA_MDCCR_40 = 0x0B, + MIIDA_MDCCR_44 = 0x0C, + MIIDA_MDCCR_48 = 0x0D, + MIIDA_MDCCR_54 = 0x0E, + MIIDA_MDCCR_60 = 0x0F, +}; + +DECLARE_GLOBAL_DATA_PTR; + +static int npcm750_mdio_read(struct mii_dev *bus, int addr, int devad, int regs) +{ + struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv; + struct emc_regs *reg = priv->emc_regs_p; + u32 start, val; + int timeout = CONFIG_MDIO_TIMEOUT; + + val = (addr << 0x08) | regs | PHYBUSY | (MIIDA_MDCCR_60 << 20); + writel(val, &reg->miida); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&reg->miida) & PHYBUSY)) { + val = readl(&reg->miid); + return val; + } + udelay(10); + }; + return -ETIMEDOUT; +} + +static int npcm750_mdio_write(struct mii_dev *bus, int addr, int devad, int regs, + u16 val) +{ + struct npcm750_eth_dev *priv = (struct npcm750_eth_dev *)bus->priv; + struct emc_regs *reg = priv->emc_regs_p; + ulong start; + int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; + + writel(val, &reg->miid); + writel((addr << 0x08) | regs | PHYBUSY | PHYWR | (MIIDA_MDCCR_60 << 20), &reg->miida); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&reg->miida) & PHYBUSY)) { + ret = 0; + break; + } + udelay(10); + }; + return ret; +} + +static int npcm750_mdio_reset(struct mii_dev *bus) +{ + return 0; +} + +static int npcm750_mdio_init(const char *name, struct npcm750_eth_dev *priv) +{ + struct emc_regs *reg = priv->emc_regs_p; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = npcm750_mdio_read; + bus->write = npcm750_mdio_write; + snprintf(bus->name, sizeof(bus->name), "%s", name); + bus->reset = npcm750_mdio_reset; + + bus->priv = (void *)priv; + + writel(readl(&reg->mcmdr) | MCMDR_ENMDC, &reg->mcmdr); + return mdio_register(bus); +} + +static void npcm750_tx_descs_init(struct npcm750_eth_dev *priv) +{ + struct emc_regs *reg = priv->emc_regs_p; + struct npcm750_txbd *desc_table_p = &priv->tdesc[0]; + struct npcm750_txbd *desc_p; + u8 *txbuffs = &priv->txbuffs[0]; + u32 idx; + + writel((u32)desc_table_p, &reg->txdlsa); + priv->curr_txd = desc_table_p; + + for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->buffer = (u32)&txbuffs[idx * PKTSIZE_ALIGN]; + desc_p->sl = 0; + desc_p->mode = 0; + desc_p->mode = TX_OWEN_CPU | PADDINGMODE | CRCMODE | MACTXINTEN; + if (idx < (CONFIG_TX_DESCR_NUM - 1)) + desc_p->next = (u32)&desc_table_p[idx + 1]; + else + desc_p->next = (u32)&priv->tdesc[0]; + } + flush_dcache_range((ulong)&desc_table_p[0], + (ulong)&desc_table_p[CONFIG_TX_DESCR_NUM]); +} + +static void npcm750_rx_descs_init(struct npcm750_eth_dev *priv) +{ + struct emc_regs *reg = priv->emc_regs_p; + struct npcm750_rxbd *desc_table_p = &priv->rdesc[0]; + struct npcm750_rxbd *desc_p; + u8 *rxbuffs = &priv->rxbuffs[0]; + u32 idx; + + flush_dcache_range((ulong)priv->rxbuffs[0], + (ulong)priv->rxbuffs[CONFIG_RX_DESCR_NUM]); + + writel((u32)desc_table_p, &reg->rxdlsa); + priv->curr_rxd = desc_table_p; + + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->sl = RX_OWEN_DMA; + desc_p->buffer = (u32)&rxbuffs[idx * PKTSIZE_ALIGN]; + if (idx < (CONFIG_RX_DESCR_NUM - 1)) + desc_p->next = (u32)&desc_table_p[idx + 1]; + else + desc_p->next = (u32)&priv->rdesc[0]; + } + flush_dcache_range((ulong)&desc_table_p[0], + (ulong)&desc_table_p[CONFIG_RX_DESCR_NUM]); +} + +static void npcm750_set_fifo_threshold(struct npcm750_eth_dev *priv) +{ + struct emc_regs *reg = priv->emc_regs_p; + unsigned int val; + + val = RXTHD | TXTHD | BLENGTH; + writel(val, &reg->fftcr); +} + +static void npcm750_set_global_maccmd(struct npcm750_eth_dev *priv) +{ + struct emc_regs *reg = priv->emc_regs_p; + unsigned int val; + + val = readl(&reg->mcmdr); + val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | MCMDR_NDEF; + writel(val, &reg->mcmdr); +} + +static void npcm750_set_cam(struct npcm750_eth_dev *priv, + unsigned int x, unsigned char *pval) +{ + struct emc_regs *reg = priv->emc_regs_p; + unsigned int msw, lsw; + + msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3]; + lsw = (pval[4] << 24) | (pval[5] << 16); + + writel(lsw, &reg->cam0l + x * CAM_ENTRY_SIZE); + writel(msw, &reg->cam0m + x * CAM_ENTRY_SIZE); + writel(readl(&reg->camen) | CAM0EN, &reg->camen); + writel(CAMCMR_ECMP | CAMCMR_ABP | CAMCMR_AUP, &reg->camcmr); +} + +static void npcm750_adjust_link(struct emc_regs *reg, + struct phy_device *phydev) +{ + u32 val = readl(&reg->mcmdr); + + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } + + if (phydev->speed == 100) + val |= MCMDR_OPMOD; + else + val &= ~MCMDR_OPMOD; + + if (phydev->duplex) + val |= MCMDR_FDUP; + else + val &= ~MCMDR_FDUP; + + writel(val, &reg->mcmdr); + + debug("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", + (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); +} + +static int npcm750_phy_init(struct npcm750_eth_dev *priv, void *dev) +{ + struct phy_device *phydev; + int ret; + u32 address = 0x0; + + phydev = phy_connect(priv->bus, address, dev, priv->interface); + if (!phydev) + return -ENODEV; + + if (priv->max_speed) { + ret = phy_set_supported(phydev, priv->max_speed); + if (ret) + return ret; + } + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + return 0; +} + +static int npcm750_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct npcm750_eth_dev *priv = dev_get_priv(dev); + struct emc_regs *reg = priv->emc_regs_p; + u8 *enetaddr = pdata->enetaddr; + int ret; + + writel(readl(&reg->mcmdr) & ~MCMDR_TXON & ~MCMDR_RXON, &reg->mcmdr); + + writel(readl(&reg->mcmdr) | MCMDR_SWR, &reg->mcmdr); + do { + ret = readl(&reg->mcmdr); + } while (ret & MCMDR_SWR); + + npcm750_rx_descs_init(priv); + npcm750_tx_descs_init(priv); + + npcm750_set_cam(priv, priv->idx, enetaddr); + npcm750_set_global_maccmd(priv); + npcm750_set_fifo_threshold(priv); + + /* Start up the PHY */ + ret = phy_startup(priv->phydev); + if (ret) { + printf("Could not initialize PHY\n"); + return ret; + } + + npcm750_adjust_link(reg, priv->phydev); + writel(readl(&reg->mcmdr) | MCMDR_TXON | MCMDR_RXON, &reg->mcmdr); + + return 0; +} + +static int npcm750_eth_send(struct udevice *dev, void *packet, int length) +{ + struct npcm750_eth_dev *priv = dev_get_priv(dev); + struct emc_regs *reg = priv->emc_regs_p; + struct npcm750_txbd *desc_p; + struct npcm750_txbd *next_desc_p; + + desc_p = priv->curr_txd; + + invalidate_dcache_range((ulong)desc_p, (ulong)(desc_p + 1)); + /* Check if the descriptor is owned by CPU */ + if (desc_p->mode & TX_OWEN_DMA) { + next_desc_p = (struct npcm750_txbd *)desc_p->next; + + while ((next_desc_p != desc_p) && (next_desc_p->mode & TX_OWEN_DMA)) + next_desc_p = (struct npcm750_txbd *)next_desc_p->next; + + if (next_desc_p == desc_p) { + struct emc_regs *reg = priv->emc_regs_p; + + writel(0, &reg->tsdr); + serial_printf("TX: overflow and exit\n"); + return -EPERM; + } + + desc_p = next_desc_p; + } + + memcpy((void *)desc_p->buffer, packet, length); + flush_dcache_range((ulong)desc_p->buffer, + (ulong)desc_p->buffer + roundup(length, ARCH_DMA_MINALIGN)); + desc_p->sl = 0; + desc_p->sl = length & TX_STAT_TBC; + desc_p->mode = TX_OWEN_DMA | PADDINGMODE | CRCMODE; + flush_dcache_range((ulong)desc_p, (ulong)(desc_p + 1)); + + if (!(readl(&reg->mcmdr) & MCMDR_TXON)) + writel(readl(&reg->mcmdr) | MCMDR_TXON, &reg->mcmdr); + priv->curr_txd = (struct npcm750_txbd *)priv->curr_txd->next; + + writel(0, &reg->tsdr); + return 0; +} + +static int npcm750_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct npcm750_eth_dev *priv = dev_get_priv(dev); + struct npcm750_rxbd *desc_p; + struct npcm750_rxbd *next_desc_p; + int length = -1; + + desc_p = priv->curr_rxd; + invalidate_dcache_range((ulong)desc_p, (ulong)(desc_p + 1)); + + if ((desc_p->sl & RX_STAT_OWNER) == RX_OWEN_DMA) { + next_desc_p = (struct npcm750_rxbd *)desc_p->next; + while ((next_desc_p != desc_p) && + ((next_desc_p->sl & RX_STAT_OWNER) == RX_OWEN_CPU)) { + next_desc_p = (struct npcm750_rxbd *)next_desc_p->next; + } + + if (next_desc_p == desc_p) { + struct emc_regs *reg = priv->emc_regs_p; + + writel(0, &reg->rsdr); + serial_printf("RX: overflow and exit\n"); + return -EPERM; + } + desc_p = next_desc_p; + } + + /* Check if the descriptor is owned by CPU */ + if ((desc_p->sl & RX_STAT_OWNER) == RX_OWEN_CPU) { + if (desc_p->sl & RX_STAT_RXGD) { + length = desc_p->sl & RX_STAT_RBC; + invalidate_dcache_range((ulong)desc_p->buffer, + (ulong)(desc_p->buffer + roundup(length, + ARCH_DMA_MINALIGN))); + *packetp = (u8 *)(u32)desc_p->buffer; + priv->curr_rxd = desc_p; + } + } + return length; +} + +static int npcm750_eth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct npcm750_eth_dev *priv = dev_get_priv(dev); + struct emc_regs *reg = priv->emc_regs_p; + struct npcm750_rxbd *desc_p = priv->curr_rxd; + + /* + * Make the current descriptor valid again and go to + * the next one + */ + desc_p->sl |= RX_OWEN_DMA; + flush_dcache_range((ulong)desc_p, (ulong)(desc_p + 1)); + priv->curr_rxd = (struct npcm750_rxbd *)priv->curr_rxd->next; + writel(0, &reg->rsdr); + + return 0; +} + +static void npcm750_eth_stop(struct udevice *dev) +{ + struct npcm750_eth_dev *priv = dev_get_priv(dev); + struct emc_regs *reg = priv->emc_regs_p; + + writel(readl(&reg->mcmdr) & ~MCMDR_TXON, &reg->mcmdr); + writel(readl(&reg->mcmdr) & ~MCMDR_RXON, &reg->mcmdr); + priv->curr_txd = (struct npcm750_txbd *)readl(&reg->txdlsa); + priv->curr_rxd = (struct npcm750_rxbd *)readl(&reg->rxdlsa); + phy_shutdown(priv->phydev); +} + +static int npcm750_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct npcm750_eth_dev *priv = dev_get_priv(dev); + + npcm750_set_cam(priv, CAM0, pdata->enetaddr); + return 0; +} + +static int npcm750_eth_bind(struct udevice *dev) +{ + return 0; +} + +static int npcm750_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct npcm750_eth_dev *priv = dev_get_priv(dev); + u32 iobase = pdata->iobase; + int ret; + + memset(priv, 0, sizeof(struct npcm750_eth_dev)); + ret = dev_read_u32(dev, "id", &priv->idx); + if (ret) { + printf("failed to get id\n"); + return -EINVAL; + } + + priv->gcr_regmap = syscon_regmap_lookup_by_phandle(dev, "syscon-gcr"); + if (IS_ERR(priv->gcr_regmap)) + return -EINVAL; + + priv->emc_regs_p = (struct emc_regs *)iobase; + priv->interface = pdata->phy_interface; + priv->max_speed = pdata->max_speed; + + if (priv->idx == 0) { + /* Enable RMII for EMC1 module */ + regmap_update_bits(priv->gcr_regmap, GCR_INTCR, INTCR_R1EN, INTCR_R1EN); + } + + npcm750_mdio_init(dev->name, priv); + priv->bus = miiphy_get_dev_by_name(dev->name); + + ret = npcm750_phy_init(priv, dev); + + return ret; +} + +static int npcm750_eth_remove(struct udevice *dev) +{ + struct npcm750_eth_dev *priv = dev_get_priv(dev); + + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + + return 0; +} + +static const struct eth_ops npcm750_eth_ops = { + .start = npcm750_eth_start, + .send = npcm750_eth_send, + .recv = npcm750_eth_recv, + .free_pkt = npcm750_eth_free_pkt, + .stop = npcm750_eth_stop, + .write_hwaddr = npcm750_eth_write_hwaddr, +}; + +static int npcm750_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct npcm750_eth_pdata *npcm750_pdata = dev_get_plat(dev); + struct eth_pdata *pdata = &npcm750_pdata->eth_pdata; + const char *phy_mode; + const fdt32_t *cell; + int ret = 0; + + pdata->iobase = (phys_addr_t)dev_read_addr_ptr(dev); + + pdata->phy_interface = -1; + phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + pdata->max_speed = 0; + cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); + if (cell) + pdata->max_speed = fdt32_to_cpu(*cell); + + return ret; +} + +static const struct udevice_id npcm750_eth_ids[] = { + { .compatible = "nuvoton,npcm750-emc" }, + { } +}; + +U_BOOT_DRIVER(eth_npcm750) = { + .name = "eth_npcm750", + .id = UCLASS_ETH, + .of_match = npcm750_eth_ids, + .of_to_plat = npcm750_eth_ofdata_to_platdata, + .bind = npcm750_eth_bind, + .probe = npcm750_eth_probe, + .remove = npcm750_eth_remove, + .ops = &npcm750_eth_ops, + .priv_auto = sizeof(struct npcm750_eth_dev), + .plat_auto = sizeof(struct npcm750_eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; -- 2.17.1

3 2

[PATCH] net: mpc8xx_fec: Migrate to DM_ETH
by Christophe Leroy 08 Aug '22

08 Aug '22

Migrate mpc8xx_fec driver to DM_ETH. Signed-off-by: Christophe Leroy <christophe.leroy(a)csgroup.eu> --- arch/powerpc/cpu/mpc8xx/cpu.c | 12 --- arch/powerpc/dts/mcr3000.dts | 4 + configs/MCR3000_defconfig | 1 + drivers/net/Kconfig | 1 + drivers/net/mpc8xx_fec.c | 189 ++++++++++++++++++---------------- include/netdev.h | 1 - 6 files changed, 104 insertions(+), 104 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 6d16ed084e..0ccb9f6df6 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -266,15 +266,3 @@ unsigned long get_tbclk(void) return oscclk / 16; } - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(struct bd_info *bis) -{ -#if defined(CONFIG_MPC8XX_FEC) - fec_initialize(bis); -#endif - return 0; -} diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts index 5abf111dc5..5f32d8a2e5 100644 --- a/arch/powerpc/dts/mcr3000.dts +++ b/arch/powerpc/dts/mcr3000.dts @@ -16,6 +16,10 @@ compatible = "fsl,pq1-smc"; }; + FEC: fec@0 { + compatible = "fsl,pq1-fec1"; + }; + chosen { stdout-path = &SERIAL; }; diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index f99a830b54..5de015b1ba 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -88,3 +88,4 @@ CONFIG_DM_SERIAL=y CONFIG_WDT=y CONFIG_SHA256=y CONFIG_LZMA=y +CONFIG_DM_ETH=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index a6171a7c7f..cb9547f9be 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -704,6 +704,7 @@ config RENESAS_RAVB config MPC8XX_FEC bool "Fast Ethernet Controller on MPC8XX" depends on MPC8xx + depends on DM_ETH select MII help This driver implements support for the Fast Ethernet Controller diff --git a/drivers/net/mpc8xx_fec.c b/drivers/net/mpc8xx_fec.c index 4eb8260281..78337731e1 100644 --- a/drivers/net/mpc8xx_fec.c +++ b/drivers/net/mpc8xx_fec.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif #ifdef CONFIG_SYS_DISCOVER_PHY -static int mii_discover_phy(struct eth_device *dev); +static int mii_discover_phy(struct udevice *dev); #endif int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg); @@ -111,50 +111,24 @@ struct common_buf_desc { static struct common_buf_desc __iomem *rtx; -static int fec_send(struct eth_device *dev, void *packet, int length); -static int fec_recv(struct eth_device *dev); -static int fec_init(struct eth_device *dev, struct bd_info *bd); -static void fec_halt(struct eth_device *dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) static void __mii_init(void); #endif -int fec_initialize(struct bd_info *bis) +static int fec_probe(struct udevice *dev) { - struct eth_device *dev; - struct ether_fcc_info_s *efis; + struct ether_fcc_info_s *efis = dev_get_priv(dev); + int index = dev_get_driver_data(dev); int i; for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) { - dev = malloc(sizeof(*dev)); - if (dev == NULL) - hang(); + if (ether_fcc_info[i].ether_index != index) + continue; - memset(dev, 0, sizeof(*dev)); + memcpy(efis, &ether_fcc_info[i], sizeof(*efis)); - /* for FEC1 make sure that the name of the interface is the same - as the old one for compatibility reasons */ - if (i == 0) - strcpy(dev->name, "FEC"); - else - sprintf(dev->name, "FEC%d", - ether_fcc_info[i].ether_index + 1); - - efis = &ether_fcc_info[i]; - - /* - * reset actual phy addr - */ efis->actual_phy_addr = -1; - dev->priv = efis; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - eth_register(dev); - #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) int retval; struct mii_dev *mdiodev = mdio_alloc(); @@ -169,13 +143,13 @@ int fec_initialize(struct bd_info *bis) return retval; #endif } - return 1; + return 0; } -static int fec_send(struct eth_device *dev, void *packet, int length) +static int fec_send(struct udevice *dev, void *packet, int length) { int j, rc; - struct ether_fcc_info_s *efis = dev->priv; + struct ether_fcc_info_s *efis = dev_get_priv(dev); fec_t __iomem *fecp = (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); @@ -217,59 +191,57 @@ static int fec_send(struct eth_device *dev, void *packet, int length) return rc; } -static int fec_recv(struct eth_device *dev) +static int fec_recv(struct udevice *dev, int flags, uchar **packetp) { - struct ether_fcc_info_s *efis = dev->priv; - fec_t __iomem *fecp = - (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); int length; - for (;;) { - /* section 16.9.23.2 */ - if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - - length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen); + /* section 16.9.23.2 */ + if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) + return -EAGAIN; - if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) { - uchar *rx = net_rx_packets[rxIdx]; + length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen); - length -= 4; + if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) { + uchar *rx = net_rx_packets[rxIdx]; #if defined(CONFIG_CMD_CDP) - if ((rx[0] & 1) != 0 && - memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 && - !is_cdp_packet((uchar *)rx)) - rx = NULL; + if ((rx[0] & 1) != 0 && + memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 && + !is_cdp_packet((uchar *)rx)) + return 0; #endif - /* - * Pass the packet up to the protocol layers. - */ - if (rx != NULL) - net_process_received_packet(rx, length); - } + *packetp = rx; - /* Give the buffer back to the FEC. */ - out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0); - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, - BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY); - rxIdx++; - } + return length - 4; + } else { + return 0; + } +} - /* Try to fill Buffer Descriptors */ - /* Descriptor polling active */ - out_be32(&fecp->fec_r_des_active, 0x01000000); +static int fec_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct ether_fcc_info_s *efis = dev_get_priv(dev); + fec_t __iomem *fecp = + (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); + + /* Give the buffer back to the FEC. */ + out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0); + + /* wrap around buffer index when necessary */ + if ((rxIdx + 1) >= PKTBUFSRX) { + out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, + BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + rxIdx = 0; + } else { + out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY); + rxIdx++; } - return length; + /* Try to fill Buffer Descriptors */ + /* Descriptor polling active */ + out_be32(&fecp->fec_r_des_active, 0x01000000); + + return 0; } /************************************************************** @@ -296,9 +268,9 @@ static int fec_recv(struct eth_device *dev) #if defined(CONFIG_RMII) -static inline void fec_10Mbps(struct eth_device *dev) +static inline void fec_10Mbps(struct udevice *dev) { - struct ether_fcc_info_s *efis = dev->priv; + struct ether_fcc_info_s *efis = dev_get_priv(dev); int fecidx = efis->ether_index; uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; @@ -309,9 +281,9 @@ static inline void fec_10Mbps(struct eth_device *dev) setbits_be32(&immr->im_cpm.cp_cptr, mask); } -static inline void fec_100Mbps(struct eth_device *dev) +static inline void fec_100Mbps(struct udevice *dev) { - struct ether_fcc_info_s *efis = dev->priv; + struct ether_fcc_info_s *efis = dev_get_priv(dev); int fecidx = efis->ether_index; uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; @@ -324,9 +296,9 @@ static inline void fec_100Mbps(struct eth_device *dev) #endif -static inline void fec_full_duplex(struct eth_device *dev) +static inline void fec_full_duplex(struct udevice *dev) { - struct ether_fcc_info_s *efis = dev->priv; + struct ether_fcc_info_s *efis = dev_get_priv(dev); fec_t __iomem *fecp = (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); @@ -334,9 +306,9 @@ static inline void fec_full_duplex(struct eth_device *dev) setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */ } -static inline void fec_half_duplex(struct eth_device *dev) +static inline void fec_half_duplex(struct udevice *dev) { - struct ether_fcc_info_s *efis = dev->priv; + struct ether_fcc_info_s *efis = dev_get_priv(dev); fec_t __iomem *fecp = (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); @@ -497,9 +469,10 @@ static int fec_reset(fec_t __iomem *fecp) return 0; } -static int fec_init(struct eth_device *dev, struct bd_info *bd) +static int fec_start(struct udevice *dev) { - struct ether_fcc_info_s *efis = dev->priv; + struct eth_pdata *plat = dev_get_plat(dev); + struct ether_fcc_info_s *efis = dev_get_priv(dev); immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; fec_t __iomem *fecp = (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); @@ -529,7 +502,7 @@ static int fec_init(struct eth_device *dev, struct bd_info *bd) /* Set station address */ -#define ea dev->enetaddr +#define ea plat->enetaddr out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | ea[3]); out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]); @@ -665,9 +638,9 @@ static int fec_init(struct eth_device *dev, struct bd_info *bd) } -static void fec_halt(struct eth_device *dev) +static void fec_stop(struct udevice *dev) { - struct ether_fcc_info_s *efis = dev->priv; + struct ether_fcc_info_s *efis = dev_get_priv(dev); fec_t __iomem *fecp = (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); int i; @@ -750,7 +723,7 @@ mii_send(uint mii_cmd) #endif #if defined(CONFIG_SYS_DISCOVER_PHY) -static int mii_discover_phy(struct eth_device *dev) +static int mii_discover_phy(struct udevice *dev) { #define MAX_PHY_PASSES 11 uint phyno; @@ -854,3 +827,37 @@ int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, return 0; } #endif + +static const struct eth_ops fec_ops = { + .start = fec_start, + .send = fec_send, + .recv = fec_recv, + .stop = fec_stop, + .free_pkt = fec_free_pkt, +}; + +static const struct udevice_id fec_ids[] = { +#ifdef CONFIG_ETHER_ON_FEC1 + { + .compatible = "fsl,pq1-fec1", + .data = 0, + }, +#endif +#ifdef CONFIG_ETHER_ON_FEC2 + { + .compatible = "fsl,pq1-fec2", + .data = 1, + }, +#endif + { } +}; + +U_BOOT_DRIVER(fec) = { + .name = "fec", + .id = UCLASS_ETH, + .of_match = fec_ids, + .probe = fec_probe, + .ops = &fec_ops, + .priv_auto = sizeof(struct ether_fcc_info_s), + .plat_auto = sizeof(struct eth_pdata), +}; diff --git a/include/netdev.h b/include/netdev.h index fb18f09893..b3f8584e90 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -42,7 +42,6 @@ int eepro100_initialize(struct bd_info *bis); int ep93xx_eth_initialize(u8 dev_num, int base_addr); int eth_3com_initialize (struct bd_info * bis); int ethoc_initialize(u8 dev_num, int base_addr); -int fec_initialize (struct bd_info *bis); int fecmxc_initialize(struct bd_info *bis); int fecmxc_initialize_multi(struct bd_info *bis, int dev_id, int phy_id, uint32_t addr); -- 2.35.1

3 2

[PATCH] net: dwc_eth_qos: lift parsing of max-speed DT property to common code
by Rasmus Villemoes 08 Aug '22

08 Aug '22

I have an iMX8MP with a ti,dp83867 phy in front of the eqos interface. The phy is Gbit capable - however, the C and D differential pairs are not physically routed to the RJ45 connector. So I need to prevent the phy from advertising 1000Mbps. The necessary code is almost already there in the form of a phy_set_supported() call in eqos_start(), but the max-speed DT property is currently only parsed in eqos_probe_resources_stm32(). Lift that parsing to eqos_probe(). Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- drivers/net/dwc_eth_qos.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 38ccb735ee..8a54e02114 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1692,8 +1692,6 @@ static int eqos_probe_resources_stm32(struct udevice *dev) if (ret) return -EINVAL; - eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); - ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); if (ret) { pr_err("clk_get_by_name(master_bus) failed: %d", ret); @@ -1842,6 +1840,8 @@ static int eqos_probe(struct udevice *dev) eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE); eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE); + eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); + ret = eqos_probe_resources_core(dev); if (ret < 0) { pr_err("eqos_probe_resources_core() failed: %d", ret); -- 2.31.1

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