August 2022 - U-Boot

[PATCH] zynq: Convert arm twd timer to DM driver
by Stefan Herbrechtsmeier 09 Aug '22

09 Aug '22

From: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> --- arch/arm/Kconfig | 3 + arch/arm/dts/zynq-7000.dtsi | 1 + arch/arm/mach-zynq/Makefile | 1 - arch/arm/mach-zynq/clk.c | 6 +- arch/arm/mach-zynq/timer.c | 113 ---------------------------------- drivers/timer/Kconfig | 6 ++ drivers/timer/Makefile | 1 + drivers/timer/arm_twd_timer.c | 108 ++++++++++++++++++++++++++++++++ 8 files changed, 123 insertions(+), 116 deletions(-) delete mode 100644 arch/arm/mach-zynq/timer.c create mode 100644 drivers/timer/arm_twd_timer.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 949ebb46ba..bccdc6dfd8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1249,6 +1249,7 @@ config ARCH_VF610 config ARCH_ZYNQ bool "Xilinx Zynq based platform" + select ARM_TWD_TIMER select CLK select CLK_ZYNQ select CPU_V7A @@ -1268,7 +1269,9 @@ config ARCH_ZYNQ select SPL_DM_SPI_FLASH if SPL select SPL_OF_CONTROL if SPL select SPL_SEPARATE_BSS if SPL + select SPL_TIMER if SPL select SUPPORT_SPL + select TIMER imply ARCH_EARLY_INIT_R imply BOARD_LATE_INIT imply CMD_CLK diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 37155df0fd..a7ca00fb76 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -416,6 +416,7 @@ }; scutimer: timer@f8f00600 { + u-boot,dm-pre-reloc; interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index 8737f434d9..d9b2b999e1 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -6,7 +6,6 @@ # (C) Copyright 2008 # Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> -obj-y := timer.o obj-y += cpu.o obj-y += ddrc.o obj-y += slcr.o diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c index 27f6bf2183..1945f60e08 100644 --- a/arch/arm/mach-zynq/clk.c +++ b/arch/arm/mach-zynq/clk.c @@ -52,10 +52,12 @@ int set_cpu_clk_info(void) return ret; rate = clk_get_rate(&clk) / 1000000; - if (i) + if (i) { gd->bd->bi_ddr_freq = rate; - else + } else { gd->bd->bi_arm_freq = rate; + gd->cpu_clk = clk_get_rate(&clk); + } clk_free(&clk); } diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c deleted file mode 100644 index a51822a530..0000000000 --- a/arch/arm/mach-zynq/timer.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG - * Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> - * - * Copyright (C) 2012 Michal Simek <monstr(a)monstr.eu> - * Copyright (C) 2011-2017 Xilinx, Inc. All rights reserved. - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. <philippe.robin(a)arm.com> - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> - * - * (C) Copyright 2003 - * Texas Instruments <www.ti.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger(a)sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu(a)sysgo.de> - */ - -#include <clk.h> -#include <common.h> -#include <div64.h> -#include <dm.h> -#include <init.h> -#include <time.h> -#include <malloc.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/clk.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct scu_timer { - u32 load; /* Timer Load Register */ - u32 counter; /* Timer Counter Register */ - u32 control; /* Timer Control Register */ -}; - -static struct scu_timer *timer_base = - (struct scu_timer *)ZYNQ_SCUTIMER_BASEADDR; - -#define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */ -#define SCUTIMER_CONTROL_PRESCALER_SHIFT 8 -#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */ -#define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */ - -#define TIMER_LOAD_VAL 0xFFFFFFFF -#define TIMER_PRESCALE 255 - -int timer_init(void) -{ - const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK | - (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) | - SCUTIMER_CONTROL_ENABLE_MASK; - - struct udevice *dev; - struct clk clk; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_CLK, - DM_DRIVER_GET(zynq_clk), &dev); - if (ret) - return ret; - - clk.id = cpu_6or4x_clk; - ret = clk_request(dev, &clk); - if (ret < 0) - return ret; - - gd->cpu_clk = clk_get_rate(&clk); - - clk_free(&clk); - - gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1); - - /* Load the timer counter register */ - writel(0xFFFFFFFF, &timer_base->load); - - /* - * Start the A9Timer device - * Enable Auto reload mode, Clear prescaler control bits - * Set prescaler value, Enable the decrementer - */ - clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK, - emask); - - /* Reset time */ - gd->arch.lastinc = readl(&timer_base->counter) / - (gd->arch.timer_rate_hz / CONFIG_SYS_HZ); - gd->arch.tbl = 0; - - return 0; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return gd->arch.timer_rate_hz; -} diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 20b5af7e26..1e2b6566c6 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -73,6 +73,12 @@ config ARC_TIMER usually at least one of them exists. Either of them is supported in U-Boot. +config ARM_TWD_TIMER + bool "ARM timer watchdog (TWD) timer support" + depends on TIMER && CLK + help + Select this to enable support for the ARM global timer watchdog timer. + config AST_TIMER bool "Aspeed ast2400/ast2500 timer support" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index d9822a5370..4db03fe09c 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -6,6 +6,7 @@ obj-y += timer-uclass.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o +obj-$(CONFIG_ARM_TWD_TIMER) += arm_twd_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o diff --git a/drivers/timer/arm_twd_timer.c b/drivers/timer/arm_twd_timer.c new file mode 100644 index 0000000000..40ccd16587 --- /dev/null +++ b/drivers/timer/arm_twd_timer.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2022 Weidmüller Interface GmbH & Co. KG + * Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> + * + * Copyright (C) 2012 Michal Simek <monstr(a)monstr.eu> + * Copyright (C) 2011-2017 Xilinx, Inc. All rights reserved. + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. <philippe.robin(a)arm.com> + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * (C) Copyright 2003 + * Texas Instruments <www.ti.com> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu(a)sysgo.de> + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <timer.h> +#include <linux/bitops.h> + +#include <asm/io.h> + +#define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */ +#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */ +#define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */ + +#define TIMER_LOAD_VAL 0xFFFFFFFF + +struct arm_twd_timer_regs { + u32 load; /* Timer Load Register */ + u32 counter; /* Timer Counter Register */ + u32 control; /* Timer Control Register */ +}; + +struct arm_twd_timer_priv { + struct arm_twd_timer_regs *base; +}; + +static u64 arm_twd_timer_get_count(struct udevice *dev) +{ + struct arm_twd_timer_priv *priv = dev_get_priv(dev); + struct arm_twd_timer_regs *regs = priv->base; + u32 count = TIMER_LOAD_VAL - readl(&regs->counter); + + return timer_conv_64(count); +} + +static int arm_twd_timer_probe(struct udevice *dev) +{ + struct arm_twd_timer_priv *priv = dev_get_priv(dev); + struct arm_twd_timer_regs *regs; + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = (struct arm_twd_timer_regs *)addr; + + regs = priv->base; + + /* Load the timer counter register */ + writel(0xFFFFFFFF, &regs->load); + + /* + * Start the A9Timer device + * Enable Auto reload mode, Clear prescaler control bits + * Set prescaler value, Enable the decrementer + */ + clrsetbits_le32(&regs->control, SCUTIMER_CONTROL_PRESCALER_MASK, + SCUTIMER_CONTROL_AUTO_RELOAD_MASK | + SCUTIMER_CONTROL_ENABLE_MASK); + + return 0; +} + +static const struct timer_ops arm_twd_timer_ops = { + .get_count = arm_twd_timer_get_count, +}; + +static const struct udevice_id arm_twd_timer_ids[] = { + { .compatible = "arm,cortex-a9-twd-timer" }, + {} +}; + +U_BOOT_DRIVER(arm_twd_timer) = { + .name = "arm_twd_timer", + .id = UCLASS_TIMER, + .of_match = arm_twd_timer_ids, + .priv_auto = sizeof(struct arm_twd_timer_priv), + .probe = arm_twd_timer_probe, + .ops = &arm_twd_timer_ops, +}; -- 2.30.2

2 1

[PATCH] arm: dts: qcom: Sync pinctrl DT nodes with Linux bindings
by Sumit Garg 09 Aug '22

09 Aug '22

Currently for all Qcom SoCs/boards there are separate compatibles for GPIO and pinctrl. But this is inconsistent with official (upstream) Linux bindings which requires only a single compatible "qcom,<SoC name>-pinctrl" and there is no such compatible property as "qcom,tlmm-<SoC name>". So fix this inconsistency for Qcom SoCs in order to comply with upstream DT bindings. This is done via removing compatibles from "msm_gpio" driver and via binding to "msm_gpio" driver from pinctrl driver in case "gpio-controller" property is specified for pinctrl node. Suggested-by: Stephan Gerhold <stephan(a)gerhold.net> Signed-off-by: Sumit Garg <sumit.garg(a)linaro.org> --- This is based on top of mine other patch-set [1]. Although, I have tested it on db845c and qcs404-evb but I would like other board maintainers to test it as well. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=309135 arch/arm/dts/dragonboard410c-uboot.dtsi | 2 +- arch/arm/dts/dragonboard410c.dts | 17 +++----- arch/arm/dts/dragonboard820c-uboot.dtsi | 2 +- arch/arm/dts/dragonboard820c.dts | 4 +- arch/arm/dts/qcom-ipq4019.dtsi | 18 +++------ arch/arm/dts/qcs404-evb.dts | 2 +- arch/arm/dts/sdm845.dtsi | 2 +- arch/arm/mach-ipq40xx/pinctrl-snapdragon.c | 31 ++++++++++++++- arch/arm/mach-snapdragon/Makefile | 2 +- arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 39 ++++++++++++++++--- drivers/gpio/msm_gpio.c | 10 +---- 11 files changed, 83 insertions(+), 46 deletions(-) diff --git a/arch/arm/dts/dragonboard410c-uboot.dtsi b/arch/arm/dts/dragonboard410c-uboot.dtsi index 9c1be2566f..e4fecaa19e 100644 --- a/arch/arm/dts/dragonboard410c-uboot.dtsi +++ b/arch/arm/dts/dragonboard410c-uboot.dtsi @@ -14,7 +14,7 @@ soc { u-boot,dm-pre-reloc; - qcom,tlmm@1000000 { + pinctrl@1000000 { u-boot,dm-pre-reloc; uart { diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index 7e56140df2..e0452b270c 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -60,9 +60,13 @@ reg = <0x60000 0x8000>; }; - pinctrl: qcom,tlmm@1000000 { - compatible = "qcom,tlmm-apq8016"; + soc_gpios: pinctrl@1000000 { + compatible = "qcom,apq8016-pinctrl"; reg = <0x1000000 0x400000>; + gpio-controller; + gpio-count = <122>; + gpio-bank-name="soc"; + #gpio-cells = <2>; blsp1_uart: uart { function = "blsp1_uart"; @@ -86,15 +90,6 @@ pinctrl-0 = <&blsp1_uart>; }; - soc_gpios: pinctrl@1000000 { - compatible = "qcom,apq8016-pinctrl"; - reg = <0x1000000 0x300000>; - gpio-controller; - gpio-count = <122>; - gpio-bank-name="soc"; - #gpio-cells = <2>; - }; - ehci@78d9000 { compatible = "qcom,ehci-host"; reg = <0x78d9000 0x400>; diff --git a/arch/arm/dts/dragonboard820c-uboot.dtsi b/arch/arm/dts/dragonboard820c-uboot.dtsi index 8610d7ec37..2270ac73bf 100644 --- a/arch/arm/dts/dragonboard820c-uboot.dtsi +++ b/arch/arm/dts/dragonboard820c-uboot.dtsi @@ -13,7 +13,7 @@ soc { u-boot,dm-pre-reloc; - qcom,tlmm@1010000 { + pinctrl@1010000 { u-boot,dm-pre-reloc; uart { diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts index 1114ddd7d3..1a6e37887f 100644 --- a/arch/arm/dts/dragonboard820c.dts +++ b/arch/arm/dts/dragonboard820c.dts @@ -64,8 +64,8 @@ reg = <0x300000 0x90000>; }; - pinctrl: qcom,tlmm@1010000 { - compatible = "qcom,tlmm-apq8096"; + pinctrl: pinctrl@1010000 { + compatible = "qcom,msm8916-pinctrl"; reg = <0x1010000 0x400000>; blsp8_uart: uart { diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi index 7a52ea2c4e..181732d262 100644 --- a/arch/arm/dts/qcom-ipq4019.dtsi +++ b/arch/arm/dts/qcom-ipq4019.dtsi @@ -75,9 +75,13 @@ u-boot,dm-pre-reloc; }; - pinctrl: qcom,tlmm@1000000 { - compatible = "qcom,tlmm-ipq4019"; + soc_gpios: pinctrl@1000000 { + compatible = "qcom,ipq4019-pinctrl"; reg = <0x1000000 0x300000>; + gpio-controller; + gpio-count = <100>; + gpio-bank-name="soc"; + #gpio-cells = <2>; u-boot,dm-pre-reloc; }; @@ -90,16 +94,6 @@ u-boot,dm-pre-reloc; }; - soc_gpios: pinctrl@1000000 { - compatible = "qcom,ipq4019-pinctrl"; - reg = <0x1000000 0x300000>; - gpio-controller; - gpio-count = <100>; - gpio-bank-name="soc"; - #gpio-cells = <2>; - u-boot,dm-pre-reloc; - }; - blsp1_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x78b5000 0x600>; diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts index 4f0ae20bdb..09687e1fd3 100644 --- a/arch/arm/dts/qcs404-evb.dts +++ b/arch/arm/dts/qcs404-evb.dts @@ -38,7 +38,7 @@ compatible = "simple-bus"; pinctrl_north@1300000 { - compatible = "qcom,tlmm-qcs404"; + compatible = "qcom,qcs404-pinctrl"; reg = <0x1300000 0x200000>; blsp1_uart2: uart { diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi index df5b6dfcfc..607af277f8 100644 --- a/arch/arm/dts/sdm845.dtsi +++ b/arch/arm/dts/sdm845.dtsi @@ -37,7 +37,7 @@ }; tlmm_north: pinctrl_north@3900000 { - compatible = "qcom,tlmm-sdm845"; + compatible = "qcom,sdm845-pinctrl"; reg = <0x3900000 0x400000>; gpio-count = <150>; gpio-controller; diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c index c51a75ee94..036fec93d7 100644 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c +++ b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c @@ -14,6 +14,8 @@ #include <dm.h> #include <errno.h> #include <asm/io.h> +#include <dm/device_compat.h> +#include <dm/lists.h> #include <dm/pinctrl.h> #include <linux/bitops.h> #include "pinctrl-snapdragon.h" @@ -110,6 +112,32 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, return 0; } +static int msm_pinctrl_bind(struct udevice *dev) +{ + ofnode node = dev_ofnode(dev); + const char *name; + int ret; + + ofnode_get_property(node, "gpio-controller", &ret); + if (ret < 0) + return 0; + + /* Get the name of gpio node */ + name = ofnode_get_name(node); + if (!name) + return -EINVAL; + + /* Bind gpio node */ + ret = device_bind_driver_to_node(dev, "gpio_msm", + name, node, NULL); + if (ret) + return ret; + + dev_dbg(dev, "bind %s\n", name); + + return 0; +} + static struct pinctrl_ops msm_pinctrl_ops = { .get_pins_count = msm_get_pins_count, .get_pin_name = msm_get_pin_name, @@ -123,7 +151,7 @@ static struct pinctrl_ops msm_pinctrl_ops = { }; static const struct udevice_id msm_pinctrl_ids[] = { - { .compatible = "qcom,tlmm-ipq4019", .data = (ulong)&ipq4019_data }, + { .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data }, { } }; @@ -134,4 +162,5 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = { .priv_auto = sizeof(struct msm_pinctrl_priv), .ops = &msm_pinctrl_ops, .probe = msm_pinctrl_probe, + .bind = msm_pinctrl_bind, }; diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 0d31f10f68..cbaaf23f6b 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -16,6 +16,6 @@ obj-y += pinctrl-snapdragon.o obj-y += pinctrl-apq8016.o obj-y += pinctrl-apq8096.o obj-y += pinctrl-qcs404.o -obj-$(CONFIG_SDM845) += pinctrl-sdm845.o +obj-y += pinctrl-sdm845.o obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index c2148a5d0a..bba1f642ae 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -10,6 +10,8 @@ #include <dm.h> #include <errno.h> #include <asm/io.h> +#include <dm/device_compat.h> +#include <dm/lists.h> #include <dm/pinctrl.h> #include <linux/bitops.h> #include "pinctrl-snapdragon.h" @@ -113,13 +115,37 @@ static struct pinctrl_ops msm_pinctrl_ops = { .get_function_name = msm_get_function_name, }; +static int msm_pinctrl_bind(struct udevice *dev) +{ + ofnode node = dev_ofnode(dev); + const char *name; + int ret; + + ofnode_get_property(node, "gpio-controller", &ret); + if (ret < 0) + return 0; + + /* Get the name of gpio node */ + name = ofnode_get_name(node); + if (!name) + return -EINVAL; + + /* Bind gpio node */ + ret = device_bind_driver_to_node(dev, "gpio_msm", + name, node, NULL); + if (ret) + return ret; + + dev_dbg(dev, "bind %s\n", name); + + return 0; +} + static const struct udevice_id msm_pinctrl_ids[] = { - { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data }, - { .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data }, -#ifdef CONFIG_SDM845 - { .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data }, -#endif - { .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data }, + { .compatible = "qcom,apq8016-pinctrl", .data = (ulong)&apq8016_data }, + { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8096_data }, + { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data }, + { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data }, { } }; @@ -130,4 +156,5 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = { .priv_auto = sizeof(struct msm_pinctrl_priv), .ops = &msm_pinctrl_ops, .probe = msm_pinctrl_probe, + .bind = msm_pinctrl_bind, }; diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index a3c3cd7824..51670f2637 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -116,20 +116,12 @@ static int msm_gpio_of_to_plat(struct udevice *dev) return 0; } -static const struct udevice_id msm_gpio_ids[] = { - { .compatible = "qcom,msm8916-pinctrl" }, - { .compatible = "qcom,apq8016-pinctrl" }, - { .compatible = "qcom,ipq4019-pinctrl" }, - { .compatible = "qcom,sdm845-pinctrl" }, - { } -}; - U_BOOT_DRIVER(gpio_msm) = { .name = "gpio_msm", .id = UCLASS_GPIO, - .of_match = msm_gpio_ids, .of_to_plat = msm_gpio_of_to_plat, .probe = msm_gpio_probe, .ops = &gpio_msm_ops, + .flags = DM_UC_FLAG_SEQ_ALIAS, .priv_auto = sizeof(struct msm_gpio_bank), }; -- 2.25.1

3 6

[PATCH] arm: mvebu: dts: Build only arch-compatible dts files
by Pali Rohár 09 Aug '22

09 Aug '22

64-bit Armada DTS files are not build correctly during compilation of 32-bit Armada boards and vice versa. So fix makefile build system to compile only those dts files which are compatible for the current build (64-bit Armada DTS files only for 64-bit builds and 32-bit Armada DTS files only for 32-bit builds). Signed-off-by: Pali Rohár <pali(a)kernel.org> --- arch/arm/dts/Makefile | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ceaa39e4b4d6..7330121dbaba 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -232,12 +232,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra210-p2571.dtb \ tegra210-p3450-0000.dtb +ifdef CONFIG_ARMADA_32BIT dtb-$(CONFIG_ARCH_MVEBU) += \ - armada-3720-db.dtb \ - armada-3720-espressobin.dtb \ - armada-3720-turris-mox.dtb \ - armada-3720-eDPU.dtb \ - armada-3720-uDPU.dtb \ armada-375-db.dtb \ armada-385-atl-x530.dtb \ armada-385-atl-x530DP.dtb \ @@ -247,12 +243,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-388-gp.dtb \ armada-388-helios4.dtb \ armada-38x-controlcenterdc.dtb \ - armada-7040-db-nand.dtb \ - armada-7040-db.dtb \ - armada-8040-clearfog-gt-8k.dtb \ - armada-8040-db.dtb \ - armada-8040-mcbin.dtb \ - armada-8040-puzzle-m801.dtb \ armada-xp-crs305-1g-4s.dtb \ armada-xp-crs305-1g-4s-bit.dtb \ armada-xp-crs326-24g-2s.dtb \ @@ -263,7 +253,20 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ - armada-xp-theadorable.dtb \ + armada-xp-theadorable.dtb +else +dtb-$(CONFIG_ARCH_MVEBU) += \ + armada-3720-db.dtb \ + armada-3720-espressobin.dtb \ + armada-3720-turris-mox.dtb \ + armada-3720-eDPU.dtb \ + armada-3720-uDPU.dtb \ + armada-7040-db-nand.dtb \ + armada-7040-db.dtb \ + armada-8040-clearfog-gt-8k.dtb \ + armada-8040-db.dtb \ + armada-8040-mcbin.dtb \ + armada-8040-puzzle-m801.dtb \ cn9130-db-A.dtb \ cn9130-db-B.dtb \ cn9131-db-A.dtb \ @@ -272,6 +275,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ cn9132-db-B.dtb \ cn9130-crb-A.dtb \ cn9130-crb-B.dtb +endif dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ -- 2.20.1

2 2

[PATCH] pci: pci_mvebu: Add support for reset-gpios
by Pali Rohár 09 Aug '22

09 Aug '22

Release PERST# signal via GPIO when "reset-gpios" is defined in device tree. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/pci/pci_mvebu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index d80f87e0cfc6..269c027db204 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -22,6 +22,7 @@ #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> +#include <asm-generic/gpio.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/errno.h> @@ -60,6 +61,7 @@ struct mvebu_pcie { struct resource mem; void __iomem *iobase; struct resource io; + struct gpio_desc reset_gpio; u32 intregs; u32 port; u32 lane; @@ -416,6 +418,14 @@ static int mvebu_pcie_probe(struct udevice *dev) struct udevice *ctlr = pci_get_controller(dev); struct pci_controller *hose = dev_get_uclass_priv(ctlr); u32 reg; + int ret; + + /* Request for optional PERST# GPIO */ + ret = gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio, GPIOD_IS_OUT); + if (ret && ret != -ENOENT) { + printf("%s: unable to request reset-gpios: %d\n", pcie->name, ret); + return ret; + } /* * Change Class Code of PCI Bridge device to PCI Bridge (0x600400) @@ -537,6 +547,10 @@ static int mvebu_pcie_probe(struct udevice *dev) pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] = PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16); + /* Release PERST# via GPIO when it was defined */ + if (dm_gpio_is_valid(&pcie->reset_gpio)) + dm_gpio_set_value(&pcie->reset_gpio, 0); + mvebu_pcie_wait_for_link(pcie); return 0; -- 2.20.1

3 14

[PATCH] misc: atsha204a: Don't check for error when waking up the device
by Pali Rohár 09 Aug '22

09 Aug '22

The device ignores any levels or transitions on the SCL pin when the device is idle, asleep or during waking up. Linux kernel driver for atsha204a (atmel-sha204a.ko) also ignores return value from i2c wakeup send command, see: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/dri… And also userspace Turris libatsha204 library ignores return value from wakeup send command, see: https://gitlab.nic.cz/turris/libatsha204/-/blob/v29.2/src/libatsha204/layer… U-Boot driver should do same thing. Fixes waking up ATSHA204 on Turris 1.x boards. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/misc/atsha204a-i2c.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c index 81ecb5b6177b..fa2d5948f128 100644 --- a/drivers/misc/atsha204a-i2c.c +++ b/drivers/misc/atsha204a-i2c.c @@ -103,12 +103,13 @@ int atsha204a_wakeup(struct udevice *dev) for (try = 1; try <= 10; ++try) { debug("Try %i... ", try); + /* + * The device ignores any levels or transitions on the SCL pin + * when the device is idle, asleep or during waking up. + * Don't check for error when waking up the device. + */ memset(req, 0, 4); - res = atsha204a_send(dev, req, 4); - if (res) { - debug("failed on I2C send, trying again\n"); - continue; - } + atsha204a_send(dev, req, 4); udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US); -- 2.20.1

4 6

[PATCH u-boot-marvell 1/3] arm64: a37xx: pinctrl: Fix definitions for MPP pins 20-22
by Pali Rohár 09 Aug '22

09 Aug '22

All 3 MPP pins (20, 21 and 22) can be configured individually and also can be configured to GPIO functions. Fix definitions for these MPP pins in existing pin groups. After this change GPIO function can be enabled just for one of these 3 pins. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index bb7a76baed1f..a5407a16ee36 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -200,9 +200,11 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), - PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), - PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), - PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), + PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), + PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), + "ptp", "mii"), + PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), + "ptp", "mii"), PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), "mii", "mii_err"), }; -- 2.20.1

2 8

[PATCH 0/6] SBx81LIFKW/SBx81LIFXCAT disable KIRKWOOD_GPIO
by Chris Packham 09 Aug '22

09 Aug '22

This series makes changes to use the DM gpio APIs so that KIRKWOOD_GPIO can be disabled on these boards. Chris Packham (6): ARM: kirkwood: SBx81LIFKW: remove direct access of GPIO registers ARM: kirkwood: SBx81LIFKW: update for DM_GPIO ARM: kirkwood: SBx81LIFKW: enable CMD_GPIO ARM: kirkwood: SBx81LIFKW: disable KIRKWOOD_GPIO ARM: kirkwood: SBx81LIFKW: enable CONFIG_NET_RANDOM_ETHADDR ARM: kirkwood: SBx81LIFXCAT: disable KIRKWOOD_GPIO arch/arm/dts/kirkwood-atl-sbx81lifkw.dts | 14 ++++ board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 71 ++++++++------------- configs/SBx81LIFKW_defconfig | 5 +- configs/SBx81LIFXCAT_defconfig | 1 - 4 files changed, 45 insertions(+), 46 deletions(-) -- 2.37.1

2 13

[PATCH] gpio: Remove mvgpio driver
by Chris Packham 09 Aug '22

09 Aug '22

The last user of this driver was removed in commit dee08b1999e2 ("arm: Remove gplugd board"). Remove the unused driver. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- drivers/gpio/Makefile | 1 - drivers/gpio/mvgpio.c | 97 ------------------------------------------- drivers/gpio/mvgpio.h | 53 ----------------------- 3 files changed, 151 deletions(-) delete mode 100644 drivers/gpio/mvgpio.c delete mode 100644 drivers/gpio/mvgpio.h diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 219f37e0e434..39762fa06ce9 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -24,7 +24,6 @@ obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o obj-$(CONFIG_KONA_GPIO) += kona_gpio.o -obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c deleted file mode 100644 index 12e7197daf7b..000000000000 --- a/drivers/gpio/mvgpio.c +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <contact(a)8051projects.net> - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - */ - -#include <common.h> -#include <malloc.h> -#include <asm/io.h> -#include <linux/errno.h> -#include "mvgpio.h" -#include <asm/gpio.h> - -#ifndef MV_MAX_GPIO -#define MV_MAX_GPIO 128 -#endif - -int gpio_request(unsigned gpio, const char *label) -{ - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO requested %d\n", __func__, gpio); - return -1; - } - return 0; -} - -int gpio_free(unsigned gpio) -{ - return 0; -} - -int gpio_direction_input(unsigned gpio) -{ - struct gpio_reg *gpio_reg_bank; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gcdr); - return 0; -} - -int gpio_direction_output(unsigned gpio, int value) -{ - struct gpio_reg *gpio_reg_bank; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gsdr); - gpio_set_value(gpio, value); - return 0; -} - -int gpio_get_value(unsigned gpio) -{ - struct gpio_reg *gpio_reg_bank; - u32 gpio_val; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - gpio_val = readl(&gpio_reg_bank->gplr); - - return GPIO_VAL(gpio, gpio_val); -} - -int gpio_set_value(unsigned gpio, int value) -{ - struct gpio_reg *gpio_reg_bank; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - if (value) - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gpsr); - else - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gpcr); - - return 0; -} diff --git a/drivers/gpio/mvgpio.h b/drivers/gpio/mvgpio.h deleted file mode 100644 index d68c48e63737..000000000000 --- a/drivers/gpio/mvgpio.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <contact(a)8051projects.net> - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - */ - -#ifndef __MVGPIO_H__ -#define __MVGPIO_H__ - -#include <common.h> - -/* - * GPIO Register map for Marvell SOCs - */ -struct gpio_reg { - u32 gplr; /* Pin Level Register - 0x0000 */ - u32 pad0[2]; - u32 gpdr; /* Pin Direction Register - 0x000C */ - u32 pad1[2]; - u32 gpsr; /* Pin Output Set Register - 0x0018 */ - u32 pad2[2]; - u32 gpcr; /* Pin Output Clear Register - 0x0024 */ - u32 pad3[2]; - u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */ - u32 pad4[2]; - u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */ - u32 pad5[2]; - u32 gedr; /* Edge Detect Status Register - 0x0048 */ - u32 pad6[2]; - u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */ - u32 pad7[2]; - u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ - u32 pad8[2]; - u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable - Register - 0x006C */ - u32 pad9[2]; - u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable - Register - 0x0078 */ - u32 pad10[2]; - u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable - Register - 0x0084 */ - u32 pad11[2]; - u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable - Register - 0x0090 */ - u32 pad12[2]; - u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */ -}; - -#endif /* __MVGPIO_H__ */ -- 2.37.1

3 2

[PATCH 0/5] arm: mvebu: Cleanup u-boot,dm-pre-reloc code
by Pali Rohár 09 Aug '22

09 Aug '22

This patch series cleanup u-boot,dm-pre-reloc code in 32-bit mvebu device tree files. All repeated code patterns are moved into the new mvebu-u-boot.dtsi file which is automatically included by U-Boot build process into all mvebu boards. In file mvebu-u-boot.dtsi is also enabled u-boot,dm-pre-reloc for SPI node when SPL is compiled with SPI driver for loading proper U-Boot. This avoids manually defining &spi0 { u-boot,dm-pre-reloc; }; in every armada soc which store U-Boot in SPI NOR. I tested this patch series only on Armada 385 Turris Omnia board (both UART and SPI-NOR booting). Please test it on other Armada boards. CI tests were running at: https://github.com/u-boot/u-boot/pull/203 But some x86 test failed, which must be irrelevant as this patch series did not touch code outside of arch/arm/. Pali Rohár (5): arm: mvebu: a7040/a8040/cn9130: Add spi0 dts reference arm: mvebu: Introduce mvebu-u-boot.dtsi for 32-bit Armada SoCs arm: mvebu: Remove redundant u-boot,dm-pre-reloc from all 32-bit Armada SoCs arm: mvebu: armada-xp-theadorable.dts: Move u-boot,dm-pre-reloc to -u-boot.dtsi arm: mvebu: armada-38x-controlcenterdc.dts: Move u-boot,dm-pre-reloc to -u-boot.dtsi arch/arm/dts/armada-370-xp.dtsi | 1 - arch/arm/dts/armada-375-db.dts | 3 --- arch/arm/dts/armada-375.dtsi | 2 -- arch/arm/dts/armada-385-atl-x530-u-boot.dtsi | 14 ++--------- arch/arm/dts/armada-385-db-88f6820-amc.dts | 3 --- .../dts/armada-385-turris-omnia-u-boot.dtsi | 8 +----- arch/arm/dts/armada-388-clearfog-u-boot.dtsi | 2 ++ arch/arm/dts/armada-388-gp.dts | 3 --- arch/arm/dts/armada-388-helios4-u-boot.dtsi | 2 ++ .../armada-38x-controlcenterdc-u-boot.dtsi | 25 +++++++++++++++++++ arch/arm/dts/armada-38x-controlcenterdc.dts | 20 --------------- .../arm/dts/armada-38x-solidrun-microsom.dtsi | 1 - arch/arm/dts/armada-38x.dtsi | 2 -- arch/arm/dts/armada-7040.dtsi | 3 +++ arch/arm/dts/armada-8040.dtsi | 3 +++ .../dts/armada-xp-crs305-1g-4s-u-boot.dtsi | 13 ---------- arch/arm/dts/armada-xp-crs305-1g-4s.dtsi | 1 - .../dts/armada-xp-crs326-24g-2s-u-boot.dtsi | 13 ---------- arch/arm/dts/armada-xp-crs326-24g-2s.dtsi | 1 - .../armada-xp-crs328-4c-20s-4s-u-boot.dtsi | 13 ---------- arch/arm/dts/armada-xp-crs328-4c-20s-4s.dtsi | 1 - .../dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi | 12 +-------- arch/arm/dts/armada-xp-gp-u-boot.dtsi | 19 -------------- arch/arm/dts/armada-xp-maxbcm.dts | 1 - .../dts/armada-xp-synology-ds414-u-boot.dtsi | 9 ------- arch/arm/dts/armada-xp-synology-ds414.dts | 1 - .../arm/dts/armada-xp-theadorable-u-boot.dtsi | 5 ++++ arch/arm/dts/armada-xp-theadorable.dts | 4 --- arch/arm/dts/armada-xp.dtsi | 1 - arch/arm/dts/cn9130.dtsi | 3 +++ arch/arm/dts/mvebu-u-boot.dtsi | 24 ++++++++++++++++++ 31 files changed, 71 insertions(+), 142 deletions(-) create mode 100644 arch/arm/dts/armada-38x-controlcenterdc-u-boot.dtsi delete mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi delete mode 100644 arch/arm/dts/armada-xp-crs326-24g-2s-u-boot.dtsi delete mode 100644 arch/arm/dts/armada-xp-crs328-4c-20s-4s-u-boot.dtsi delete mode 100644 arch/arm/dts/armada-xp-gp-u-boot.dtsi delete mode 100644 arch/arm/dts/armada-xp-synology-ds414-u-boot.dtsi create mode 100644 arch/arm/dts/armada-xp-theadorable-u-boot.dtsi create mode 100644 arch/arm/dts/mvebu-u-boot.dtsi -- 2.20.1

3 19

[PATCH u-boot-marvell] arm: mvebu: turris_omnia: Add Winbond SPI flash support
by Marek Behún 09 Aug '22

09 Aug '22

Some new Omnia boards will come with Winbond SPI flash. Add to defconfig. Signed-off-by: Marek Behún <kabel(a)kernel.org> --- configs/turris_omnia_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index da94ca74ac..a7f4b4153c 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -81,6 +81,7 @@ CONFIG_DM_MTD=y CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_PHY_FIXED=y -- 2.35.1

2 2