April 2022 - U-Boot

Re: [PATCH v2 1/1] riscv: alloc space exhausted
by Rick Chen 06 Apr '22

06 Apr '22

> From: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> > Sent: Tuesday, April 05, 2022 10:47 PM > To: Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com> > Cc: u-boot(a)lists.denx.de; Tom Rini <trini(a)konsulko.com>; Fabio Estevam <festevam(a)gmail.com>; Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> > Subject: [PATCH v2 1/1] riscv: alloc space exhausted > > When trying to run qemu-riscv64_smode_defconfig with 32 harts booting fails. The debug UART shows a message > > alloc space exhausted > > 32 is the current maximum number of harts for machine virt in QEMU 7.0. > > Raise the default for SYS_MALLOC_F_LEN to 16 KiB. > > Move the setting to /Kconfig where we define SYS_MALLOC_F_LEN for other architectures too. > > Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> > --- > v2: > move the setting to /Kconfig > --- > Kconfig | 2 +- > arch/riscv/Kconfig | 3 --- > 2 files changed, 1 insertion(+), 4 deletions(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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Re: ELDK for Armv8.2
by Ron Eggler 06 Apr '22

06 Apr '22

>On Mon, Apr 4, 2022 at 7:12 PM Ron Eggler <ron.eggler(a)mistywest.com> wrote: >> I'm working on a BSP that features the Reesas RZ/G2L & RZ/V2L CPUs which >> have a Cortex-A55 core onthe Arm8.2 architecture. I don't see it listed >> under https://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.4. and was >> wondering if there's a way to use ELDK for this Aarch64 architecture at >> all? >> >I would recommend you use Buildroot <https://buildroot.org/> to build a >cross compiler and pretty much everything else you need to boot and run >linux (or your custom code) on your CPU. It takes a bit to configure it and >a while to build from scratch, but it works very well. Buildroot makes >building a cross compiler extremely simple. Building a whole (linux based) >system is complicated only because there are many, many choices to make - >the actual building is trivial. Instead of Buildroot, I have now built a distribution that I can use on the platform with Yocto and it does give me U-Boot as well as an SDK with it as well. Thanks!

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[RESEND PATCH v2 0/3] sunxi: Improve automatic eMMC boot partition support
by Andre Przywara 06 Apr '22

06 Apr '22

(resent to also include forgotten U-Boot list) The Allwinner BootROM supports loading the SPL from eMMC boot partitions, but so far the SPL support for this case was a bit lacking, as it was a compile time decision, and even required a manual config change. This actually got accidentally fixed in v2021.04 (c0b417b2f1a3 "sunxi: support loading with SPL > 32KB"), but still some gaps remain: When just enabling an eMMC boot partition, but having no bootable code there, the BROM will just continue with booting from the user data partition, but U-Boot does not detect this and will try to load U-Boot proper from that boot partition. This series fixes this, by replicating the BROMs decisions in the SPL, to decide on the partition to continue loading from. Patch 1/3 prepares a generic function to take an extra argument, while patch 2/3 implements the actual algorithm. As this now allows to always have eMMC boot support on, patch 3/3 just activates this for a number of boards I could test it on. I'd like to encourage other people to test this on boards with eMMC, to enable this in the respective defconfig, maybe even centrally. Some more details on eMMC boot partition support and how to install U-Boot in there can be found in the linux-sunxi Wiki: http://linux-sunxi.org/Bootable_eMMC Cheers, Andre Changelog v1 .. v2: - drop patch 1/5 (bugfix): already merged - drop patch 3/5, as it was obsoleted by c0b417b2f1a3 - remove check for 32KB SPL limit (not applicable for H6 and beyond) - remove extra sector offset adjustment (obsoleted by c0b417b2f1a3) Andre Przywara (3): spl: mmc: extend spl_mmc_boot_mode() to take mmc argument sunxi: eMMC: Improve automatic boot source detection sunxi: defconfig: enable eMMC boot partition support arch/arm/mach-imx/spl.c | 2 +- arch/arm/mach-k3/am6_init.c | 2 +- arch/arm/mach-k3/j721e_init.c | 2 +- arch/arm/mach-omap2/boot-common.c | 2 +- arch/arm/mach-rockchip/spl.c | 2 +- arch/arm/mach-socfpga/spl_a10.c | 2 +- arch/arm/mach-socfpga/spl_gen5.c | 2 +- arch/arm/mach-stm32mp/spl.c | 2 +- arch/arm/mach-sunxi/board.c | 80 ++++++++++++++++++++++ arch/arm/mach-uniphier/mmc-boot-mode.c | 5 +- common/spl/spl_mmc.c | 4 +- configs/bananapi_m64_defconfig | 1 + configs/emlid_neutis_n5_devboard_defconfig | 1 + configs/pine64-lts_defconfig | 1 + configs/pine_h64_defconfig | 1 + include/spl.h | 3 +- 16 files changed, 97 insertions(+), 15 deletions(-) -- 2.17.5

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[PATCH 0/4] sunxi: Fixes for DM I2C drivers
by Samuel Holland 06 Apr '22

06 Apr '22

A while back, the sunxi-specific P2WI and RSB drivers were converted to support DM_I2C. Now they are used as non-DM drivers in SPL, and DM drivers in U-Boot proper. However, the DM version of the code did not fully initialize either the controller or the connected chips. So the DM driver would only work if the non-DM version had previously been used in SPL. With these bug fixes and the pinctrl series, the drivers now work on SoCs like A64 and H6, which have a PMIC but do not set it up in SPL. Samuel Holland (4): i2c: sun6i_p2wi: Initialize chips in .child_pre_probe i2c: sun6i_p2wi: Add support for DM clocks and resets i2c: sun8i_rsb: Initialize chips in .child_pre_probe i2c: sun8i_rsb: Add support for DM clocks and resets drivers/i2c/sun6i_p2wi.c | 15 ++++++++++++++- drivers/i2c/sun8i_rsb.c | 15 ++++++++++++++- 2 files changed, 28 insertions(+), 2 deletions(-) -- 2.33.1

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[PATCH v5 0/3] sunxi: TOC0 image type support
by Samuel Holland 06 Apr '22

06 Apr '22

This series adds support for the TOC0 image format used by the Allwinner secure boot ROM (SBROM). This series has been tested on the following SoCs/boards, with the eFuse burnt to enable secure mode: - A50: Ainol Q88 Tablet - A64: Pine A64 Plus - H5: Orange Pi Zero Plus - H6: Pine H64 Model B - H616: Orange Pi Zero 2 This time I also tested it on boards that are not switched to secure mode (with A64, H3, and H5). Due to both series changing Makefile.spl, the last patch depends on: https://patchwork.ozlabs.org/project/uboot/list/?series=267136 I have seen no comments on that series, so I assume that it is ready to merge along with this one. Changes in v5: - Rebased on top of suniv platform additions - Took care of additional hardcoded offset in SPL SPI code - Dropped controversial Kconfig patch Changes in v4: - Do not select TOOLS_LIBCRYPTO anywhere Changes in v3: - Removed TOOLS_LIBCRYPTO selection for sunxi, since most boards do not need it - Added __packed to all new "ABI" structs - Added entry to MAINTAINERS for sunxi tools - Fixed offset of magic passed to memcmp - Refactored functions to not return pointers (fixes ambiguous NULL) Changes in v2: - Moved certificate and key item structures out of sunxi_image.h - Renamed "main" and "item" variables for clarity - Improved error messages, and added a hint about key generation - Added a comment explaining the purpose of the various key files - Mentioned testing this code on A50 in the commit message - Moved SPL header signature checks out of sunxi_image.h - Refactored SPL header signature checks to use fewer casts - Rebase on top of Icenowy's RISC-V support series - Rename Kconfig symbols to include the full image type name Samuel Holland (3): tools: mkimage: Add Allwinner TOC0 support sunxi: Support SPL in both eGON and TOC0 images sunxi: Support building a SPL as a TOC0 image MAINTAINERS | 1 + arch/arm/include/asm/arch-sunxi/spl.h | 3 +- arch/arm/mach-sunxi/Kconfig | 2 + arch/arm/mach-sunxi/board.c | 39 +- arch/arm/mach-sunxi/spl_spi_sunxi.c | 2 +- board/sunxi/Kconfig | 24 + boot/image.c | 1 + include/image.h | 1 + include/sunxi_image.h | 37 ++ scripts/Makefile.spl | 5 +- tools/Makefile | 7 +- tools/sunxi_toc0.c | 907 ++++++++++++++++++++++++++ 12 files changed, 1013 insertions(+), 16 deletions(-) create mode 100644 board/sunxi/Kconfig create mode 100644 tools/sunxi_toc0.c -- 2.33.1

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[PATCH 0/3] sunxi: H6/H616: PRCM updates
by Jernej Skrabec 06 Apr '22

06 Apr '22

During H616 boot0 blob and H6 boot0 sources analysis, I noticed that SPL doesn't set resistor calibration and PLL LDO on H6. Tests didn't show any observable difference, but nevertheless it's better to mimick boot0 behaviour. In the process I also added names for few PRCM registers so it's clearer what code does. Please take a look. Best regards, Jernej Jernej Skrabec (3): sunxi: prcm: Add a few registers sunxi: clock: H6/H616: Add resistor calibration sunxi: clock: H6: Adjust PLL LDO before clock setup arch/arm/include/asm/arch-sunxi/prcm_sun50i.h | 10 ++++++++++ arch/arm/mach-sunxi/clock_sun50i_h6.c | 20 ++++++++++++++++--- arch/arm/mach-sunxi/dram_sun50i_h6.c | 8 +++++--- arch/arm/mach-sunxi/dram_sun50i_h616.c | 7 +++++-- 4 files changed, 37 insertions(+), 8 deletions(-) -- 2.35.1

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[PATCH v2 0/4] mkimage: sunxi_egon: add riscv support
by Icenowy Zheng 06 Apr '22

06 Apr '22

This patchset tries to make mkimage -T sunxi_egon to be able to generate an eGON.BT0 image for Allwinner RISC-V SoCs (e.g. D1). In addition, to keep the compatibility, it will still consider the architecture to be ARM when no architecture is specified. Icenowy Zheng (4): mkimage: add a flag to describe whether -A is specified mkimage: sunxi_egon: refactor for multi-architecture support mkimage: sunxi_egon: add support for riscv sunxi: specify architecture when generating SPL boot image scripts/Makefile.spl | 2 +- tools/imagetool.h | 1 + tools/mkimage.c | 1 + tools/sunxi_egon.c | 86 ++++++++++++++++++++++++++++++++++++++++---- 4 files changed, 82 insertions(+), 8 deletions(-) -- 2.30.2

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[PATCH 1/2] sunxi: add H2+ config option
by Angelo Dureghello 06 Apr '22

06 Apr '22

Add H2+ Kconfig oiption to display proper cpu at boot time, and for other future uses, if needed, to differentiate against H3. The patch does not change any board defconfig at this stage, so that nothing is broken. Tested this CONFIG_MACH_SUN8I_H2_PLUS to work properly on banana pi m2 zero. Signed-off-by: Angelo Dureghello <angelo.dureghello(a)timesys.com> --- arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/psci.c | 2 ++ arch/arm/cpu/armv7/sunxi/tzpc.c | 2 +- arch/arm/dts/Makefile | 5 +++++ arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 4 ++-- arch/arm/mach-sunxi/Kconfig | 9 +++++++++ arch/arm/mach-sunxi/board.c | 3 ++- arch/arm/mach-sunxi/cpu_info.c | 6 ++++-- arch/arm/mach-sunxi/dram_sunxi_dw.c | 4 ++-- drivers/clk/sunxi/Makefile | 1 + drivers/video/sunxi/sunxi_de2.c | 2 +- 11 files changed, 30 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 1d40d6a18d..5fdfe45401 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -8,6 +8,7 @@ obj-y += timer.o obj-$(CONFIG_MACH_SUN6I) += tzpc.o +obj-$(CONFIG_MACH_SUN8I_H2_PLUS) += tzpc.o obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 1ac50f558a..bcdbe888bc 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -79,6 +79,7 @@ static void __secure __mdelay(u32 ms) static void __secure clamp_release(u32 __maybe_unused *clamp) { #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_H2_PLUS) || \ defined(CONFIG_MACH_SUN8I_H3) || \ defined(CONFIG_MACH_SUN8I_R40) u32 tmp = 0x1ff; @@ -94,6 +95,7 @@ static void __secure clamp_release(u32 __maybe_unused *clamp) static void __secure clamp_set(u32 __maybe_unused *clamp) { #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_H2_PLUS) || \ defined(CONFIG_MACH_SUN8I_H3) || \ defined(CONFIG_MACH_SUN8I_R40) writel(0xff, clamp); diff --git a/arch/arm/cpu/armv7/sunxi/tzpc.c b/arch/arm/cpu/armv7/sunxi/tzpc.c index 0c86a21a3f..44640509ff 100644 --- a/arch/arm/cpu/armv7/sunxi/tzpc.c +++ b/arch/arm/cpu/armv7/sunxi/tzpc.c @@ -17,7 +17,7 @@ void tzpc_init(void) writel(SUN6I_TZPC_DECPORT0_RTC, &tzpc->decport0_set); #endif -#ifdef CONFIG_MACH_SUN8I_H3 +#if defined(CONFIG_MACH_SUN8I_H2_PLUS) || defined(CONFIG_MACH_SUN8I_H3) /* Enable non-secure access to all peripherals */ writel(SUN8I_H3_TZPC_DECPORT0_ALL, &tzpc->decport0_set); writel(SUN8I_H3_TZPC_DECPORT1_ALL, &tzpc->decport1_set); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b8a382d153..2e58815769 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -598,6 +598,11 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ sun8i-a83t-bananapi-m3.dtb \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dtb +dtb-$(CONFIG_MACH_SUN8I_H2_PLUS) += \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ + sun8i-h2-plus-libretech-all-h3-cc.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h2-plus-bananapi-m2-zero.dtb \ sun8i-h2-plus-libretech-all-h3-cc.dtb \ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index d4c795d89c..b7a66b91e7 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -15,7 +15,7 @@ !defined(CONFIG_MACH_SUN8I_R40) && \ !defined(CONFIG_MACH_SUN8I_V3S) #define SUNXI_SRAM_A2_BASE 0x00040000 -#ifdef CONFIG_MACH_SUN8I_H3 +#if defined(CONFIG_MACH_SUN8I_H2_PLUS) || defined(CONFIG_MACH_SUN8I_H3) #define SUNXI_SRAM_A2_SIZE (48 * 1024) /* 16+32 kiB */ #else #define SUNXI_SRAM_A2_SIZE (80 * 1024) /* 16+64 kiB */ @@ -174,7 +174,7 @@ defined(CONFIG_MACH_SUN50I) /* module sram */ #define SUNXI_SRAM_C_BASE 0x01d00000 -#ifndef CONFIG_MACH_SUN8I_H3 +#if !defined(CONFIG_MACH_SUN8I_H2_PLUS) && !defined(CONFIG_MACH_SUN8I_H3) #define SUNXI_DE_FE0_BASE 0x01e00000 #else #define SUNXI_TVE0_BASE 0x01e00000 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 1d4a4fdd0c..eae8a0e68b 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -288,6 +288,15 @@ config MACH_SUN8I_A83T select MMC_SUNXI_HAS_MODE_SWITCH select SUPPORT_SPL +config MACH_SUN8I_H2_PLUS + bool "sun8i (Allwinner H2+)" + select CPU_V7A + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select ARCH_SUPPORT_PSCI + select MACH_SUNXI_H3_H5 + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + config MACH_SUN8I_H3 bool "sun8i (Allwinner H3)" select CPU_V7A diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index d9b04f75fc..adb63e93e7 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -228,7 +228,8 @@ void s_init(void) "mcr p15, 0, r0, c1, c0, 1\n" ::: "r0"); #endif -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3 +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H2_PLUS || \ + defined CONFIG_MACH_SUN8I_H3 /* Enable non-secure access to some peripherals */ tzpc_init(); #endif diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c index ba33ef2430..429e5ce283 100644 --- a/arch/arm/mach-sunxi/cpu_info.c +++ b/arch/arm/mach-sunxi/cpu_info.c @@ -85,6 +85,8 @@ int print_cpuinfo(void) printf("CPU: Allwinner A33 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_A83T printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id()); +#elif defined CONFIG_MACH_SUN8I_H2_PLUS + printf("CPU: Allwinner H2+ (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_H3 printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id()); #elif defined CONFIG_MACH_SUN8I_R40 @@ -109,7 +111,7 @@ int print_cpuinfo(void) } #endif -#ifdef CONFIG_MACH_SUN8I_H3 +#if defined(CONFIG_MACH_SUN8I_H2_PLUS) || defined(CONFIG_MACH_SUN8I_H3) #define SIDC_PRCTL 0x40 #define SIDC_RDKEY 0x60 @@ -143,7 +145,7 @@ int sunxi_get_sid(unsigned int *sid) { #ifdef CONFIG_AXP221_POWER return axp_get_sid(sid); -#elif defined CONFIG_MACH_SUN8I_H3 +#elif defined(CONFIG_MACH_SUN8I_H2_PLUS) || defined(CONFIG_MACH_SUN8I_H3) /* * H3 SID controller has a bug, which makes the initial value of * SUNXI_SID_BASE at boot wrong. diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 9107b114df..f28c23d0c6 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -863,7 +863,7 @@ unsigned long sunxi_dram_init(void) } }, -#if defined(CONFIG_MACH_SUN8I_H3) +#if defined(CONFIG_MACH_SUN8I_H2_PLUS) || defined(CONFIG_MACH_SUN8I_H3) .dx_read_delays = SUN8I_H3_DX_READ_DELAYS, .dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS, .ac_delays = SUN8I_H3_AC_DELAYS, @@ -890,7 +890,7 @@ unsigned long sunxi_dram_init(void) * the static functions. This saves us #ifdefs, but still keeps the binary * small. */ -#if defined(CONFIG_MACH_SUN8I_H3) +#if defined(CONFIG_MACH_SUN8I_H2_PLUS) || defined(CONFIG_MACH_SUN8I_H3) uint16_t socid = SOCID_H3; #elif defined(CONFIG_MACH_SUN8I_R40) uint16_t socid = SOCID_R40; diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 4f9282a8b9..d8565b3946 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o +obj-$(CONFIG_CLK_SUN8I_H2_PLUS) += clk_h3.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index e02d359cd2..2af2ae4cac 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -84,7 +84,7 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, u32 format; /* enable clock */ -#ifdef CONFIG_MACH_SUN8I_H3 +#if defined(CONFIG_MACH_SUN8I_H2_PLUS) || defined(CONFIG_MACH_SUN8I_H3) setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4); #else setbits_le32(&de_clk_regs->rst_cfg, BIT(mux)); -- 2.32.0

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[PATCH 1/2] ram: k3-am654: Write all configuration values
by Christian Gmeiner 05 Apr '22

05 Apr '22

From: Dominic Rath <rath(a)ibv-augsburg.net> Makes it possible to use 16-bit DDR memory. Signed-off-by: Dominic Rath <rath(a)ibv-augsburg.net> Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- drivers/ram/k3-am654-ddrss.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/ram/k3-am654-ddrss.c b/drivers/ram/k3-am654-ddrss.c index 4ec12bf42e..a48ebe6ada 100644 --- a/drivers/ram/k3-am654-ddrss.c +++ b/drivers/ram/k3-am654-ddrss.c @@ -265,6 +265,16 @@ static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss) ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5); ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, cfg->ddrphy_dx2gcr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR1, cfg->ddrphy_dx2gcr1); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR2, cfg->ddrphy_dx2gcr2); + ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR3, cfg->ddrphy_dx2gcr3); + + ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, cfg->ddrphy_dx3gcr0); + ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR1, cfg->ddrphy_dx3gcr1); + ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR2, cfg->ddrphy_dx3gcr2); + ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR3, cfg->ddrphy_dx3gcr3); + ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0); ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1); ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2); -- 2.35.1

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[PATCH 0/8] ram: k3-ddrss: Enable DDRSS ECC for full DDR Space
by Dave Gerlach 05 Apr '22

05 Apr '22

Hi, This series adds support for single bit ECC in the TI DDRSS bridge inline ECC and adds required support code for AM64x EVM to enable it for the full DDR space. This ECC module checks reads and writes to and from DDR once enabled without additional action required. ECC is stored together with the data so because of this, 1/9th of the total SDRAM space is used for ECC storage and the rest 8/9th is available for system use. From system point of view this means that available SDRAM will be reduced from the end by 1/9, but otherwise SDRAM is accessed and used the same. This series adds updates to the k3-ddrss driver for configuration of the ECC, and also board and arch code to automatically resize the available DDR if ECC is enabled through DT fixup. In order to avoid duplicating information and keeping this series generic this series moves to use the "memory" dt node for the main source of DDR amount and base address instead of hard coding it which has been done for all K3 previously. All TI K3 devices that use the k3-ddrss driver have this same inline ECC, so taking this step to make this more generic will allow this to be extended more easily. By default this series does NOT actually enable ECC for the any platform due to the multi second boot time increase that comes from the ECC priming that is done as part of ECC init, but it can be enabled by adding the 'ti,ecc-enable` property to the memorycontroller node in k3-am642-r5-evm DT. Regards, Dave Dave Gerlach (8): arm: dts: k3-am642-r5-evm: Mark memory with u-boot,dm-spl board: ti: am64x: Use fdt functions for ram and bank init dt-bindings: memory-controller: Add information about ECC bindings ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs ram: k3-ddrss: Introduce ECC Functionality for full memory space board: ti: am64x: Account for DDR size fixups if ECC is enabled arm: dts: k3-am64-ddr: Add ss_cfg reg entry configs: am64x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfig arch/arm/dts/k3-am64-ddr.dtsi | 5 +- arch/arm/dts/k3-am642-r5-evm.dts | 1 + board/ti/am64x/evm.c | 74 ++++++++-- configs/am64x_evm_r5_defconfig | 1 + .../memory-controller/k3-j721e-ddrss.txt | 8 + drivers/ram/k3-ddrss/k3-ddrss.c | 138 +++++++++++++++++- include/k3-ddrss.h | 16 ++ 7 files changed, 230 insertions(+), 13 deletions(-) create mode 100644 include/k3-ddrss.h -- 2.35.0

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