April 2022 - U-Boot

[PATCH] dt-bindings: xilinx: Add missing ids for PD
by Michal Simek 05 Apr '22

05 Apr '22

There are some new power domain IDs which are used in Linux kernel that's why add them here too. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/dt-bindings/power/xlnx-versal-power.h | 11 +++++++++++ include/dt-bindings/power/xlnx-zynqmp-power.h | 11 +++++++++++ 2 files changed, 22 insertions(+) diff --git a/include/dt-bindings/power/xlnx-versal-power.h b/include/dt-bindings/power/xlnx-versal-power.h index 4a727754ad02..51d1def67739 100644 --- a/include/dt-bindings/power/xlnx-versal-power.h +++ b/include/dt-bindings/power/xlnx-versal-power.h @@ -6,6 +6,16 @@ #ifndef _DT_BINDINGS_VERSAL_POWER_H #define _DT_BINDINGS_VERSAL_POWER_H +#define PM_DEV_RPU0_0 (0x18110005U) +#define PM_DEV_RPU0_1 (0x18110006U) +#define PM_DEV_OCM_0 (0x18314007U) +#define PM_DEV_OCM_1 (0x18314008U) +#define PM_DEV_OCM_2 (0x18314009U) +#define PM_DEV_OCM_3 (0x1831400aU) +#define PM_DEV_TCM_0_A (0x1831800bU) +#define PM_DEV_TCM_0_B (0x1831800cU) +#define PM_DEV_TCM_1_A (0x1831800dU) +#define PM_DEV_TCM_1_B (0x1831800eU) #define PM_DEV_USB_0 (0x18224018U) #define PM_DEV_GEM_0 (0x18224019U) #define PM_DEV_GEM_1 (0x1822401aU) @@ -38,6 +48,7 @@ #define PM_DEV_ADMA_5 (0x1822403aU) #define PM_DEV_ADMA_6 (0x1822403bU) #define PM_DEV_ADMA_7 (0x1822403cU) +#define PM_DEV_AMS_ROOT (0x18224055U) #define PM_DEV_AI (0x18224072U) #endif diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h index 0d9a412fd5e0..e7eb0960480a 100644 --- a/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -6,6 +6,16 @@ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H +#define PD_RPU_0 6 +#define PD_RPU_1 7 +#define PD_OCM_BANK_0 11 +#define PD_OCM_BANK_1 12 +#define PD_OCM_BANK_2 13 +#define PD_OCM_BANK_3 14 +#define PD_TCM_BANK_0 15 +#define PD_TCM_BANK_1 16 +#define PD_TCM_BANK_2 17 +#define PD_TCM_BANK_3 18 #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 @@ -35,5 +45,6 @@ #define PD_CAN_1 48 #define PD_GPU 58 #define PD_PCIE 59 +#define PD_PL 69 #endif -- 2.35.1

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[PATCH] arm64: zynqmp: Record ID code for XCZU1EG device
by Michal Simek 05 Apr '22

05 Apr '22

Add ID code for 1eg device. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/xilinx/zynqmp/zynqmp.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index d791689f1141..668ea4b3c128 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -69,6 +69,11 @@ static const struct { u8 device; u8 variants; } zynqmp_devices[] = { + { + .id = 0x04688093, + .device = 1, + .variants = ZYNQMP_VARIANT_EG, + }, { .id = 0x04711093, .device = 2, -- 2.35.1

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[PATCH] net: phy: Fix rgmii-id phy reset timeout issue
by Michal Simek 05 Apr '22

05 Apr '22

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> While creating a phy device using phy_device_create(), we need to provide a valid phyaddr instead of 0 causing phy address being registered as 0 with mdio bus and shows mdio phy list as below ZynqMP> mdio list eth0: 0 - TI DP83867 <--> ethernet@ff0b0000 eth1: 0 - TI DP83867 <--> ethernet@ff0c0000 Also PHY soft reset is being requested on 0 instead of valid address causing "PHY reset timed out" error. So add phyaddr argument to phy_connect_phy_id() and to its prototype to create phy device with valid phyaddress. Fixes: a744a284e354 ("net: phy: Add support for ethernet-phy-id with gpio reset") Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/net/phy/ethernet_id.c | 4 ++-- drivers/net/phy/phy.c | 2 +- include/phy.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c index 5617ac3ad62f..44abc5bfb301 100644 --- a/drivers/net/phy/ethernet_id.c +++ b/drivers/net/phy/ethernet_id.c @@ -12,7 +12,7 @@ #include <asm/gpio.h> struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev, - phy_interface_t interface) + int phyaddr, phy_interface_t interface) { struct phy_device *phydev; struct ofnode_phandle_args phandle_args; @@ -61,7 +61,7 @@ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev, } id = vendor << 16 | device; - phydev = phy_device_create(bus, 0, id, false, interface); + phydev = phy_device_create(bus, phyaddr, id, false, interface); if (phydev) phydev->node = node; diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 08a37a344e65..690ed38ba622 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -1049,7 +1049,7 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, #ifdef CONFIG_PHY_ETHERNET_ID if (!phydev) - phydev = phy_connect_phy_id(bus, dev, interface); + phydev = phy_connect_phy_id(bus, dev, addr, interface); #endif #ifdef CONFIG_PHY_XILINX_GMII2RGMII diff --git a/include/phy.h b/include/phy.h index 9ea4bd42db4d..5e3da4b01b6c 100644 --- a/include/phy.h +++ b/include/phy.h @@ -479,7 +479,7 @@ struct phy_device *phy_device_create(struct mii_dev *bus, int addr, * or NULL otherwise */ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev, - phy_interface_t interface); + int phyaddr, phy_interface_t interface); static inline ofnode phy_get_ofnode(struct phy_device *phydev) { -- 2.35.1

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[PATCH] clk: zynqmp: Add support for for DP audio/video clocks
by Michal Simek 05 Apr '22

05 Apr '22

Add support for getting rate for DP audio and video clocks. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/clk/clk_zynqmp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 9038fb8befd9..45c679a627b3 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -238,6 +238,12 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id) return CRF_APB_DBG_TRACE_CTRL; case dbg_tstmp: return CRF_APB_DBG_TSTMP_CTRL; + case dp_video_ref: + return CRF_APB_DP_VIDEO_REF_CTRL; + case dp_audio_ref: + return CRF_APB_DP_AUDIO_REF_CTRL; + case dp_stc_ref: + return CRF_APB_DP_STC_REF_CTRL; case gpu_ref ... gpu_pp1_ref: return CRF_APB_GPU_REF_CTRL; case ddr_ref: @@ -673,6 +679,7 @@ static ulong zynqmp_clk_get_rate(struct clk *clk) case dll_ref: return zynqmp_clk_get_dll_rate(priv); case gem_tsu_ref: + case dp_video_ref ... dp_stc_ref: case pl0 ... pl3: case gem0_ref ... gem3_ref: case gem0_tx ... gem3_tx: -- 2.35.1

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ELDK for Armv8.2
by Ron Eggler 05 Apr '22

05 Apr '22

Hi, I'm working on a BSP that features the Reesas RZ/G2L & RZ/V2L CPUs which have a Cortex-A55 core onthe Arm8.2 architecture. I don't see it listed under https://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.4. and was wondering if there's a way to use ELDK for this Aarch64 architecture at all? Thanks, Ron

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[PATCH] xilinx: Increase max size of image from 60 to 100MB
by Michal Simek 05 Apr '22

05 Apr '22

Recently big Linux kernels can have more then 60MB that's why increase this limit to also cover these large kernels. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- include/configs/xilinx_versal.h | 2 +- include/configs/xilinx_zynqmp.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 19e09e3cafa2..9088b318ec89 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -43,7 +43,7 @@ # define PHY_ANEG_TIMEOUT 20000 #endif -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024) #define CONFIG_CLOCKS diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 494a7c4b0017..d1abe44c4558 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -58,7 +58,7 @@ # define PHY_ANEG_TIMEOUT 20000 #endif -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN (100 * 1024 * 1024) #define CONFIG_CLOCKS -- 2.35.1

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[RFC PATCH 0/3] Fix iMX6 DDR configuration issues and update toradex apalis-imx6
by Francesco Dolcini 05 Apr '22

05 Apr '22

Dear all, we do recently have debugged some spurious boot failures and crashes, about 2% of times on specific "bad" modules", on the toradex apalis imx6 [0]. We found a couple of issues in the generic imx6 ddr configuration code and we updated the apalis-imx6 memory timing to fix those. With the following patches applied we were able to run a complete validation cycle (weeks of testing for multiple SKUs) over the whole industrial temperature range (-40 to +85) without any issues. I'm sending this patch as RFC since we plan to run some additional validation testing SKUs from different batches before asking for this to be merged. [0] https://lore.kernel.org/all/20211202161428.GA104937@francesco-nb.int.torade… Francesco Dolcini (3): mx6: ddr: Restore ralat/walat in write level calibration mx6: ddr: Wait before issuing the first MRS cmd board: apalis_imx6: DDR init using mx6_dram_cfg() arch/arm/mach-imx/mx6/ddr.c | 10 +- board/toradex/apalis_imx6/apalis_imx6.c | 439 ++++++++++-------------- 2 files changed, 193 insertions(+), 256 deletions(-) -- 2.25.1

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[PATCH] powerpc: dts: p1020/p2020: Fix esdhc node name
by Pali Rohár 05 Apr '22

05 Apr '22

For compatibility with Linux kernel DTS files and also with other U-Boot powerpc DTS files, rename esdhc@2e000 node to sdhc@2e000 in p1020-post.dtsi and p2020-post.dtsi include files. Linux kernel DTS files which include these dtsi files, expect that esdhc node has name sdhc@2e000 and do not work with other node names. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- arch/powerpc/dts/p1020-post.dtsi | 2 +- arch/powerpc/dts/p2020-post.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 03b688699189..668ca0fa07e8 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -37,7 +37,7 @@ last-interrupt-source = <255>; }; - esdhc: esdhc@2e000 { + esdhc: sdhc@2e000 { compatible = "fsl,esdhc"; reg = <0x2e000 0x1000>; /* Filled in by U-Boot */ diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 0a9e81a4248c..6debae7720ad 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -31,7 +31,7 @@ last-interrupt-source = <255>; }; - esdhc: esdhc@2e000 { + esdhc: sdhc@2e000 { compatible = "fsl,esdhc"; reg = <0x2e000 0x1000>; /* Filled in by U-Boot */ -- 2.20.1

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[PATCH 0/5] mtd: rawnand: fsl_elbc: Device tree support
by Pali Rohár 05 Apr '22

05 Apr '22

This patch series adds device tree support for P2020 NAND controller in SW ECC mode. Pali Rohár (5): mtd: rawnand: fsl_elbc: Implement RNDOUT command mtd: rawnand: fsl_elbc: Add device tree support mtd: rawnand: fsl_elbc: Use ECC configuration from device tree mtd: nand: raw: Add support for DT property nand-ecc-algo=bch powerpc: dts: p2020: Add localbus node arch/powerpc/dts/p2020-post.dtsi | 7 ++ arch/powerpc/dts/p2020rdb-pc.dts | 4 ++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 4 ++ drivers/mtd/nand/raw/Kconfig | 4 ++ drivers/mtd/nand/raw/fsl_elbc_nand.c | 99 +++++++++++++++++++++------- drivers/mtd/nand/raw/nand_base.c | 6 ++ 6 files changed, 99 insertions(+), 25 deletions(-) -- 2.20.1

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Cannot add the EFI Loader to a 64-bit EFI stubbed U-Boot
by Nicklas Larsson 05 Apr '22

05 Apr '22

Dear U-Boot community, I have a default configuration based on 'efi-x86_payload64_defconfig' (64-bit EFI stub), to which I want to add the EFI_LOADER. In order to do so I also have to enable X86-64 to fulfill the "depends on" criterias in EFI_LOADER Kconfig. I'm doing this by setting X86_RUN_64BIT via the configuration editor. This dramatically changes the default generated .config file and executing 'make' on top of this leaves me with a number of errors starting with: [image: image.png] Trying to resolve it just leads me to another error, and eventually I don't understand what to do. Can someone guide me how to add the EFI Loader to my 64-bit EFI stubbed U-Boot? Is it possible? Tried it on U-Boot master 2022.04-rc4 and the latest from next without success. Thanks, Nicklas

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