April 2022 - U-Boot

[PATCH v1 0/6] Add Nuvoton NPCM750 support
by Jim Liu 08 Apr '22

08 Apr '22

The patch series add basic supoorts for NPCM750, which is Nuvoton's 3th-generation BMC (Baseboard Management Controller). Add drivers to support Clock,Timer,Uart for NPCM7xx SoC. the NPCM750 computing subsystem comprises a dual-core ARM a9 at 800MHz speed with L1/L2 caches Jim Liu (6): ARM: configs: Add defconfig for Nuvoton NPCM750 ARM: dts: Add Nuvoton NPCM750 device tree timer: npcm: Add NPCM timer support serial: npcm: Add support for Nuvoton NPCM SoCs clk: nuvoton: Add support for NPCM750 arm: nuvoton: Add support for Nuvoton NPCM750 BMC arch/arm/Kconfig | 8 + arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/nuvoton-common-npcm7xx.dtsi | 1120 +++++++++++++++++ arch/arm/dts/nuvoton-npcm750-buv-pincfg.dtsi | 132 ++ arch/arm/dts/nuvoton-npcm750-buv.dts | 198 +++ arch/arm/dts/nuvoton-npcm750.dtsi | 63 + arch/arm/dts/nuvoton-npcm7xx-uboot.dtsi | 263 ++++ arch/arm/include/asm/arch-npcm7xx/cpu.h | 28 + arch/arm/include/asm/arch-npcm7xx/gcr.h | 64 + arch/arm/include/asm/arch-npcm7xx/rst.h | 37 + arch/arm/mach-nuvoton/Kconfig | 34 + arch/arm/mach-nuvoton/Makefile | 1 + arch/arm/mach-nuvoton/npcm7xx/Kconfig | 18 + arch/arm/mach-nuvoton/npcm7xx/Makefile | 2 + arch/arm/mach-nuvoton/npcm7xx/cpu.c | 67 + .../arm/mach-nuvoton/npcm7xx/l2_cache_pl310.c | 30 + .../npcm7xx/l2_cache_pl310_init.S | 89 ++ arch/arm/mach-nuvoton/npcm7xx/reset.c | 46 + board/nuvoton/poleg/Kconfig | 31 + board/nuvoton/poleg/MAINTAINERS | 7 + board/nuvoton/poleg/Makefile | 1 + board/nuvoton/poleg/poleg_evb.c | 52 + configs/PolegRunBMC_defconfig | 50 + drivers/clk/Makefile | 1 + drivers/clk/nuvoton/Makefile | 1 + drivers/clk/nuvoton/clk_npcm7xx.c | 469 +++++++ drivers/serial/Kconfig | 7 + drivers/serial/Makefile | 1 + drivers/serial/serial_npcm.c | 150 +++ drivers/timer/Kconfig | 7 + drivers/timer/Makefile | 1 + drivers/timer/npcm-timer.c | 115 ++ include/configs/poleg.h | 77 ++ .../dt-bindings/clock/nuvoton,npcm7xx-clock.h | 46 + .../dt-bindings/reset/nuvoton,npcm7xx-reset.h | 91 ++ 36 files changed, 3309 insertions(+) create mode 100644 arch/arm/dts/nuvoton-common-npcm7xx.dtsi create mode 100644 arch/arm/dts/nuvoton-npcm750-buv-pincfg.dtsi create mode 100644 arch/arm/dts/nuvoton-npcm750-buv.dts create mode 100644 arch/arm/dts/nuvoton-npcm750.dtsi create mode 100644 arch/arm/dts/nuvoton-npcm7xx-uboot.dtsi create mode 100644 arch/arm/include/asm/arch-npcm7xx/cpu.h create mode 100644 arch/arm/include/asm/arch-npcm7xx/gcr.h create mode 100644 arch/arm/include/asm/arch-npcm7xx/rst.h create mode 100644 arch/arm/mach-nuvoton/Kconfig create mode 100644 arch/arm/mach-nuvoton/Makefile create mode 100644 arch/arm/mach-nuvoton/npcm7xx/Kconfig create mode 100644 arch/arm/mach-nuvoton/npcm7xx/Makefile create mode 100644 arch/arm/mach-nuvoton/npcm7xx/cpu.c create mode 100644 arch/arm/mach-nuvoton/npcm7xx/l2_cache_pl310.c create mode 100644 arch/arm/mach-nuvoton/npcm7xx/l2_cache_pl310_init.S create mode 100644 arch/arm/mach-nuvoton/npcm7xx/reset.c create mode 100644 board/nuvoton/poleg/Kconfig create mode 100644 board/nuvoton/poleg/MAINTAINERS create mode 100644 board/nuvoton/poleg/Makefile create mode 100644 board/nuvoton/poleg/poleg_evb.c create mode 100644 configs/PolegRunBMC_defconfig create mode 100644 drivers/clk/nuvoton/Makefile create mode 100644 drivers/clk/nuvoton/clk_npcm7xx.c create mode 100644 drivers/serial/serial_npcm.c create mode 100644 drivers/timer/npcm-timer.c create mode 100644 include/configs/poleg.h create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clock.h create mode 100644 include/dt-bindings/reset/nuvoton,npcm7xx-reset.h -- 2.17.1

3 13

[l4m-2022.04][u-boot-at91] spi: atmel-quadspi.c: Fix the buswidth adjustment between spi-mem and controller
by Tudor Ambarus 08 Apr '22

08 Apr '22

Use the spi_mem_default_supports_op() core helper in order to take into account the buswidth specified by the user in device tree. Fixes: 24c8ff4684 ("spi: Add Atmel QuadSPI driver") Signed-off-by: Tudor Ambarus <tudor.ambarus(a)microchip.com> --- drivers/spi/atmel-quadspi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 098298336d..cb64119f97 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -438,6 +438,9 @@ static bool atmel_qspi_supports_op(struct spi_slave *slave, { struct atmel_qspi *aq = dev_get_priv(slave->dev->parent); + if (!spi_mem_default_supports_op(slave, op)) + return false; + if (aq->caps->octal) { if (atmel_qspi_sama7g5_find_mode(op) < 0) return false; -- 2.25.1

2 1

[RFC PATCH 0/7] spl: Use common function for loading/parsing images
by Sean Anderson 08 Apr '22

08 Apr '22

This series adds support for loading all image types (Legacy, FIT (with and without LOAD_FIT_FULL), and i.MX) to the MMC, SPI, NOR, NET, FAT, and EXT load methods. It does this by introducing a helper function which handles the minutiae of invoking the proper parsing function, and reading the rest of the image. Hopefully, this will make it easier for load methods to support all image types that U-Boot supports, without having undocumented unsupported image types. I applied this to several loaders which were invoking spl_load_simple_fit and/or spl_parse_image_header, but I did not use it with others (e.g. DFU/RAM) which had complications in the mix. Here's some bloat-o-meter for j7200_evm_a72_defconfig with ext4 support enabled: add/remove: 1/0 grow/shrink: 2/4 up/down: 224/-232 (-8) Function old new delta spl_load - 176 +176 spl_fit_read 60 104 +44 spl_load_image_ext 364 368 +4 spl_nor_load_image 120 108 -12 spl_spi_load_image 280 232 -48 spl_load_image_fat 320 264 -56 spl_mmc_load 712 596 -116 Total: Before=264476, After=264468, chg -0.00% ext4 support is +48 bytes, because the original image support was so bare-bones (just legacy/raw images). For most boards with a few load methods (where one of them isn't ext4), this series should be no bloat or a net negative. However, in the worst case this series will add 150-180 bytes. I haven't tested most of this, so this series is marked RFC. I had a nand conversion in here as well, but dropped due to difficulties outlines in [1]. [1] https://lore.kernel.org/u-boot/c2ea7097-9e85-b9ec-e404-bd46eb83dd5b@seco.co… Sean Anderson (7): spl: Add generic spl_load function spl: Convert ext to use spl_load spl: Convert fat to spl_load spl: Convert mmc to spl_load spl: Convert net to spl_load spl: Convert nor to spl_load spl: Convert spi to spl_load common/spl/spl.c | 61 ++++++++++++++++++++++++++++++++++++ common/spl/spl_ext.c | 24 ++++++++++----- common/spl/spl_fat.c | 36 ++++------------------ common/spl/spl_mmc.c | 73 ++++---------------------------------------- common/spl/spl_net.c | 24 +++------------ common/spl/spl_nor.c | 35 ++++----------------- common/spl/spl_spi.c | 48 +++++------------------------ include/spl.h | 30 +++++++++++++++++- 8 files changed, 137 insertions(+), 194 deletions(-) -- 2.35.1.1320.gc452695387.dirty

2 17

[PATCH 1/2] usb: dwc3: Rename .select_dr_mode to .glue_configure
by Marek Vasut 08 Apr '22

08 Apr '22

Rename the select_dr_mode callback to glue_configure, the callback is used for more than enforcing controller mode even on the TI chips, so change the name to a more generic one. No functional change. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Angus Ainslie <angus(a)akkea.ca> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Kunihiko Hayashi <hayashi.kunihiko(a)socionext.com> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/usb/dwc3/dwc3-generic.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 01bd0ca190e..7e3814207e4 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -219,11 +219,11 @@ U_BOOT_DRIVER(dwc3_generic_host) = { #endif struct dwc3_glue_ops { - void (*select_dr_mode)(struct udevice *dev, int index, + void (*glue_configure)(struct udevice *dev, int index, enum usb_dr_mode mode); }; -void dwc3_ti_select_dr_mode(struct udevice *dev, int index, +void dwc3_ti_glue_configure(struct udevice *dev, int index, enum usb_dr_mode mode) { #define USBOTGSS_UTMI_OTG_STATUS 0x0084 @@ -304,7 +304,7 @@ enum dwc3_omap_utmi_mode { } struct dwc3_glue_ops ti_ops = { - .select_dr_mode = dwc3_ti_select_dr_mode, + .glue_configure = dwc3_ti_glue_configure, }; static int dwc3_glue_bind(struct udevice *parent) @@ -435,8 +435,8 @@ static int dwc3_glue_probe(struct udevice *dev) dr_mode = usb_get_dr_mode(dev_ofnode(child)); device_find_next_child(&child); - if (ops && ops->select_dr_mode) - ops->select_dr_mode(dev, index, dr_mode); + if (ops && ops->glue_configure) + ops->glue_configure(dev, index, dr_mode); index++; } -- 2.35.1

2 8

[PATCH v2] clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock
by Marek Vasut 08 Apr '22

08 Apr '22

Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX domain. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Ye Li <ye.li(a)nxp.com> --- V2: - Get and probe 24m clock without registering it again (suggested by Ye) - Add 32k clock the same way for usb_root_clk --- drivers/clk/imx/clk-imx8mp.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index c77500bcce0..041ba5321a3 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -76,6 +76,10 @@ static const char *imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; +static const char *imx8mp_hsio_axi_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m", "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", "video_pll1_out", "sys_pll1_100m",}; @@ -156,6 +160,14 @@ static const char *imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_ "sys_pll2_100m", "sys_pll3_out", "clk_ext2", "clk_ext3", "audio_pll2_out", }; +static const char *imx8mp_usb_core_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char *imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll1_800m", "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; @@ -276,7 +288,9 @@ static struct clk_ops imx8mp_clk_ops = { static int imx8mp_clk_probe(struct udevice *dev) { + struct clk osc_24m_clk, osc_32k_clk; void __iomem *base; + int ret; base = (void *)ANATOP_BASE_ADDR; @@ -324,6 +338,16 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_SYS_PLL2_500M, imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2)); clk_dm(IMX8MP_SYS_PLL2_1000M, imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); + ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk); + if (ret) + return ret; + clk_dm(IMX8MP_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev)); + + ret = clk_get_by_name(dev, "osc_32k", &osc_32k_clk); + if (ret) + return ret; + clk_dm(IMX8MP_CLK_32K, dev_get_clk_ptr(osc_32k_clk.dev)); + base = dev_read_addr_ptr(dev); if (!base) return -EINVAL; @@ -332,6 +356,7 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28)); clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); + clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380)); clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800)); clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880)); clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900)); @@ -361,6 +386,8 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80)); clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000)); clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080)); + clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite("usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100)); + clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180)); clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200)); clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900)); @@ -389,11 +416,14 @@ static int imx8mp_clk_probe(struct udevice *dev) clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0)); clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0)); clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0)); + clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "osc_32k", base + 0x44d0, 0)); + clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0)); clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0)); clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0)); clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0)); clk_dm(IMX8MP_CLK_WDOG2_ROOT, imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0)); clk_dm(IMX8MP_CLK_WDOG3_ROOT, imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0)); + clk_dm(IMX8MP_CLK_HSIO_ROOT, imx_clk_gate4("hsio_root_clk", "ipg_root", base + 0x45c0, 0)); clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0)); -- 2.35.1

3 2

[PATCH] phy: phy-imx8mq-usb: Add support for i.MX8MP USB PHY
by Marek Vasut 08 Apr '22

08 Apr '22

Add initial support for i.MX8MP USB PHY, i.MX8MP USB is similar to the i.MX8MQ, except for clock and power domain design customization. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/phy/Kconfig | 6 ++-- drivers/phy/phy-imx8mq-usb.c | 66 +++++++++++++++++++++++++++++++++--- 2 files changed, 65 insertions(+), 7 deletions(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index d79798429b1..c01d9e09b90 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -275,11 +275,11 @@ config PHY_MTK_TPHY so you can easily distinguish them by banks layout. config PHY_IMX8MQ_USB - bool "NXP i.MX8MQ USB PHY Driver" + bool "NXP i.MX8MQ/i.MX8MP USB PHY Driver" depends on PHY - depends on IMX8MQ + depends on IMX8MQ || IMX8MP help - Support the USB3.0 PHY in NXP i.MX8MQ SoC + Support the USB3.0 PHY in NXP i.MX8MQ or i.MX8MP SoC config PHY_XILINX_ZYNQMP tristate "Xilinx ZynqMP PHY driver" diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c index afbc7ad8dd4..69f01de5553 100644 --- a/drivers/phy/phy-imx8mq-usb.c +++ b/drivers/phy/phy-imx8mq-usb.c @@ -9,7 +9,9 @@ #include <dm.h> #include <errno.h> #include <generic-phy.h> +#include <linux/bitfield.h> #include <linux/bitops.h> +#include <linux/delay.h> #include <linux/err.h> #include <clk.h> @@ -68,17 +70,22 @@ #define PHY_STS0_FSVPLUS BIT(3) #define PHY_STS0_FSVMINUS BIT(2) +enum imx8mpq_phy_type { + IMX8MQ_PHY, + IMX8MP_PHY, +}; + struct imx8mq_usb_phy { #if CONFIG_IS_ENABLED(CLK) struct clk phy_clk; #endif void __iomem *base; + enum imx8mpq_phy_type type; }; static const struct udevice_id imx8mq_usb_phy_of_match[] = { - { - .compatible = "fsl,imx8mq-usb-phy", - }, + { .compatible = "fsl,imx8mq-usb-phy", .data = IMX8MQ_PHY }, + { .compatible = "fsl,imx8mp-usb-phy", .data = IMX8MP_PHY }, {}, }; @@ -111,6 +118,56 @@ static int imx8mq_usb_phy_init(struct phy *usb_phy) return 0; } +static int imx8mp_usb_phy_init(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + + /* USB3.0 PHY signal fsel for 24M ref */ + value = readl(imx_phy->base + PHY_CTRL0); + value &= ~PHY_CTRL0_FSEL_MASK; + value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M); + writel(value, imx_phy->base + PHY_CTRL0); + + /* Disable alt_clk_en and use internal MPLL clocks */ + value = readl(imx_phy->base + PHY_CTRL6); + value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN); + writel(value, imx_phy->base + PHY_CTRL6); + + value = readl(imx_phy->base + PHY_CTRL1); + value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0); + value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET; + writel(value, imx_phy->base + PHY_CTRL1); + + value = readl(imx_phy->base + PHY_CTRL0); + value |= PHY_CTRL0_REF_SSP_EN; + writel(value, imx_phy->base + PHY_CTRL0); + + value = readl(imx_phy->base + PHY_CTRL2); + value |= PHY_CTRL2_TXENABLEN0 | PHY_CTRL2_OTG_DISABLE; + writel(value, imx_phy->base + PHY_CTRL2); + + udelay(10); + + value = readl(imx_phy->base + PHY_CTRL1); + value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET); + writel(value, imx_phy->base + PHY_CTRL1); + + return 0; +} + +static int imx8mpq_usb_phy_init(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + + if (imx_phy->type == IMX8MP_PHY) + return imx8mp_usb_phy_init(usb_phy); + else + return imx8mq_usb_phy_init(usb_phy); +} + static int imx8mq_usb_phy_power_on(struct phy *usb_phy) { struct udevice *dev = usb_phy->dev; @@ -158,7 +215,7 @@ static int imx8mq_usb_phy_exit(struct phy *usb_phy) } struct phy_ops imx8mq_usb_phy_ops = { - .init = imx8mq_usb_phy_init, + .init = imx8mpq_usb_phy_init, .power_on = imx8mq_usb_phy_power_on, .power_off = imx8mq_usb_phy_power_off, .exit = imx8mq_usb_phy_exit, @@ -168,6 +225,7 @@ int imx8mq_usb_phy_probe(struct udevice *dev) { struct imx8mq_usb_phy *priv = dev_get_priv(dev); + priv->type = dev_get_driver_data(dev); priv->base = dev_read_addr_ptr(dev); if (!priv->base) -- 2.35.1

2 1

[PATCH] imx: power-domain: Add i.MX8MP support
by Marek Vasut 08 Apr '22

08 Apr '22

Add i.MX8MP power domain handling into the driver. This is based on the Linux GPCv2 driver state which is soon to be in Linux next. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/power/domain/imx8m-power-domain.c | 79 +++++++++++++++++++++++ include/dt-bindings/power/imx8mp-power.h | 46 +++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 include/dt-bindings/power/imx8mp-power.h diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index e2e41cf5fee..145f6ec0cd3 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -20,11 +20,13 @@ #include <dt-bindings/power/imx8mm-power.h> #include <dt-bindings/power/imx8mn-power.h> +#include <dt-bindings/power/imx8mp-power.h> #include <dt-bindings/power/imx8mq-power.h> DECLARE_GLOBAL_DATA_PTR; #define GPC_PGC_CPU_MAPPING 0x0ec +#define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc #define IMX8M_PCIE2_A53_DOMAIN BIT(15) #define IMX8M_OTG2_A53_DOMAIN BIT(5) @@ -38,6 +40,14 @@ DECLARE_GLOBAL_DATA_PTR; #define IMX8MN_OTG1_A53_DOMAIN BIT(4) #define IMX8MN_MIPI_A53_DOMAIN BIT(2) +#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19) +#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5) +#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4) +#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3) + +#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8 +#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4 + #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 #define GPC_PU_PGC_SW_PDN_REQ 0x104 @@ -53,8 +63,14 @@ DECLARE_GLOBAL_DATA_PTR; #define IMX8MN_OTG1_SW_Pxx_REQ BIT(2) #define IMX8MN_MIPI_SW_Pxx_REQ BIT(0) +#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17) +#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3) +#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2) +#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1) + #define GPC_M4_PU_PDN_FLG 0x1bc +#define IMX8MP_GPC_PU_PWRHSK 0x190 #define GPC_PU_PWRHSK 0x1fc #define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24)) @@ -63,6 +79,9 @@ DECLARE_GLOBAL_DATA_PTR; #define IMX8MN_HSIO_HSK_PWRDNACKN BIT(23) #define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5) +#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28) +#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12) + /* * The PGC offset values in Reference Manual * (Rev. 1, 01/2018 and the older ones) GPC chapter's @@ -80,6 +99,11 @@ DECLARE_GLOBAL_DATA_PTR; #define IMX8MN_PGC_OTG1 18 +#define IMX8MP_PGC_PCIE 13 +#define IMX8MP_PGC_USB1 14 +#define IMX8MP_PGC_USB2 15 +#define IMX8MP_PGC_HSIOMIX 29 + #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) @@ -244,6 +268,58 @@ static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = { }; #endif +#ifdef CONFIG_IMX8MP +static const struct imx_pgc_domain imx8mp_pgc_domains[] = { + [IMX8MP_POWER_DOMAIN_PCIE_PHY] = { + .bits = { + .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ, + .map = IMX8MP_PCIE_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_PCIE), + }, + + [IMX8MP_POWER_DOMAIN_USB1_PHY] = { + .bits = { + .pxx = IMX8MP_USB1_PHY_Pxx_REQ, + .map = IMX8MP_USB1_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_USB1), + }, + + [IMX8MP_POWER_DOMAIN_USB2_PHY] = { + .bits = { + .pxx = IMX8MP_USB2_PHY_Pxx_REQ, + .map = IMX8MP_USB2_PHY_A53_DOMAIN, + }, + .pgc = BIT(IMX8MP_PGC_USB2), + }, + + [IMX8MP_POWER_DOMAIN_HSIOMIX] = { + .bits = { + .pxx = IMX8MP_HSIOMIX_Pxx_REQ, + .map = IMX8MP_HSIOMIX_A53_DOMAIN, + .hskreq = IMX8MP_HSIOMIX_PWRDNREQN, + .hskack = IMX8MP_HSIOMIX_PWRDNACKN, + }, + .pgc = BIT(IMX8MP_PGC_HSIOMIX), + .keep_clocks = true, + }, +}; + +static const struct imx_pgc_regs imx8mp_pgc_regs = { + .map = IMX8MP_GPC_PGC_CPU_MAPPING, + .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ, + .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ, + .hsk = IMX8MP_GPC_PU_PWRHSK, +}; + +static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = { + .domains = imx8mp_pgc_domains, + .domains_num = ARRAY_SIZE(imx8mp_pgc_domains), + .pgc_regs = &imx8mp_pgc_regs, +}; +#endif + static int imx8m_power_domain_on(struct power_domain *power_domain) { struct udevice *dev = power_domain->dev; @@ -457,6 +533,9 @@ static const struct udevice_id imx8m_power_domain_ids[] = { #endif #ifdef CONFIG_IMX8MN { .compatible = "fsl,imx8mn-gpc", .data = (long)&imx8mn_pgc_domain_data }, +#endif +#ifdef CONFIG_IMX8MP + { .compatible = "fsl,imx8mp-gpc", .data = (long)&imx8mp_pgc_domain_data }, #endif { } }; diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h new file mode 100644 index 00000000000..3f72bf7818f --- /dev/null +++ b/include/dt-bindings/power/imx8mp-power.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Pengutronix, Sascha Hauer <kernel(a)pengutronix.de> + */ + +#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ +#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ + +#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0 +#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1 +#define IMX8MP_POWER_DOMAIN_USB1_PHY 2 +#define IMX8MP_POWER_DOMAIN_USB2_PHY 3 +#define IMX8MP_POWER_DOMAIN_MLMIX 4 +#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5 +#define IMX8MP_POWER_DOMAIN_GPU2D 6 +#define IMX8MP_POWER_DOMAIN_GPUMIX 7 +#define IMX8MP_POWER_DOMAIN_VPUMIX 8 +#define IMX8MP_POWER_DOMAIN_GPU3D 9 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10 +#define IMX8MP_POWER_DOMAIN_VPU_G1 11 +#define IMX8MP_POWER_DOMAIN_VPU_G2 12 +#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13 +#define IMX8MP_POWER_DOMAIN_HDMIMIX 14 +#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15 +#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16 +#define IMX8MP_POWER_DOMAIN_HSIOMIX 17 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18 + +#define IMX8MP_HSIOBLK_PD_USB 0 +#define IMX8MP_HSIOBLK_PD_USB_PHY1 1 +#define IMX8MP_HSIOBLK_PD_USB_PHY2 2 +#define IMX8MP_HSIOBLK_PD_PCIE 3 +#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4 + +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0 +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1 +#define IMX8MP_MEDIABLK_PD_LCDIF_1 2 +#define IMX8MP_MEDIABLK_PD_ISI 3 +#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4 +#define IMX8MP_MEDIABLK_PD_LCDIF_2 5 +#define IMX8MP_MEDIABLK_PD_ISP2 6 +#define IMX8MP_MEDIABLK_PD_ISP1 7 +#define IMX8MP_MEDIABLK_PD_DWE 8 +#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 9 + +#endif -- 2.35.1

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[PATCH v2] imx: power-domain: Add i.MX8MP HSIOMIX driver
by Marek Vasut 08 Apr '22

08 Apr '22

Add trivial driver for i.MX8MP HSIOMIX handling. This is responsible for enabling the GPCv2 power domains and clock for USB 3.0 and PCIe in the correct order. Currently supported is the USB 3.0 part which can be tested, PCIe support should be easy to add. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- V2: Drop two left over unused variables which triggered build warning --- drivers/power/domain/Kconfig | 7 ++ drivers/power/domain/Makefile | 1 + drivers/power/domain/imx8mp-hsiomix.c | 159 ++++++++++++++++++++++++++ 3 files changed, 167 insertions(+) create mode 100644 drivers/power/domain/imx8mp-hsiomix.c diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 04fc0054323..7e1b8c072fa 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -40,6 +40,13 @@ config IMX8M_POWER_DOMAIN Enable support for manipulating NXP i.MX8M on-SoC power domains via requests to the ATF. +config IMX8MP_HSIOMIX_BLKCTRL + bool "Enable i.MX8MP HSIOMIX domain driver" + depends on POWER_DOMAIN && IMX8MP + select CLK + help + Enable support for manipulating NXP i.MX8MP on-SoC HSIOMIX block controller. + config MTK_POWER_DOMAIN bool "Enable the MediaTek power domain driver" depends on POWER_DOMAIN && ARCH_MEDIATEK diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index 7c8af67dbd6..e6244776216 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o imx8-power-domain.o obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o +obj-$(CONFIG_IMX8MP_HSIOMIX_BLKCTRL) += imx8mp-hsiomix.o obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o diff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c new file mode 100644 index 00000000000..6a721a934a7 --- /dev/null +++ b/drivers/power/domain/imx8mp-hsiomix.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Marek Vasut <marex(a)denx.de> + */ + +#include <common.h> +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <power-domain-uclass.h> + +#include <dt-bindings/power/imx8mp-power.h> + +#define GPR_REG0 0x0 +#define PCIE_CLOCK_MODULE_EN BIT(0) +#define USB_CLOCK_MODULE_EN BIT(1) + +struct imx8mp_hsiomix_priv { + void __iomem *base; + struct clk clk_usb; + struct power_domain pd_bus; + struct power_domain pd_usb; + struct power_domain pd_usb_phy1; + struct power_domain pd_usb_phy2; +}; + +static int imx8mp_hsiomix_on(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev); + struct power_domain *domain; + int ret; + + ret = power_domain_on(&priv->pd_bus); + if (ret) + return ret; + + if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) { + domain = &priv->pd_usb; + } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1) { + domain = &priv->pd_usb_phy1; + } else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) { + domain = &priv->pd_usb_phy2; + } else { + ret = -EINVAL; + goto err_pd; + } + + ret = power_domain_on(domain); + if (ret) + goto err_pd; + + ret = clk_enable(&priv->clk_usb); + if (ret) + goto err_clk; + + if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) + setbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN); + + return 0; + +err_clk: + power_domain_off(domain); +err_pd: + power_domain_off(&priv->pd_bus); + return ret; +} + +static int imx8mp_hsiomix_off(struct power_domain *power_domain) +{ + struct udevice *dev = power_domain->dev; + struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev); + + if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) + clrbits_le32(priv->base + GPR_REG0, USB_CLOCK_MODULE_EN); + + clk_disable(&priv->clk_usb); + + if (power_domain->id == IMX8MP_HSIOBLK_PD_USB) + power_domain_off(&priv->pd_usb); + else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY1) + power_domain_off(&priv->pd_usb_phy1); + else if (power_domain->id == IMX8MP_HSIOBLK_PD_USB_PHY2) + power_domain_off(&priv->pd_usb_phy2); + + power_domain_off(&priv->pd_bus); + + return 0; +} + +static int imx8mp_hsiomix_of_xlate(struct power_domain *power_domain, + struct ofnode_phandle_args *args) +{ + power_domain->id = args->args[0]; + + return 0; +} + +static int imx8mp_hsiomix_probe(struct udevice *dev) +{ + struct imx8mp_hsiomix_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + + ret = clk_get_by_name(dev, "usb", &priv->clk_usb); + if (ret < 0) + return ret; + + ret = power_domain_get_by_name(dev, &priv->pd_bus, "bus"); + if (ret < 0) + goto err_pd_bus; + + ret = power_domain_get_by_name(dev, &priv->pd_usb, "usb"); + if (ret < 0) + goto err_pd_usb; + + ret = power_domain_get_by_name(dev, &priv->pd_usb_phy1, "usb-phy1"); + if (ret < 0) + goto err_pd_usb_phy1; + + ret = power_domain_get_by_name(dev, &priv->pd_usb_phy2, "usb-phy2"); + if (ret < 0) + goto err_pd_usb_phy2; + + return 0; + +err_pd_usb_phy2: + power_domain_free(&priv->pd_usb_phy1); +err_pd_usb_phy1: + power_domain_free(&priv->pd_usb); +err_pd_usb: + power_domain_free(&priv->pd_bus); +err_pd_bus: + clk_free(&priv->clk_usb); + return ret; +} + +static const struct udevice_id imx8mp_hsiomix_ids[] = { + { .compatible = "fsl,imx8mp-hsio-blk-ctrl" }, + { } +}; + +struct power_domain_ops imx8mp_hsiomix_ops = { + .on = imx8mp_hsiomix_on, + .off = imx8mp_hsiomix_off, + .of_xlate = imx8mp_hsiomix_of_xlate, +}; + +U_BOOT_DRIVER(imx8mp_hsiomix) = { + .name = "imx8mp_hsiomix", + .id = UCLASS_POWER_DOMAIN, + .of_match = imx8mp_hsiomix_ids, + .probe = imx8mp_hsiomix_probe, + .priv_auto = sizeof(struct imx8mp_hsiomix_priv), + .ops = &imx8mp_hsiomix_ops, +}; -- 2.35.1

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[PATCH] mtd: spi-nor-ids: Add Winbond W25Q128JW ID
by Marek Vasut 07 Apr '22

07 Apr '22

Add ID for Winbond W25Q128JW device. This is a 128 Mbit QSPI NOR. Tested on W25Q128JWPIM part. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Horatiu Vultur <horatiu.vultur(a)microchip.com> Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Stefan Roese <sr(a)denx.de> Cc: Vignesh R <vigneshr(a)ti.com> --- drivers/mtd/spi/spi-nor-ids.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index b551ebd75ef..e2d09fc747d 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -345,6 +345,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q256fw", 0xef6019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | -- 2.34.1

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[PATCH v3] imx8/ls10xx: Use a sane SYS_MALLOC_F_LEN default
by Fabio Estevam 07 Apr '22

07 Apr '22

From: Fabio Estevam <festevam(a)denx.de> When adding new features to imx8m boards, such as DM clock support, the malloc area can be exhausted. To avoid such issue, provide a reasonable default for the SYS_MALLOC_F_LEN size. Quoting Tom Rini: "This seems to be an area where everyone is either: - Kicking the value up a bit for themselves - Having hard to figure out problems booting the platform because it's too small a value until they see someone else picked a larger value. So lets raise these a bit and get some acks, please." Suggested-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Signed-off-by: Fabio Estevam <festevam(a)denx.de> Tested-by: Adam Ford <aford173(a)gmail.com> #imx8mm-beacon, imx8mn-beacon Tested-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- Changes since v2: - Also bump the default for imx8/layerscape - Tom - Expand the Cc list - Tom Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Kconfig b/Kconfig index 9dd9ec7f6dfb..8b346894e581 100644 --- a/Kconfig +++ b/Kconfig @@ -232,10 +232,10 @@ config SYS_MALLOC_F_LEN depends on SYS_MALLOC_F default 0x1000 if AM33XX default 0x4000 if SANDBOX - default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \ - ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \ - ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \ - ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI || ARCH_OWL) + default 0x2000 if (ARCH_MX7 || ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \ + ARCH_QEMU || ARCH_SUNXI || ARCH_OWL) + default 0x10000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_LS1012A || \ + ARCH_LS1021A || ARCH_LS1043A || ARCH_LS1046A) default 0x400 help Before relocation, memory is very limited on many platforms. Still, -- 2.25.1

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