April 2022 - U-Boot

Radxa rock-pi-3a
by Richard Kojedzinszky 09 Apr '22

09 Apr '22

Dear community, I own a rock-pi-3a board with 8G ram. Right now, radxa's u-boot is capable of detecting the whole amount during boot. Upstream u-boot shows 1G of dram installed. I've started with evb-rk3568_defconfig. What I would like to achieve is that u-boot load grub-efi, to finally boot the operating system. Howewer, with radxa uboot, and using grub-efi, the kernel sees 4G only. If I boot the kernel image directly from radxa u-boot, the whole 8G is visible. I assume that efi is broken somehow, as I get multiple warnings from kernel regarding EFI firmware. Reading radxa's u-boot, it seems that it uses ATAGs do detect memory size. Am I in the right way? Would it be beneficial to port some of that code to upstream u-boot, or are there other solutions to detect correct memory size? Thanks in advance, Richard

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[PATCH v4 00/12] Prepare RK3066 U-boot support
by Johan Jonker 09 Apr '22

09 Apr '22

This patch serie combines a number of cleanups and fixes that are needed in preparation of Rockchip RK3066 U-boot support. The common TPL/SPL files contain support for 2 timers that are not used in the early models. Change there call condition. As we are there also increase the build coverage. The existing timer driver is not prepared for OF_PLATDATA. Code was added to make it work for RK3066. Early Rockchip SoCs don't have MMC internal dma support. Add code to enable the fifo-mode and OF_PLATDATA support. Fix clock ID's when calling the clock driver. Rockchip serial driver support is split up between SYS_NS16550 for full U-boot and ROCKCHIP_SERIAL init in TPL/SPL. Make it work for more SoC models and OF_PLATDATA. Changed V4: combine series rebase style fixes === Johan Jonker (12): rockchip: move ROCKCHIP_STIMER_BASE to Kconfig rockchip: spl: change call condition rockchip_stimer_init() rockchip: tpl: change call condition rockchip_stimer_init() rockchip: spl: replace ifdef by IS_ENABLED for timer_init() call condition rockchip: tpl: use IS_ENABLED for timer_init() call condition rockchip: timer: add OF_PLATDATA support for dw-apb-timer rockchip: timer: dw-apb-timer: fix whitespace in U_BOOT_DRIVER structure rockchip: mmc: rockchip_dw_mmc: fix ciu clock index rockchip: mmc: rockchip_dw_mmc: add rk3066/rk3188 support rockchip: serial: restyle the serial_rockchip.c driver rockchip: serial: move driver alias to serial_rockchip.c rockchip: serial: Kconfig: add select SYS_NS16550 to config ROCKCHIP_SERIAL arch/arm/mach-rockchip/Kconfig | 10 ++++++ arch/arm/mach-rockchip/px30/Kconfig | 3 ++ arch/arm/mach-rockchip/rk3036/Kconfig | 3 ++ arch/arm/mach-rockchip/rk3128/Kconfig | 3 ++ arch/arm/mach-rockchip/rk322x/Kconfig | 3 ++ arch/arm/mach-rockchip/rk3288/Kconfig | 3 ++ arch/arm/mach-rockchip/rk3308/Kconfig | 10 +++--- arch/arm/mach-rockchip/rk3328/Kconfig | 3 ++ arch/arm/mach-rockchip/rk3368/Kconfig | 3 ++ arch/arm/mach-rockchip/rk3399/Kconfig | 3 ++ arch/arm/mach-rockchip/rk3568/Kconfig | 3 ++ arch/arm/mach-rockchip/spl.c | 21 ++++++----- arch/arm/mach-rockchip/tpl.c | 12 +++++-- configs/rock_defconfig | 3 +- drivers/mmc/rockchip_dw_mmc.c | 20 ++++++++--- drivers/serial/Kconfig | 1 + drivers/serial/ns16550.c | 2 -- drivers/serial/serial_rockchip.c | 39 +++++++++----------- drivers/timer/dw-apb-timer.c | 52 +++++++++++++++++++-------- include/configs/px30_common.h | 1 - include/configs/rk3036_common.h | 1 - include/configs/rk3128_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3308_common.h | 1 - include/configs/rk3328_common.h | 1 - include/configs/rk3368_common.h | 1 - include/configs/rk3399_common.h | 1 - include/configs/rk3568_common.h | 1 - 29 files changed, 137 insertions(+), 70 deletions(-) -- 2.20.1

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[PATCH 0/2] Enable booting from SCSI on rockpro64-rk3399.
by Vagrant Cascadian 09 Apr '22

09 Apr '22

This patch series adds SCSI booting to rockchip-common.h to enable scsi boot options from distro boot, and enables SCSI options in the rockpro64-rk3399 configuration. Vagrant Cascadian (2): rockchip: Enable SCSI in distro bootcmd for rk3399. rockchip: Enable AHCI/SCSI/SATA on rockpro64-rk3399. configs/rockpro64-rk3399_defconfig | 7 +++++++ include/configs/rockchip-common.h | 7 +++++++ 2 files changed, 14 insertions(+) -- 2.35.1

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[RFC Patch] arm: kirkwood: nsa310s: Use Marvell uclass mvgbe and PHY driver for DM Ethernet
by Tony Dinh 09 Apr '22

09 Apr '22

Hi all, This is a work-in-progress patch that I'm working on, to clean up the DM Ethernet code for the Zyxel NSA310S board (Kirkwood 88F6702 A1). This NSA310s board Ethernet has some quirks that it does not work quite the same way as other Kirwood boards with the similar network chip (MV88E1318), such as the Sheevaplug and the Dreamplug. Currently, in the NSA310S board file we use CONFIG_RESET_PHY_R to execute reset_phy() during initialization. And the reset_phy() code in this board file is ad-hoc, does not involve Marvell PHY driver (which it should be). So I'm following the same pattern that I've done for the Sheevaplug: use the uclass drivers/net/mvgbe.c (CONFIG_MVGBE) to bring up Ethernet, removing the reset_phy() code, and enable CONFIG_PHY_MARVEL. With this board, I could not get it to work the same way as for the Sheevaplug to bring up the PHY automatically. I had to insert the ad-hoc code to set RGMII delay in the __mvgbe_phy_init() function in mvgbe.c, so the phy_connect() call will find the PHY. The PHY Id is 1410e90, same as in the Sheevaplug and Dreamplug. Please see this in the patch below (it's only a hack to see the PHY can be brought up this way). With the Sheevaplug and Dreamplug, there is no need to do this hack. The uclass mvgbe did all the work, by the time phy_connect() is executed, the PHY was already up and working fine. And then the Marvell PHY driver kicks in, setting up the rest. Perhaps we need code in the uclass MVGBE that handles this in a generic way? These are the Marvell PHY driver functions invoked after phy_connect() was successful. This happens in all 3 boards (Sheevaplug, Dreamplug, and NSA310s). m88e1310_config m88e1011s_startup I would appreciate hearing some explanation and perhaps some suggestion/guidance about this topic. Thanks, Tony diff --git a/board/zyxel/nsa310s/nsa310s.c b/board/zyxel/nsa310s/nsa310s.c index b71de4e11f..78d472d56c 100644 --- a/board/zyxel/nsa310s/nsa310s.c +++ b/board/zyxel/nsa310s/nsa310s.c @@ -1,22 +1,49 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2015, 2021 Tony Dinh <mibodhi(a)gmail.com> + * Copyright (C) 2015, 2021-2022 Tony Dinh <mibodhi(a)gmail.com> * Copyright (C) 2015 Gerald Kerma <dreagle(a)doukki.net> */ #include <common.h> #include <init.h> -#include <miiphy.h> -#include <net.h> +#include <netdev.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/arch/mpp.h> #include <asm/global_data.h> #include <asm/io.h> -#include "nsa310s.h" +#include <linux/bitops.h> DECLARE_GLOBAL_DATA_PTR; +/* + * low GPIO's + */ +#define HDD1_GREEN_LED BIT(16) +#define HDD1_RED_LED BIT(13) +#define USB_GREEN_LED BIT(15) +#define USB_POWER BIT(21) +#define SYS_GREEN_LED BIT(28) +#define SYS_ORANGE_LED BIT(29) + +#define COPY_GREEN_LED BIT(22) +#define COPY_RED_LED BIT(23) + +#define PIN_USB_GREEN_LED 15 +#define PIN_USB_POWER 21 + +#define NSA310S_OE_LOW (~(0)) +#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER) + +/* + * high GPIO's +*/ +#define HDD2_GREEN_LED BIT(2) +#define HDD2_POWER BIT(1) + +#define NSA310S_OE_HIGH (~(0)) +#define NSA310S_VAL_HIGH (HDD2_POWER) + int board_early_init_f(void) { /* @@ -80,87 +107,7 @@ int board_init(void) return 0; } -static int fdt_get_phy_addr(const char *path) +int board_eth_init(struct bd_info *bis) { - const void *fdt = gd->fdt_blob; - const u32 *reg; - const u32 *val; - int node, phandle, addr; - - /* Find the node by its full path */ - node = fdt_path_offset(fdt, path); - if (node >= 0) { - /* Look up phy-handle */ - val = fdt_getprop(fdt, node, "phy-handle", NULL); - if (val) { - phandle = fdt32_to_cpu(*val); - if (!phandle) - return -1; - /* Follow it to its node */ - node = fdt_node_offset_by_phandle(fdt, phandle); - if (node) { - /* Look up reg */ - reg = fdt_getprop(fdt, node, "reg", NULL); - if (reg) { - addr = fdt32_to_cpu(*reg); - return addr; - } - } - } - } - return -1; -} - -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ - u16 reg; - u16 phyaddr; - char *name = "ethernet-controller@72000"; - char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0"; - - if (miiphy_set_current_dev(name)) - return; - - phyaddr = fdt_get_phy_addr(eth0_path); - if (phyaddr < 0) - return; - - /* set RGMII delay */ - miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG); - miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, &reg); - reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL); - miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg); - miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0); - - /* reset PHY */ - if (miiphy_reset(name, phyaddr)) - return; - - /* - * ZyXEL NSA310S uses the 88E1310S Alaska (interface identical to 88E1318) - * and has an MCU attached to the LED[2] via tristate interrupt - */ - - /* switch to LED register page */ - miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_LED_PG); - /* read out LED polarity register */ - miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, &reg); - /* clear 4, set 5 - LED2 low, tri-state */ - reg &= ~(MV88E1318_LED2_4); - reg |= (MV88E1318_LED2_5); - /* write back LED polarity register */ - miiphy_write(name, phyaddr, MV88E1318_LED_POL_REG, reg); - /* jump back to page 0, per the PHY chip documenation. */ - miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0); - - /* set PHY back to auto-negotiation mode */ - miiphy_write(name, phyaddr, 0x4, 0x1e1); - miiphy_write(name, phyaddr, 0x9, 0x300); - /* downshift */ - miiphy_write(name, phyaddr, 0x10, 0x3860); - miiphy_write(name, phyaddr, 0x0, 0x9140); - - printf("MV88E1318 PHY initialized on %s\n", name); + return cpu_eth_init(bis); } -#endif /* CONFIG_RESET_PHY_R */ diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index 05a6761854..07c96489c0 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_KIRKWOOD=y CONFIG_SYS_KWD_CONFIG="board/zyxel/nsa310s/kwbimage.cfg" CONFIG_SYS_TEXT_BASE=0x600000 @@ -31,6 +32,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_CMD_JFFS2=y +CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0xe0000@0x0(uboot),0x20000@0xe0000(uboot_env),0x100000@0x100000(second_stage_uboot),-@0x200000(root)" CONFIG_CMD_UBI=y @@ -47,6 +49,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=1 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y +CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_MVGBE=y CONFIG_MII=y diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 954bf86121..9aff72bc74 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -726,6 +726,13 @@ static int mvgbe_recv(struct eth_device *dev) } #endif +/* PHY related */ +#define MV88E1318_PGADR_REG 22 +#define MV88E1318_MAC_CTRL_PG 2 +#define MV88E1318_MAC_CTRL_REG 21 +#define MV88E1318_RGMII_TX_CTRL (1 << 4) +#define MV88E1318_RGMII_RX_CTRL (1 << 5) + #if defined(CONFIG_PHYLIB) || defined(CONFIG_DM_ETH) #if defined(CONFIG_DM_ETH) static struct phy_device *__mvgbe_phy_init(struct udevice *dev, @@ -740,11 +747,19 @@ static struct phy_device *__mvgbe_phy_init(struct eth_device *dev, #endif { struct phy_device *phydev; + int reg; /* Set phy address of the port */ miiphy_write(dev->name, MV_PHY_ADR_REQUEST, MV_PHY_ADR_REQUEST, phyid); + /* Set RGMII delay */ + miiphy_write(dev->name, phyid, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG); + miiphy_read(dev->name, phyid, MV88E1318_MAC_CTRL_REG, &reg); + reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL); + miiphy_write(dev->name, phyid, MV88E1318_MAC_CTRL_REG, reg); + miiphy_write(dev->name, phyid, MV88E1318_PGADR_REG, 0); + phydev = phy_connect(bus, phyid, dev, phy_interface); if (!phydev) { printf("phy_connect failed\n");

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[PATCH] Fix BMP display when the image stretches beyond border
by Vitaly Wool 09 Apr '22

09 Apr '22

When an image stretches beyond the display border, one still needs to seek to the next pixel line to display the visible part of that image correctly. Signed-off-by: Vitaly Wool <vitaly.wool(a)konsulko.com> --- drivers/video/video_bmp.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c index 4d2d961696..d0177daf58 100644 --- a/drivers/video/video_bmp.c +++ b/drivers/video/video_bmp.c @@ -238,7 +238,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, struct bmp_image *bmp = map_sysmem(bmp_image, 0); uchar *bmap; ushort padded_width; - unsigned long width, height, byte_width; + unsigned long width, vis_width, height, byte_width; unsigned long pwidth = priv->xsize; unsigned colours, bpix, bmp_bpix; enum video_format eformat; @@ -297,8 +297,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, video_splash_align_axis(&y, priv->ysize, height); } - if ((x + width) > pwidth) - width = pwidth - x; + vis_width = min(pwidth - x, width); if ((y + height) > priv->ysize) height = priv->ysize - y; @@ -318,7 +317,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, debug("compressed %d %d\n", compression, BMP_BI_RLE8); if (compression == BMP_BI_RLE8) { video_display_rle8_bitmap(dev, bmp, bpix, palette, fb, - x, y, width, height); + x, y, vis_width, height); break; } } @@ -330,7 +329,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, for (i = 0; i < height; ++i) { WATCHDOG_RESET(); - for (j = 0; j < width; j++) { + for (j = 0; j < vis_width; j++) { write_pix8(fb, bpix, eformat, palette, bmap); bmap++; fb += bpix / 8; @@ -343,7 +342,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, if (IS_ENABLED(CONFIG_BMP_16BPP)) { for (i = 0; i < height; ++i) { WATCHDOG_RESET(); - for (j = 0; j < width; j++) { + for (j = 0; j < vis_width; j++) { *fb++ = *bmap++; *fb++ = *bmap++; } @@ -355,7 +354,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, case 24: if (IS_ENABLED(CONFIG_BMP_24BPP)) { for (i = 0; i < height; ++i) { - for (j = 0; j < width; j++) { + for (j = 0; j < vis_width; j++) { if (bpix == 16) { /* 16bit 565RGB format */ *(u16 *)fb = ((bmap[2] >> 3) @@ -389,7 +388,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, case 32: if (IS_ENABLED(CONFIG_BMP_32BPP)) { for (i = 0; i < height; ++i) { - for (j = 0; j < width; j++) { + for (j = 0; j < vis_width; j++) { if (eformat == VIDEO_X2R10G10B10) { u32 pix; -- 2.30.2

2 1

[PATCH 1/2] mkimage: Document misc options
by Sean Anderson 09 Apr '22

09 Apr '22

Over the years, several options have not made it into the help message. Document them. Do the same for the man page. Signed-off-by: Sean Anderson <sean.anderson(a)seco.com> --- doc/mkimage.1 | 36 +++++++++++++++++++++++++++++++++++- tools/mkimage.c | 15 +++++++++++---- 2 files changed, 46 insertions(+), 5 deletions(-) diff --git a/doc/mkimage.1 b/doc/mkimage.1 index 287006279f..c92e133732 100644 --- a/doc/mkimage.1 +++ b/doc/mkimage.1 @@ -53,6 +53,10 @@ Parse image file as type. Pass \-h as the image to see the list of supported image type. Without this option image type is autodetected. +.TP +.BI "\-q" +Quiet. Don't print the image header on successful verification. + .P .B Create old legacy image: @@ -91,6 +95,11 @@ List the contents of an image. .BI "\-n [" "image name" "]" Set image name to 'image name'. +.TP +.BI "\-R [" "secondary image name" "]" +Some image types support a second image for additional data. For these types, +use \-R to specify this second image. + .TP .BI "\-d [" "image data file" "]" Use image data from 'image data file'. @@ -99,6 +108,15 @@ Use image data from 'image data file'. .BI "\-x" Set XIP (execute in place) flag. +.TP +.BI "\-s" +Create an image with no data. The header will be created, but the image itself +will not contain data (such as U-Boot or any specified kernel). + +.TP +.BI "\-v" +Verbose. Print file names as they are added to the image. + .P .B Create FIT image: @@ -126,6 +144,11 @@ in each image will be replaced with 'data-offset' and 'data-size' properties. A 'data-offset' of 0 indicates that it starts in the first (4-byte aligned) byte after the FIT. +.TP +.BI "\-B [" "alignment" "]" +The alignment, in hexadecimal, that external data will be aligned to. This +option only has an effect when \-E is specified. + .TP .BI "\-f [" "image tree source file" " | " "auto" "]" Image tree source file that describes the structure and contents of the @@ -161,6 +184,11 @@ the corresponding public key is written into this file for for run-time verification. Typically the file here is the device tree binary used by CONFIG_OF_CONTROL in U-Boot. +.TP +.BI "\-G [" "key_file" "]" +Specifies the private key file to use when signing. This option may be used +instead of \-k. + .TP .BI "\-o [" "signing algorithm" "]" Specifies the algorithm to be used for signing a FIT image. The default is @@ -173,11 +201,17 @@ a 'data-offset' property defining the offset from the end of the FIT, \-p will use 'data-position' as the absolute position from the base of the FIT. .TP -.BI "\-r +.BI "\-r" Specifies that keys used to sign the FIT are required. This means that they must be verified for the image to boot. Without this option, the verification will be optional (useful for testing but not for release). +.TP +.BI "\-N [" "engine" "]" +The openssl engine to use when signing and verifying the image. For a complete list of +available engines, refer to +.BR engine (1). + .TP .BI "\-t Update the timestamp in the FIT. diff --git a/tools/mkimage.c b/tools/mkimage.c index 74bd072832..c12d5932fc 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -84,7 +84,8 @@ static void usage(const char *msg) fprintf(stderr, "Error: %s\n", msg); fprintf(stderr, "Usage: %s [-T type] -l image\n" " -l ==> list image header information\n" - " -T ==> parse image file as 'type'\n", + " -T ==> parse image file as 'type'\n" + " -q ==> quiet\n", params.cmdname); fprintf(stderr, " %s [-x] -A arch -O os -T type -C comp -a addr -e ep -n name -d data_file[:data_file...] image\n" @@ -95,8 +96,11 @@ static void usage(const char *msg) " -a ==> set load address to 'addr' (hex)\n" " -e ==> set entry point to 'ep' (hex)\n" " -n ==> set image name to 'name'\n" + " -R ==> set second image name to 'name'\n" " -d ==> use image data from 'datafile'\n" - " -x ==> set XIP (execute in place)\n", + " -x ==> set XIP (execute in place)\n" + " -s ==> create an image with no data\n" + " -v ==> verbose\n", params.cmdname); fprintf(stderr, " %s [-D dtc_options] [-f fit-image.its|-f auto|-F] [-b <dtb> [-b <dtb>]] [-E] [-B size] [-i <ramdisk.cpio.gz>] fit-image\n" @@ -107,7 +111,9 @@ static void usage(const char *msg) " -f => input filename for FIT source\n" " -i => input filename for ramdisk file\n" " -E => place data outside of the FIT structure\n" - " -B => align size in hex for FIT structure and header\n"); + " -B => align size in hex for FIT structure and header\n" + " -b => append the device tree binary to the FIT\n" + " -t => update the timestamp in the FIT\n"); #ifdef CONFIG_FIT_SIGNATURE fprintf(stderr, "Signing / verified boot options: [-k keydir] [-K dtb] [ -c <comment>] [-p addr] [-r] [-N engine]\n" @@ -118,7 +124,8 @@ static void usage(const char *msg) " -F => re-sign existing FIT image\n" " -p => place external data at a static position\n" " -r => mark keys used as 'required' in dtb\n" - " -N => openssl engine to use for signing\n"); + " -N => openssl engine to use for signing\n" + " -o => algorithm to use for signing\n"); #else fprintf(stderr, "Signing / verified boot not supported (CONFIG_FIT_SIGNATURE undefined)\n"); -- 2.35.1.1320.gc452695387.dirty

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[PATCH] ns16550: Respect CONFIG_BAUDRATE < 0 in _debug_uart_init
by Joakim Tjernlund 08 Apr '22

08 Apr '22

CONFIG_BAUDRATE less than 0 means do not touch baudrate settings. Signed-off-by: Joakim Tjernlund <joakim.tjernlund(a)infinera.com> --- drivers/serial/ns16550.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 702109b23b..286d8aecca 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -333,15 +333,19 @@ static inline void _debug_uart_init(void) * feasible. The better fix is to move all users of this driver to * driver model. */ - baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK, - CONFIG_BAUDRATE); serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); serial_dout(&com_port->mcr, UART_MCRVAL); serial_dout(&com_port->fcr, UART_FCR_DEFVAL); - serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); - serial_dout(&com_port->dll, baud_divisor & 0xff); - serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); + if (CONFIG_BAUDRATE > 0) { + baud_divisor = ns16550_calc_divisor(com_port, + CONFIG_DEBUG_UART_CLOCK, + CONFIG_BAUDRATE); + + serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); + serial_dout(&com_port->dll, baud_divisor & 0xff); + serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); + } serial_dout(&com_port->lcr, UART_LCRVAL); } -- 2.34.1

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[PATCH] mkimage: fit: Simplify tmpfile name calculation
by Sean Anderson 08 Apr '22

08 Apr '22

snprintf will not overrun the buffer, and will return the number of characters which would have been printed (had the buffer been large enough). This allows us to create the tmpfile name and check for overflow in one pass. Signed-off-by: Sean Anderson <sean.anderson(a)seco.com> --- tools/fit_image.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tools/fit_image.c b/tools/fit_image.c index 1884a2eb0b..0d5a6a28f9 100644 --- a/tools/fit_image.c +++ b/tools/fit_image.c @@ -684,14 +684,13 @@ static int fit_handle_file(struct image_tool_params *params) debug ("FIT format handling\n"); /* call dtc to include binary properties into the tmp file */ - if (strlen (params->imagefile) + - strlen (MKIMAGE_TMPFILE_SUFFIX) + 1 > sizeof (tmpfile)) { + if (snprintf(tmpfile, sizeof(tmpfile), "%s%s", params->imagefile, + MKIMAGE_TMPFILE_SUFFIX) >= sizeof(tmpfile)) { fprintf (stderr, "%s: Image file name (%s) too long, " "can't create tmpfile.\n", params->imagefile, params->cmdname); return (EXIT_FAILURE); } - sprintf (tmpfile, "%s%s", params->imagefile, MKIMAGE_TMPFILE_SUFFIX); /* We either compile the source file, or use the existing FIT image */ if (params->auto_its) { -- 2.35.1.1320.gc452695387.dirty

2 2

[PATCH 01/10] net: Remove armada100_fec driver
by Tom Rini 08 Apr '22

08 Apr '22

This driver is not enabled by any board and not converted to DM_ETH. Remove. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- drivers/net/Makefile | 1 - drivers/net/armada100_fec.c | 739 ------------------------------------ drivers/net/armada100_fec.h | 208 ---------- 3 files changed, 948 deletions(-) delete mode 100644 drivers/net/armada100_fec.c delete mode 100644 drivers/net/armada100_fec.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a6d0c23f02d3..b57149b33994 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -6,7 +6,6 @@ obj-$(CONFIG_AG7XXX) += ag7xxx.o obj-$(CONFIG_ALTERA_TSE) += altera_tse.o -obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o obj-$(CONFIG_ASPEED_MDIO) += aspeed_mdio.o obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c deleted file mode 100644 index 5d4b90c6ba72..000000000000 --- a/drivers/net/armada100_fec.c +++ /dev/null @@ -1,739 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <contact(a)8051projects.net> - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Contributor: Mahavir Jain <mjain(a)marvell.com> - */ - -#include <common.h> -#include <log.h> -#include <net.h> -#include <malloc.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/types.h> -#include <asm/byteorder.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/mii.h> -#include <asm/io.h> -#include <asm/arch/armada100.h> -#include "armada100_fec.h" - -#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */ - -#ifdef DEBUG -static int eth_dump_regs(struct eth_device *dev) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - unsigned int i = 0; - - printf("\noffset: phy_adr, value: 0x%x\n", readl(&regs->phyadr)); - printf("offset: smi, value: 0x%x\n", readl(&regs->smi)); - for (i = 0x400; i <= 0x4e4; i += 4) - printf("offset: 0x%x, value: 0x%x\n", - i, readl(ARMD1_FEC_BASE + i)); - return 0; -} -#endif - -static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond) -{ - u32 timeout = PHY_WAIT_ITERATIONS; - u32 reg_val; - - while (--timeout) { - reg_val = readl(reg); - if (cond && (reg_val & flag)) - break; - else if (!cond && !(reg_val & flag)) - break; - udelay(PHY_WAIT_MICRO_SECONDS); - } - return !timeout; -} - -static int smi_reg_read(struct mii_dev *bus, int phy_addr, int devad, - int phy_reg) -{ - u16 value = 0; - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - u32 val; - - if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { - val = readl(&regs->phyadr); - value = val & 0x1f; - return value; - } - - /* check parameters */ - if (phy_addr > PHY_MASK) { - printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n", - __func__, phy_addr); - return -EINVAL; - } - if (phy_reg > PHY_MASK) { - printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n", - __func__, phy_reg); - return -EINVAL; - } - - /* wait for the SMI register to become available */ - if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) { - printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); - return -1; - } - - writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, &regs->smi); - - /* now wait for the data to be valid */ - if (armdfec_phy_timeout(&regs->smi, SMI_R_VALID, true)) { - val = readl(&regs->smi); - printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n", - __func__, val); - return -1; - } - val = readl(&regs->smi); - value = val & 0xffff; - - return value; -} - -static int smi_reg_write(struct mii_dev *bus, int phy_addr, int devad, - int phy_reg, u16 value) -{ - struct eth_device *dev = eth_get_dev_by_name(bus->name); - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - - if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { - clrsetbits_le32(&regs->phyadr, 0x1f, value & 0x1f); - return 0; - } - - /* check parameters */ - if (phy_addr > PHY_MASK) { - printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__); - return -EINVAL; - } - if (phy_reg > PHY_MASK) { - printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__); - return -EINVAL; - } - - /* wait for the SMI register to become available */ - if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) { - printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); - return -1; - } - - writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff), - &regs->smi); - return 0; -} - -/* - * Abort any transmit and receive operations and put DMA - * in idle state. AT and AR bits are cleared upon entering - * in IDLE state. So poll those bits to verify operation. - */ -static void abortdma(struct eth_device *dev) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - int delay; - int maxretries = 40; - u32 tmp; - - while (--maxretries) { - writel(SDMA_CMD_AR | SDMA_CMD_AT, &regs->sdma_cmd); - udelay(100); - - delay = 10; - while (--delay) { - tmp = readl(&regs->sdma_cmd); - if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT))) - break; - udelay(10); - } - if (delay) - break; - } - - if (!maxretries) - printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__); -} - -static inline u32 nibble_swapping_32_bit(u32 x) -{ - return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4); -} - -static inline u32 nibble_swapping_16_bit(u32 x) -{ - return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4); -} - -static inline u32 flip_4_bits(u32 x) -{ - return ((x & 0x01) << 3) | ((x & 0x002) << 1) - | ((x & 0x04) >> 1) | ((x & 0x008) >> 3); -} - -/* - * This function will calculate the hash function of the address. - * depends on the hash mode and hash size. - * Inputs - * mach - the 2 most significant bytes of the MAC address. - * macl - the 4 least significant bytes of the MAC address. - * Outputs - * return the calculated entry. - */ -static u32 hash_function(u32 mach, u32 macl) -{ - u32 hashresult; - u32 addrh; - u32 addrl; - u32 addr0; - u32 addr1; - u32 addr2; - u32 addr3; - u32 addrhswapped; - u32 addrlswapped; - - addrh = nibble_swapping_16_bit(mach); - addrl = nibble_swapping_32_bit(macl); - - addrhswapped = flip_4_bits(addrh & 0xf) - + ((flip_4_bits((addrh >> 4) & 0xf)) << 4) - + ((flip_4_bits((addrh >> 8) & 0xf)) << 8) - + ((flip_4_bits((addrh >> 12) & 0xf)) << 12); - - addrlswapped = flip_4_bits(addrl & 0xf) - + ((flip_4_bits((addrl >> 4) & 0xf)) << 4) - + ((flip_4_bits((addrl >> 8) & 0xf)) << 8) - + ((flip_4_bits((addrl >> 12) & 0xf)) << 12) - + ((flip_4_bits((addrl >> 16) & 0xf)) << 16) - + ((flip_4_bits((addrl >> 20) & 0xf)) << 20) - + ((flip_4_bits((addrl >> 24) & 0xf)) << 24) - + ((flip_4_bits((addrl >> 28) & 0xf)) << 28); - - addrh = addrhswapped; - addrl = addrlswapped; - - addr0 = (addrl >> 2) & 0x03f; - addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2); - addr2 = (addrl >> 15) & 0x1ff; - addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8); - - hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); - hashresult = hashresult & 0x07ff; - return hashresult; -} - -/* - * This function will add an entry to the address table. - * depends on the hash mode and hash size that was initialized. - * Inputs - * mach - the 2 most significant bytes of the MAC address. - * macl - the 4 least significant bytes of the MAC address. - * skip - if 1, skip this address. - * rd - the RD field in the address table. - * Outputs - * address table entry is added. - * 0 if success. - * -ENOSPC if table full - */ -static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach, - u32 macl, u32 rd, u32 skip, int del) -{ - struct addr_table_entry_t *entry, *start; - u32 newhi; - u32 newlo; - u32 i; - - newlo = (((mach >> 4) & 0xf) << 15) - | (((mach >> 0) & 0xf) << 11) - | (((mach >> 12) & 0xf) << 7) - | (((mach >> 8) & 0xf) << 3) - | (((macl >> 20) & 0x1) << 31) - | (((macl >> 16) & 0xf) << 27) - | (((macl >> 28) & 0xf) << 23) - | (((macl >> 24) & 0xf) << 19) - | (skip << HTESKIP) | (rd << HTERDBIT) - | HTEVALID; - - newhi = (((macl >> 4) & 0xf) << 15) - | (((macl >> 0) & 0xf) << 11) - | (((macl >> 12) & 0xf) << 7) - | (((macl >> 8) & 0xf) << 3) - | (((macl >> 21) & 0x7) << 0); - - /* - * Pick the appropriate table, start scanning for free/reusable - * entries at the index obtained by hashing the specified MAC address - */ - start = (struct addr_table_entry_t *)(darmdfec->htpr); - entry = start + hash_function(mach, macl); - for (i = 0; i < HOP_NUMBER; i++) { - if (!(entry->lo & HTEVALID)) { - break; - } else { - /* if same address put in same position */ - if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8)) - && (entry->hi == newhi)) - break; - } - if (entry == start + 0x7ff) - entry = start; - else - entry++; - } - - if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) && - (entry->hi != newhi) && del) - return 0; - - if (i == HOP_NUMBER) { - if (!del) { - printf("ARMD100 FEC: (%s) table section is full\n", - __func__); - return -ENOSPC; - } else { - return 0; - } - } - - /* - * Update the selected entry - */ - if (del) { - entry->hi = 0; - entry->lo = 0; - } else { - entry->hi = newhi; - entry->lo = newlo; - } - - return 0; -} - -/* - * Create an addressTable entry from MAC address info - * found in the specifed net_device struct - * - * Input : pointer to ethernet interface network device structure - * Output : N/A - */ -static void update_hash_table_mac_address(struct armdfec_device *darmdfec, - u8 *oaddr, u8 *addr) -{ - u32 mach; - u32 macl; - - /* Delete old entry */ - if (oaddr) { - mach = (oaddr[0] << 8) | oaddr[1]; - macl = (oaddr[2] << 24) | (oaddr[3] << 16) | - (oaddr[4] << 8) | oaddr[5]; - add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE); - } - - /* Add new entry */ - mach = (addr[0] << 8) | addr[1]; - macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; - add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD); -} - -/* Address Table Initialization */ -static void init_hashtable(struct eth_device *dev) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE); - writel((u32)darmdfec->htpr, &regs->htpr); -} - -/* - * This detects PHY chip from address 0-31 by reading PHY status - * registers. PHY chip can be connected at any of this address. - */ -static int ethernet_phy_detect(struct eth_device *dev) -{ - u32 val; - u16 tmp, mii_status; - u8 addr; - - for (addr = 0; addr < 32; addr++) { - if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0) - /* try next phy */ - continue; - - /* invalid MII status. More validation required here... */ - if (mii_status == 0 || mii_status == 0xffff) - /* try next phy */ - continue; - - if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0) - /* try next phy */ - continue; - - val = tmp << 16; - if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0) - /* try next phy */ - continue; - - val |= tmp; - - if ((val & 0xfffffff0) != 0) - return addr; - } - return -1; -} - -static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec) -{ - struct rx_desc *p_rx_desc; - int i; - - /* initialize the Rx descriptors ring */ - p_rx_desc = darmdfec->p_rxdesc; - for (i = 0; i < RINGSZ; i++) { - p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; - p_rx_desc->buf_size = PKTSIZE_ALIGN; - p_rx_desc->byte_cnt = 0; - p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN; - if (i == (RINGSZ - 1)) { - p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc; - } else { - p_rx_desc->nxtdesc_p = (struct rx_desc *) - ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE); - p_rx_desc = p_rx_desc->nxtdesc_p; - } - } - darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc; -} - -static int armdfec_init(struct eth_device *dev, struct bd_info *bd) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - int phy_adr; - u32 temp; - - armdfec_init_rx_desc_ring(darmdfec); - - /* Disable interrupts */ - writel(0, &regs->im); - writel(0, &regs->ic); - /* Write to ICR to clear interrupts. */ - writel(0, &regs->iwc); - - /* - * Abort any transmit and receive operations and put DMA - * in idle state. - */ - abortdma(dev); - - /* Initialize address hash table */ - init_hashtable(dev); - - /* SDMA configuration */ - writel(SDCR_BSZ8 | /* Burst size = 32 bytes */ - SDCR_RIFB | /* Rx interrupt on frame */ - SDCR_BLMT | /* Little endian transmit */ - SDCR_BLMR | /* Little endian receive */ - SDCR_RC_MAX_RETRANS, /* Max retransmit count */ - &regs->sdma_conf); - /* Port Configuration */ - writel(PCR_HS, &regs->pconf); /* Hash size is 1/2kb */ - - /* Set extended port configuration */ - writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */ - PCXR_DSCP_EN | /* Enable DSCP in IP */ - PCXR_MFL_1536 | /* Set MTU = 1536 */ - PCXR_FLP | /* do not force link pass */ - PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */ - &regs->pconf_ext); - - update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr); - - /* Update TX and RX queue descriptor register */ - temp = (u32)&regs->txcdp[TXQ]; - writel((u32)darmdfec->p_txdesc, temp); - temp = (u32)&regs->rxfdp[RXQ]; - writel((u32)darmdfec->p_rxdesc, temp); - temp = (u32)&regs->rxcdp[RXQ]; - writel((u32)darmdfec->p_rxdesc_curr, temp); - - /* Enable Interrupts */ - writel(ALL_INTS, &regs->im); - - /* Enable Ethernet Port */ - setbits_le32(&regs->pconf, PCR_EN); - - /* Enable RX DMA engine */ - setbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD); - -#ifdef DEBUG - eth_dump_regs(dev); -#endif - -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) - -#if defined(CONFIG_PHY_BASE_ADR) - miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR); -#else - /* Search phy address from range 0-31 */ - phy_adr = ethernet_phy_detect(dev); - if (phy_adr < 0) { - printf("ARMD100 FEC: PHY not detected at address range 0-31\n"); - return -1; - } else { - debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr); - miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr); - } -#endif - -#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) - /* Wait up to 5s for the link status */ - for (i = 0; i < 5; i++) { - u16 phy_adr; - - miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr); - /* Return if we get link up */ - if (miiphy_link(dev->name, phy_adr)) - return 0; - udelay(1000000); - } - - printf("ARMD100 FEC: No link on %s\n", dev->name); - return -1; -#endif -#endif - return 0; -} - -static void armdfec_halt(struct eth_device *dev) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - - /* Stop RX DMA */ - clrbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD); - - /* - * Abort any transmit and receive operations and put DMA - * in idle state. - */ - abortdma(dev); - - /* Disable interrupts */ - writel(0, &regs->im); - writel(0, &regs->ic); - writel(0, &regs->iwc); - - /* Disable Port */ - clrbits_le32(&regs->pconf, PCR_EN); -} - -static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct armdfec_reg *regs = darmdfec->regs; - struct tx_desc *p_txdesc = darmdfec->p_txdesc; - void *p = (void *)dataptr; - int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS; - u32 cmd_sts, temp; - - /* Copy buffer if it's misaligned */ - if ((u32)dataptr & 0x07) { - if (datasize > PKTSIZE_ALIGN) { - printf("ARMD100 FEC: Non-aligned data too large (%d)\n", - datasize); - return -1; - } - memcpy(darmdfec->p_aligned_txbuf, p, datasize); - p = darmdfec->p_aligned_txbuf; - } - - p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC; - p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC; - p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA; - p_txdesc->cmd_sts |= TX_EN_INT; - p_txdesc->buf_ptr = p; - p_txdesc->byte_cnt = datasize; - - /* Apply send command using high priority TX queue */ - temp = (u32)&regs->txcdp[TXQ]; - writel((u32)p_txdesc, temp); - writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, &regs->sdma_cmd); - - /* - * wait for packet xmit completion - */ - cmd_sts = readl(&p_txdesc->cmd_sts); - while (cmd_sts & BUF_OWNED_BY_DMA) { - /* return fail if error is detected */ - if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) == - (TX_ERROR | TX_LAST_DESC)) { - printf("ARMD100 FEC: (%s) in xmit packet\n", __func__); - return -1; - } - cmd_sts = readl(&p_txdesc->cmd_sts); - if (!(retry--)) { - printf("ARMD100 FEC: (%s) xmit packet timeout!\n", - __func__); - return -1; - } - } - - return 0; -} - -static int armdfec_recv(struct eth_device *dev) -{ - struct armdfec_device *darmdfec = to_darmdfec(dev); - struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr; - u32 cmd_sts; - u32 timeout = 0; - u32 temp; - - /* wait untill rx packet available or timeout */ - do { - if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) { - timeout++; - } else { - debug("ARMD100 FEC: %s time out...\n", __func__); - return -1; - } - } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA); - - if (p_rxdesc_curr->byte_cnt != 0) { - debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x" - "(cmd_sts= %08x)\n", __func__, - (u32)p_rxdesc_curr->byte_cnt, - (u32)p_rxdesc_curr->buf_ptr, - (u32)p_rxdesc_curr->cmd_sts); - } - - /* - * In case received a packet without first/last bits on - * OR the error summary bit is on, - * the packets needs to be dropeed. - */ - cmd_sts = readl(&p_rxdesc_curr->cmd_sts); - - if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != - (RX_FIRST_DESC | RX_LAST_DESC)) { - printf("ARMD100 FEC: (%s) Dropping packet spread on" - " multiple descriptors\n", __func__); - } else if (cmd_sts & RX_ERROR) { - printf("ARMD100 FEC: (%s) Dropping packet with errors\n", - __func__); - } else { - /* !!! call higher layer processing */ - debug("ARMD100 FEC: (%s) Sending Received packet to" - " upper layer (net_process_received_packet)\n", __func__); - - /* - * let the upper layer handle the packet, subtract offset - * as two dummy bytes are added in received buffer see - * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit. - */ - net_process_received_packet( - p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET, - (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET)); - } - /* - * free these descriptors and point next in the ring - */ - p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; - p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; - p_rxdesc_curr->byte_cnt = 0; - - temp = (u32)&darmdfec->p_rxdesc_curr; - writel((u32)p_rxdesc_curr->nxtdesc_p, temp); - - return 0; -} - -int armada100_fec_register(unsigned long base_addr) -{ - struct armdfec_device *darmdfec; - struct eth_device *dev; - - darmdfec = malloc(sizeof(struct armdfec_device)); - if (!darmdfec) - goto error; - - memset(darmdfec, 0, sizeof(struct armdfec_device)); - - darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE); - if (!darmdfec->htpr) - goto error1; - - darmdfec->p_rxdesc = memalign(PKTALIGN, - ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1); - - if (!darmdfec->p_rxdesc) - goto error1; - - darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1); - if (!darmdfec->p_rxbuf) - goto error1; - - darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); - if (!darmdfec->p_aligned_txbuf) - goto error1; - - darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1); - if (!darmdfec->p_txdesc) - goto error1; - - dev = &darmdfec->dev; - /* Assign ARMADA100 Fast Ethernet Controller Base Address */ - darmdfec->regs = (void *)base_addr; - - /* must be less than sizeof(dev->name) */ - strcpy(dev->name, "armd-fec0"); - - dev->init = armdfec_init; - dev->halt = armdfec_halt; - dev->send = armdfec_send; - dev->recv = armdfec_recv; - - eth_register(dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = smi_reg_read; - mdiodev->write = smi_reg_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - return 0; - -error1: - free(darmdfec->p_aligned_txbuf); - free(darmdfec->p_rxbuf); - free(darmdfec->p_rxdesc); - free(darmdfec->htpr); -error: - free(darmdfec); - printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__); - return -1; -} diff --git a/drivers/net/armada100_fec.h b/drivers/net/armada100_fec.h deleted file mode 100644 index e6f286cfd387..000000000000 --- a/drivers/net/armada100_fec.h +++ /dev/null @@ -1,208 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <contact(a)8051projects.net> - * - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Contributor: Mahavir Jain <mjain(a)marvell.com> - */ - -#ifndef __ARMADA100_FEC_H__ -#define __ARMADA100_FEC_H__ - -#define PORT_NUM 0x0 - -/* RX & TX descriptor command */ -#define BUF_OWNED_BY_DMA (1<<31) - -/* RX descriptor status */ -#define RX_EN_INT (1<<23) -#define RX_FIRST_DESC (1<<17) -#define RX_LAST_DESC (1<<16) -#define RX_ERROR (1<<15) - -/* TX descriptor command */ -#define TX_EN_INT (1<<23) -#define TX_GEN_CRC (1<<22) -#define TX_ZERO_PADDING (1<<18) -#define TX_FIRST_DESC (1<<17) -#define TX_LAST_DESC (1<<16) -#define TX_ERROR (1<<15) - -/* smi register */ -#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */ -#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */ -#define SMI_OP_W (0<<26) /* Write operation */ -#define SMI_OP_R (1<<26) /* Read operation */ - -#define HASH_ADD 0 -#define HASH_DELETE 1 -#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ -#define HOP_NUMBER 12 - -#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ -#define PHY_WAIT_MICRO_SECONDS 10 - -#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ -#define ETH_EXTRA_HEADER (6+6+2+4) - /* dest+src addr+protocol id+crc */ -#define MAX_PKT_SIZE 1536 - - -/* Bit definitions of the SDMA Config Reg */ -#define SDCR_BSZ_OFF 12 -#define SDCR_BSZ8 (3<<SDCR_BSZ_OFF) -#define SDCR_BSZ4 (2<<SDCR_BSZ_OFF) -#define SDCR_BSZ2 (1<<SDCR_BSZ_OFF) -#define SDCR_BSZ1 (0<<SDCR_BSZ_OFF) -#define SDCR_BLMR (1<<6) -#define SDCR_BLMT (1<<7) -#define SDCR_RIFB (1<<9) -#define SDCR_RC_OFF 2 -#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) - -/* SDMA_CMD */ -#define SDMA_CMD_AT (1<<31) -#define SDMA_CMD_TXDL (1<<24) -#define SDMA_CMD_TXDH (1<<23) -#define SDMA_CMD_AR (1<<15) -#define SDMA_CMD_ERD (1<<7) - - -/* Bit definitions of the Port Config Reg */ -#define PCR_HS (1<<12) -#define PCR_EN (1<<7) -#define PCR_PM (1<<0) - -/* Bit definitions of the Port Config Extend Reg */ -#define PCXR_2BSM (1<<28) -#define PCXR_DSCP_EN (1<<21) -#define PCXR_MFL_1518 (0<<14) -#define PCXR_MFL_1536 (1<<14) -#define PCXR_MFL_2048 (2<<14) -#define PCXR_MFL_64K (3<<14) -#define PCXR_FLP (1<<11) -#define PCXR_PRIO_TX_OFF 3 -#define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF) - -/* - * * Bit definitions of the Interrupt Cause Reg - * * and Interrupt MASK Reg is the same - * */ -#define ICR_RXBUF (1<<0) -#define ICR_TXBUF_H (1<<2) -#define ICR_TXBUF_L (1<<3) -#define ICR_TXEND_H (1<<6) -#define ICR_TXEND_L (1<<7) -#define ICR_RXERR (1<<8) -#define ICR_TXERR_H (1<<10) -#define ICR_TXERR_L (1<<11) -#define ICR_TX_UDR (1<<13) -#define ICR_MII_CH (1<<28) - -#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ - ICR_TXERR_H | ICR_TXERR_L |\ - ICR_TXEND_H | ICR_TXEND_L |\ - ICR_RXBUF | ICR_RXERR | ICR_MII_CH) - -#define PHY_MASK 0x0000001f - -#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev) -/* Size of a Tx/Rx descriptor used in chain list data structure */ -#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \ - (((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN) - -#define RX_BUF_OFFSET 0x2 -#define RXQ 0x0 /* RX Queue 0 */ -#define TXQ 0x1 /* TX Queue 1 */ - -struct addr_table_entry_t { - u32 lo; - u32 hi; -}; - -/* Bit fields of a Hash Table Entry */ -enum hash_table_entry { - HTEVALID = 1, - HTESKIP = 2, - HTERD = 4, - HTERDBIT = 2 -}; - -struct tx_desc { - u32 cmd_sts; /* Command/status field */ - u16 reserved; - u16 byte_cnt; /* buffer byte count */ - u8 *buf_ptr; /* pointer to buffer for this descriptor */ - struct tx_desc *nextdesc_p; /* Pointer to next descriptor */ -}; - -struct rx_desc { - u32 cmd_sts; /* Descriptor command status */ - u16 byte_cnt; /* Descriptor buffer byte count */ - u16 buf_size; /* Buffer size */ - u8 *buf_ptr; /* Descriptor buffer pointer */ - struct rx_desc *nxtdesc_p; /* Next descriptor pointer */ -}; - -/* - * Armada100 Fast Ethernet controller Registers - * Refer Datasheet Appendix A.22 - */ -struct armdfec_reg { - u32 phyadr; /* PHY Address */ - u32 pad1[3]; - u32 smi; /* SMI */ - u32 pad2[0xFB]; - u32 pconf; /* Port configuration */ - u32 pad3; - u32 pconf_ext; /* Port configuration extend */ - u32 pad4; - u32 pcmd; /* Port Command */ - u32 pad5; - u32 pstatus; /* Port Status */ - u32 pad6; - u32 spar; /* Serial Parameters */ - u32 pad7; - u32 htpr; /* Hash table pointer */ - u32 pad8; - u32 fcsal; /* Flow control source address low */ - u32 pad9; - u32 fcsah; /* Flow control source address high */ - u32 pad10; - u32 sdma_conf; /* SDMA configuration */ - u32 pad11; - u32 sdma_cmd; /* SDMA command */ - u32 pad12; - u32 ic; /* Interrupt cause */ - u32 iwc; /* Interrupt write to clear */ - u32 im; /* Interrupt mask */ - u32 pad13; - u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code - Point to Priority 0 Low */ - u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */ - u32 pad14[3]; - struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor - Pointer */ - u32 pad15[4]; - struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor - Pointer */ - u32 pad16[0x0C]; - struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor - Pointer */ -}; - -struct armdfec_device { - struct eth_device dev; - struct armdfec_reg *regs; - struct tx_desc *p_txdesc; - struct rx_desc *p_rxdesc; - struct rx_desc *p_rxdesc_curr; - u8 *p_rxbuf; - u8 *p_aligned_txbuf; - u8 *htpr; /* hash pointer */ -}; - -#endif /* __ARMADA100_FEC_H__ */ -- 2.25.1

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[PATCH v2 0/2] env: setenv add resolve value option
by Artem Lapkin 08 Apr '22

08 Apr '22

Add possibility setup env variable with additional resolving vars inside value. Usage examples: => setenv a hello; setenv b world; setenv c '${a} ${b}' => setenv -r d '${c}! ${a}...' => printenv d d=hello world! hello... /* internal usage example */ env_resolve("d", "${c}! ${a}..."); /* d="hello world! hello..." */ Artem Lapkin (2): env: setenv add resolve value option test: env: deep resolve value testing --- V2 changes: _ fix comments style _ add comment include/exports.h _ remake strcpy to strdup _ env_resolve minimize _ test added: test/py/tests/test_env.py: test_env_resovle --- cmd/nvedit.c | 43 ++++++++++++++++++++++++++++++++++++++- include/_exports.h | 1 + include/env.h | 11 ++++++++++ include/exports.h | 2 ++ test/py/tests/test_env.py | 24 ++++++++++++++++++++++ 5 files changed, 80 insertions(+), 1 deletion(-) -- 2.25.1

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