October 2022 - U-Boot

[PATCH 2/2] mach-snapdragon/mach-ipq40xx: fix, merge and refactoring
by Andrey Volkov 25 Oct '22

25 Oct '22

ipq40xx/snapdragon: Merge two, more than 90% overlapping Qualcomm's Snapdrgon based arches, into one: "mach-snapdragon". Signed-off-by: Andrey VOLKOV <andrey(a)volkov.fr> --- arch/arm/Kconfig | 19 --- arch/arm/Makefile | 1 arch/arm/mach-ipq40xx/Kconfig | 15 -- arch/arm/mach-ipq40xx/Makefile | 9 - arch/arm/mach-ipq40xx/clock-ipq4019.c | 88 ------------- arch/arm/mach-ipq40xx/include/mach/gpio.h | 10 -- arch/arm/mach-ipq40xx/pinctrl-ipq4019.c | 54 -------- arch/arm/mach-ipq40xx/pinctrl-snapdragon.c | 166 ------------------------- arch/arm/mach-ipq40xx/pinctrl-snapdragon.h | 30 ----- arch/arm/mach-snapdragon/Kconfig | 47 ++++++- arch/arm/mach-snapdragon/Makefile | 5 + arch/arm/mach-snapdragon/clock-ipq4019.c | 88 +++++++++++++ arch/arm/mach-snapdragon/pinctrl-ipq4019.c | 54 ++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 36 +++-- arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 drivers/phy/qcom/Kconfig | 2 drivers/reset/Kconfig | 2 drivers/reset/reset-qcom.c | 2 drivers/smem/Kconfig | 2 drivers/spi/Kconfig | 2 20 files changed, 220 insertions(+), 413 deletions(-) delete mode 100644 arch/arm/mach-ipq40xx/Kconfig delete mode 100644 arch/arm/mach-ipq40xx/Makefile delete mode 100644 arch/arm/mach-ipq40xx/clock-ipq4019.c delete mode 100644 arch/arm/mach-ipq40xx/include/mach/gpio.h delete mode 100644 arch/arm/mach-ipq40xx/pinctrl-ipq4019.c delete mode 100644 arch/arm/mach-ipq40xx/pinctrl-snapdragon.c delete mode 100644 arch/arm/mach-ipq40xx/pinctrl-snapdragon.h create mode 100644 arch/arm/mach-snapdragon/clock-ipq4019.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-ipq4019.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a25b7f6d99..a495dfe813 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -803,21 +803,6 @@ config ARCH_INTEGRATOR select PL01X_SERIAL imply CMD_DM -config ARCH_IPQ40XX - bool "Qualcomm IPQ40xx SoCs" - select CPU_V7A - select DM - select DM_GPIO - select DM_SERIAL - select DM_RESET - select GPIO_EXTRA_HEADER - select MSM_SMEM - select PINCTRL - select CLK - select SMEM - select OF_CONTROL - imply CMD_DM - config ARCH_KEYSTONE bool "TI Keystone" select CMD_POWEROFF @@ -1098,6 +1083,7 @@ config ARCH_RMOBILE config ARCH_SNAPDRAGON bool "Qualcomm Snapdragon SoCs" + select CLK select DM select DM_GPIO select DM_SERIAL @@ -1105,6 +1091,7 @@ config ARCH_SNAPDRAGON select MSM_SMEM select OF_CONTROL select OF_SEPARATE + select PINCTRL select SMEM select SPMI imply CMD_DM @@ -2225,8 +2212,6 @@ source "arch/arm/mach-highbank/Kconfig" source "arch/arm/mach-integrator/Kconfig" -source "arch/arm/mach-ipq40xx/Kconfig" - source "arch/arm/mach-k3/Kconfig" source "arch/arm/mach-keystone/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index ac602aed9c..ceee6a02d0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -61,7 +61,6 @@ machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_EXYNOS) += exynos machine-$(CONFIG_ARCH_GXP) += hpe machine-$(CONFIG_ARCH_HIGHBANK) += highbank -machine-$(CONFIG_ARCH_IPQ40XX) += ipq40xx machine-$(CONFIG_ARCH_K3) += k3 machine-$(CONFIG_ARCH_KEYSTONE) += keystone machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood diff --git a/arch/arm/mach-ipq40xx/Kconfig b/arch/arm/mach-ipq40xx/Kconfig deleted file mode 100644 index 4eef80e935..0000000000 --- a/arch/arm/mach-ipq40xx/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if ARCH_IPQ40XX - -config SYS_SOC - default "ipq40xx" - -config SYS_MALLOC_F_LEN - default 0x2000 - -config SYS_TEXT_BASE - default 0x87300000 - -config NR_DRAM_BANKS - default 1 - -endif diff --git a/arch/arm/mach-ipq40xx/Makefile b/arch/arm/mach-ipq40xx/Makefile deleted file mode 100644 index 08a65b8854..0000000000 --- a/arch/arm/mach-ipq40xx/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2019 Sartura Ltd. -# -# Author: Robert Marko <robert.marko(a)sartura.hr> - -obj-y += clock-ipq4019.o -obj-y += pinctrl-snapdragon.o -obj-y += pinctrl-ipq4019.o diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c deleted file mode 100644 index c1d5c4ecdd..0000000000 --- a/arch/arm/mach-ipq40xx/clock-ipq4019.c +++ /dev/null @@ -1,88 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Clock drivers for Qualcomm IPQ40xx - * - * Copyright (c) 2020 Sartura Ltd. - * - * Author: Robert Marko <robert.marko(a)sartura.hr> - * - */ - -#include <clk-uclass.h> -#include <common.h> -#include <dm.h> -#include <errno.h> - -#include <dt-bindings/clock/qcom,ipq4019-gcc.h> - -struct msm_clk_priv { - phys_addr_t base; -}; - -ulong msm_set_rate(struct clk *clk, ulong rate) -{ - switch (clk->id) { - case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ - /* This clock is already initialized by SBL1 */ - return 0; - default: - return -EINVAL; - } -} - -static int msm_clk_probe(struct udevice *dev) -{ - struct msm_clk_priv *priv = dev_get_priv(dev); - - priv->base = dev_read_addr(dev); - if (priv->base == FDT_ADDR_T_NONE) - return -EINVAL; - - return 0; -} - -static ulong msm_clk_set_rate(struct clk *clk, ulong rate) -{ - return msm_set_rate(clk, rate); -} - -static int msm_enable(struct clk *clk) -{ - switch (clk->id) { - case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/ - /* This clock is already initialized by SBL1 */ - return 0; - case GCC_PRNG_AHB_CLK: /*PRNG*/ - /* This clock is already initialized by SBL1 */ - return 0; - case GCC_USB3_MASTER_CLK: - case GCC_USB3_SLEEP_CLK: - case GCC_USB3_MOCK_UTMI_CLK: - case GCC_USB2_MASTER_CLK: - case GCC_USB2_SLEEP_CLK: - case GCC_USB2_MOCK_UTMI_CLK: - /* These clocks is already initialized by SBL1 */ - return 0; - default: - return -EINVAL; - } -} - -static struct clk_ops msm_clk_ops = { - .set_rate = msm_clk_set_rate, - .enable = msm_enable, -}; - -static const struct udevice_id msm_clk_ids[] = { - { .compatible = "qcom,gcc-ipq4019" }, - { } -}; - -U_BOOT_DRIVER(clk_msm) = { - .name = "clk_msm", - .id = UCLASS_CLK, - .of_match = msm_clk_ids, - .ops = &msm_clk_ops, - .priv_auto = sizeof(struct msm_clk_priv), - .probe = msm_clk_probe, -}; diff --git a/arch/arm/mach-ipq40xx/include/mach/gpio.h b/arch/arm/mach-ipq40xx/include/mach/gpio.h deleted file mode 100644 index a45747c0fe..0000000000 --- a/arch/arm/mach-ipq40xx/include/mach/gpio.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Empty gpio.h - * - * This file must stay as arch/arm/include/asm/gpio.h requires it. - * - * Copyright (c) 2019 Sartura Ltd. - * - * Author: Robert Marko <robert.marko(a)sartura.hr> - */ diff --git a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c b/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c deleted file mode 100644 index 3e365f8cc8..0000000000 --- a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c +++ /dev/null @@ -1,54 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Qualcomm IPQ40xx pinctrl - * - * Copyright (c) 2019 Sartura Ltd. - * - * Author: Robert Marko <robert.marko(a)sartura.hr> - */ - -#include "pinctrl-snapdragon.h" -#include <common.h> - -#define MAX_PIN_NAME_LEN 32 -static char pin_name[MAX_PIN_NAME_LEN]; - -static const struct pinctrl_function msm_pinctrl_functions[] = { - {"gpio", 0}, - {"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */ - {"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */ - {"blsp_uart1", 1}, - {"blsp_spi0_0", 1}, /* Only for GPIO:12,13,14,15 */ - {"blsp_spi0_1", 2}, /* Only for GPIO:54,55,56,57 */ - {"blsp_spi1", 2}, - {"mdio_0", 1}, /* Only for GPIO6 */ - {"mdio_1", 2}, /* Only for GPIO53 */ - {"mdc_0", 1}, /* Only for GPIO7 */ - {"mdc_1", 2}, /* Only for GPIO52 */ -}; - -static const char *ipq4019_get_function_name(struct udevice *dev, - unsigned int selector) -{ - return msm_pinctrl_functions[selector].name; -} - -static const char *ipq4019_get_pin_name(struct udevice *dev, - unsigned int selector) -{ - snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); - return pin_name; -} - -static unsigned int ipq4019_get_function_mux(unsigned int selector) -{ - return msm_pinctrl_functions[selector].val; -} - -struct msm_pinctrl_data ipq4019_data = { - .pin_count = 100, - .functions_count = ARRAY_SIZE(msm_pinctrl_functions), - .get_function_name = ipq4019_get_function_name, - .get_function_mux = ipq4019_get_function_mux, - .get_pin_name = ipq4019_get_pin_name, -}; diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c deleted file mode 100644 index 036fec93d7..0000000000 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * TLMM driver for Qualcomm IPQ40xx - * - * (C) Copyright 2018 Ramon Fried <ramon.fried(a)gmail.com> - * - * Copyright (c) 2020 Sartura Ltd. - * - * Author: Robert Marko <robert.marko(a)sartura.hr> - * - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <asm/io.h> -#include <dm/device_compat.h> -#include <dm/lists.h> -#include <dm/pinctrl.h> -#include <linux/bitops.h> -#include "pinctrl-snapdragon.h" - -struct msm_pinctrl_priv { - phys_addr_t base; - struct msm_pinctrl_data *data; -}; - -#define GPIO_CONFIG_OFFSET(x) ((x) * 0x1000) -#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) -#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) -#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_DISABLE BIT(9) - -static const struct pinconf_param msm_conf_params[] = { - { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, - { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, - { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 2 }, -}; - -static int msm_get_functions_count(struct udevice *dev) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - return priv->data->functions_count; -} - -static int msm_get_pins_count(struct udevice *dev) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - return priv->data->pin_count; -} - -static const char *msm_get_function_name(struct udevice *dev, - unsigned int selector) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - return priv->data->get_function_name(dev, selector); -} - -static int msm_pinctrl_probe(struct udevice *dev) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - priv->base = devfdt_get_addr(dev); - priv->data = (struct msm_pinctrl_data *)dev->driver_data; - - return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0; -} - -static const char *msm_get_pin_name(struct udevice *dev, unsigned int selector) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - return priv->data->get_pin_name(dev, selector); -} - -static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, - unsigned int func_selector) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), - TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, - priv->data->get_function_mux(func_selector) << 2); - return 0; -} - -static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, - unsigned int param, unsigned int argument) -{ - struct msm_pinctrl_priv *priv = dev_get_priv(dev); - - switch (param) { - case PIN_CONFIG_DRIVE_STRENGTH: - clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), - TLMM_DRV_STRENGTH_MASK, argument << 6); - break; - case PIN_CONFIG_BIAS_DISABLE: - clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), - TLMM_GPIO_PULL_MASK); - break; - case PIN_CONFIG_BIAS_PULL_UP: - clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), - TLMM_GPIO_PULL_MASK, argument); - break; - default: - return 0; - } - - return 0; -} - -static int msm_pinctrl_bind(struct udevice *dev) -{ - ofnode node = dev_ofnode(dev); - const char *name; - int ret; - - ofnode_get_property(node, "gpio-controller", &ret); - if (ret < 0) - return 0; - - /* Get the name of gpio node */ - name = ofnode_get_name(node); - if (!name) - return -EINVAL; - - /* Bind gpio node */ - ret = device_bind_driver_to_node(dev, "gpio_msm", - name, node, NULL); - if (ret) - return ret; - - dev_dbg(dev, "bind %s\n", name); - - return 0; -} - -static struct pinctrl_ops msm_pinctrl_ops = { - .get_pins_count = msm_get_pins_count, - .get_pin_name = msm_get_pin_name, - .set_state = pinctrl_generic_set_state, - .pinmux_set = msm_pinmux_set, - .pinconf_num_params = ARRAY_SIZE(msm_conf_params), - .pinconf_params = msm_conf_params, - .pinconf_set = msm_pinconf_set, - .get_functions_count = msm_get_functions_count, - .get_function_name = msm_get_function_name, -}; - -static const struct udevice_id msm_pinctrl_ids[] = { - { .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data }, - { } -}; - -U_BOOT_DRIVER(pinctrl_snapdraon) = { - .name = "pinctrl_msm", - .id = UCLASS_PINCTRL, - .of_match = msm_pinctrl_ids, - .priv_auto = sizeof(struct msm_pinctrl_priv), - .ops = &msm_pinctrl_ops, - .probe = msm_pinctrl_probe, - .bind = msm_pinctrl_bind, -}; diff --git a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h b/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h deleted file mode 100644 index 2341a71349..0000000000 --- a/arch/arm/mach-ipq40xx/pinctrl-snapdragon.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Qualcomm Pin control - * - * (C) Copyright 2018 Ramon Fried <ramon.fried(a)gmail.com> - * - */ -#ifndef _PINCTRL_SNAPDRAGON_H -#define _PINCTRL_SNAPDRAGON_H - -#include <common.h> - -struct msm_pinctrl_data { - int pin_count; - int functions_count; - const char *(*get_function_name)(struct udevice *dev, - unsigned int selector); - unsigned int (*get_function_mux)(unsigned int selector); - const char *(*get_pin_name)(struct udevice *dev, - unsigned int selector); -}; - -struct pinctrl_function { - const char *name; - int val; -}; - -extern struct msm_pinctrl_data ipq4019_data; - -#endif diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 83dd2c07a1..6600120248 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -9,28 +9,61 @@ config SYS_MALLOC_F_LEN config SPL_SYS_MALLOC_F_LEN default 0x2000 -config APQ8016 +config COMMON_SNAPDRAGON + bool + default n + +config SNAPDRAGON_ARMV8 bool select ARM64 + select COMMON_SNAPDRAGON + default n + +config SNAPDRAGON_ARMV7A + bool + select CPU_V7A + default n + +config APQ8016 + bool + select SNAPDRAGON_ARMV8 default n config APQ8096 bool - select ARM64 + select SNAPDRAGON_ARMV8 default n config SDM845 bool - select ARM64 + select SNAPDRAGON_ARMV8 select LINUX_KERNEL_IMAGE_HEADER default n config QCS40X bool - select ARM64 + select SNAPDRAGON_ARMV8 select LINUX_KERNEL_IMAGE_HEADER default n +config IPQ40XX + bool + select SNAPDRAGON_ARMV7A + select DM_RESET + default n + +config SYS_LOAD_ADDR + default 0x80000000 if (IPQ40XX || SDM845 || QCS40X) + default 0x80080000 if (APQ8096 || APQ8016) + +config SYS_TEXT_BASE + default 0x8f600000 if APQ8016 + default 0x87300000 if IPQ40XX + +config NR_DRAM_BANKS + default 1 if (IPQ40XX || APQ8016) + default 2 if APQ8096 + config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x80000000 @@ -98,6 +131,12 @@ config TARGET_QCS404EVB - 1GiB RAM - 8GiB eMMC, uSD slot +config TARGET_IPQ4019 + bool "Generic IPQ4019 based board" + select IPQ40XX + help + Support for the generic Qualcomm IPQ4019 based board + endchoice source "board/qualcomm/dragonboard410c/Kconfig" diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 00997196ab..89e5a49780 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,7 +2,7 @@ # # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski(a)gmail.com> -obj-y += clock-snapdragon.o +obj-$(CONFIG_COMMON_SNAPDRAGON) += clock-snapdragon.o obj-y += pinctrl-snapdragon.o obj-$(CONFIG_SDM845) += clock-sdm845.o @@ -22,3 +22,6 @@ obj-$(CONFIG_APQ8016) += misc.o dram.o obj-$(CONFIG_QCS40X) += clock-qcs404.o obj-$(CONFIG_QCS40X) += sysmap-qcs404.o obj-$(CONFIG_QCS40X) += pinctrl-qcs404.o + +obj-$(CONFIG_IPQ40XX) += clock-ipq4019.o +obj-$(CONFIG_IPQ40XX) += pinctrl-ipq4019.o diff --git a/arch/arm/mach-snapdragon/clock-ipq4019.c b/arch/arm/mach-snapdragon/clock-ipq4019.c new file mode 100644 index 0000000000..c1d5c4ecdd --- /dev/null +++ b/arch/arm/mach-snapdragon/clock-ipq4019.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Clock drivers for Qualcomm IPQ40xx + * + * Copyright (c) 2020 Sartura Ltd. + * + * Author: Robert Marko <robert.marko(a)sartura.hr> + * + */ + +#include <clk-uclass.h> +#include <common.h> +#include <dm.h> +#include <errno.h> + +#include <dt-bindings/clock/qcom,ipq4019-gcc.h> + +struct msm_clk_priv { + phys_addr_t base; +}; + +ulong msm_set_rate(struct clk *clk, ulong rate) +{ + switch (clk->id) { + case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ + /* This clock is already initialized by SBL1 */ + return 0; + default: + return -EINVAL; + } +} + +static int msm_clk_probe(struct udevice *dev) +{ + struct msm_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static ulong msm_clk_set_rate(struct clk *clk, ulong rate) +{ + return msm_set_rate(clk, rate); +} + +static int msm_enable(struct clk *clk) +{ + switch (clk->id) { + case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/ + /* This clock is already initialized by SBL1 */ + return 0; + case GCC_PRNG_AHB_CLK: /*PRNG*/ + /* This clock is already initialized by SBL1 */ + return 0; + case GCC_USB3_MASTER_CLK: + case GCC_USB3_SLEEP_CLK: + case GCC_USB3_MOCK_UTMI_CLK: + case GCC_USB2_MASTER_CLK: + case GCC_USB2_SLEEP_CLK: + case GCC_USB2_MOCK_UTMI_CLK: + /* These clocks is already initialized by SBL1 */ + return 0; + default: + return -EINVAL; + } +} + +static struct clk_ops msm_clk_ops = { + .set_rate = msm_clk_set_rate, + .enable = msm_enable, +}; + +static const struct udevice_id msm_clk_ids[] = { + { .compatible = "qcom,gcc-ipq4019" }, + { } +}; + +U_BOOT_DRIVER(clk_msm) = { + .name = "clk_msm", + .id = UCLASS_CLK, + .of_match = msm_clk_ids, + .ops = &msm_clk_ops, + .priv_auto = sizeof(struct msm_clk_priv), + .probe = msm_clk_probe, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-ipq4019.c b/arch/arm/mach-snapdragon/pinctrl-ipq4019.c new file mode 100644 index 0000000000..3e365f8cc8 --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-ipq4019.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm IPQ40xx pinctrl + * + * Copyright (c) 2019 Sartura Ltd. + * + * Author: Robert Marko <robert.marko(a)sartura.hr> + */ + +#include "pinctrl-snapdragon.h" +#include <common.h> + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN]; + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"gpio", 0}, + {"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */ + {"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */ + {"blsp_uart1", 1}, + {"blsp_spi0_0", 1}, /* Only for GPIO:12,13,14,15 */ + {"blsp_spi0_1", 2}, /* Only for GPIO:54,55,56,57 */ + {"blsp_spi1", 2}, + {"mdio_0", 1}, /* Only for GPIO6 */ + {"mdio_1", 2}, /* Only for GPIO53 */ + {"mdc_0", 1}, /* Only for GPIO7 */ + {"mdc_1", 2}, /* Only for GPIO52 */ +}; + +static const char *ipq4019_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *ipq4019_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; +} + +static unsigned int ipq4019_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data ipq4019_data = { + .pin_count = 100, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = ipq4019_get_function_name, + .get_function_mux = ipq4019_get_function_mux, + .get_pin_name = ipq4019_get_pin_name, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index 4ed4ab4d4c..fc72f6ad92 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -1,9 +1,13 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * TLMM driver for Qualcomm APQ8016, APQ8096 + * TLMM driver for Qualcomm Snapdragon SOCs * * (C) Copyright 2018 Ramon Fried <ramon.fried(a)gmail.com> * + * Copyright (c) 2020 Sartura Ltd. + * + * Author: Robert Marko <robert.marko(a)sartura.hr> + * */ #include <common.h> @@ -30,6 +34,7 @@ struct msm_pinctrl_priv { static const struct pinconf_param msm_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 2 }, }; static int msm_get_functions_count(struct udevice *dev) @@ -96,6 +101,10 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, clrbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), TLMM_GPIO_PULL_MASK); break; + case PIN_CONFIG_BIAS_PULL_UP: + clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), + TLMM_GPIO_PULL_MASK, argument); + break; default: return 0; } @@ -103,18 +112,6 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, return 0; } -static struct pinctrl_ops msm_pinctrl_ops = { - .get_pins_count = msm_get_pins_count, - .get_pin_name = msm_get_pin_name, - .set_state = pinctrl_generic_set_state, - .pinmux_set = msm_pinmux_set, - .pinconf_num_params = ARRAY_SIZE(msm_conf_params), - .pinconf_params = msm_conf_params, - .pinconf_set = msm_pinconf_set, - .get_functions_count = msm_get_functions_count, - .get_function_name = msm_get_function_name, -}; - static int msm_pinctrl_bind(struct udevice *dev) { ofnode node = dev_ofnode(dev); @@ -141,11 +138,24 @@ static int msm_pinctrl_bind(struct udevice *dev) return 0; } +static struct pinctrl_ops msm_pinctrl_ops = { + .get_pins_count = msm_get_pins_count, + .get_pin_name = msm_get_pin_name, + .set_state = pinctrl_generic_set_state, + .pinmux_set = msm_pinmux_set, + .pinconf_num_params = ARRAY_SIZE(msm_conf_params), + .pinconf_params = msm_conf_params, + .pinconf_set = msm_pinconf_set, + .get_functions_count = msm_get_functions_count, + .get_function_name = msm_get_function_name, +}; + static const struct udevice_id msm_pinctrl_ids[] = { { .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data }, { .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data }, { .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data }, { .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data }, + { .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data }, { } }; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h index 178ee01a41..2ba61a45b3 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -29,5 +29,6 @@ extern struct msm_pinctrl_data apq8016_data; extern struct msm_pinctrl_data apq8096_data; extern struct msm_pinctrl_data sdm845_data; extern struct msm_pinctrl_data qcs404_data; +extern struct msm_pinctrl_data ipq4019_data; #endif diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index f4ca174805..cdc73d46b4 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -8,7 +8,7 @@ config MSM8916_USB_PHY config PHY_QCOM_IPQ4019_USB tristate "Qualcomm IPQ4019 USB PHY driver" - depends on PHY && ARCH_IPQ40XX + depends on PHY && IPQ40XX help Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 4cb0ba0850..a3d5fe8872 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -158,7 +158,7 @@ config RESET_IMX7 config RESET_QCOM bool "Reset driver for Qualcomm SoCs" - depends on DM_RESET && (ARCH_SNAPDRAGON || ARCH_IPQ40XX) + depends on DM_RESET && ARCH_SNAPDRAGON default y help Support for reset controller on Qualcomm SoCs. diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c index 2c61d6a6dc..7e5eae190d 100644 --- a/drivers/reset/reset-qcom.c +++ b/drivers/reset/reset-qcom.c @@ -25,7 +25,7 @@ struct qcom_reset_map { u8 bit; }; -#ifdef CONFIG_ARCH_IPQ40XX +#ifdef CONFIG_IPQ40XX #include <dt-bindings/reset/qcom,ipq4019-reset.h> static const struct qcom_reset_map gcc_qcom_resets[] = { [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 }, diff --git a/drivers/smem/Kconfig b/drivers/smem/Kconfig index 73d51b3a7a..7169d0f205 100644 --- a/drivers/smem/Kconfig +++ b/drivers/smem/Kconfig @@ -15,7 +15,7 @@ config SANDBOX_SMEM config MSM_SMEM bool "Qualcomm Shared Memory Manager (SMEM)" depends on DM - depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX + depends on ARCH_SNAPDRAGON help Enable support for the Qualcomm Shared Memory Manager. The driver provides an interface to items in a heap shared among all diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2f12081f88..a2d5c689ff 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -361,7 +361,7 @@ config PL022_SPI config SPI_QUP bool "Qualcomm SPI controller with QUP interface" - depends on ARCH_IPQ40XX + depends on ARCH_SNAPDRAGON help Qualcomm Universal Peripheral (QUP) core is an AHB slave that provides a common data path (an output FIFO and an input FIFO)

1 0

[PATCH 0/2] mach-snapdragon/mach-ipq40xx: fix, merge and refactoring
by Andrey Volkov 25 Oct '22

25 Oct '22

Hello, At the present timeI'm working with 2 Qualcomm's Snapdragon SOCs: msm8916 and msm9207 both of them are mostly the same, except application CPU: former is ARMv8 based and latter is ARMv7A (same as IPQ4019), so keep 2 archs for almost same (from IPs point of view) things is a real headache for me. In this regard, I decided to merge and refactor the above archs, and you can find the result of it in the following two patches: * the first patch is just added some missing SOCs definitions to KConfig and minor bug fixing (like missing PINCTL, CLK etc dependencies), * the second one is a real merge. -- Regards Andrey VOLKOV

1 0

[PATCH] mmc: Fix static checker warnings
by Venkatesh Yadav Abbarapu 25 Oct '22

25 Oct '22

Correct pointer dereferencing check to be more consistent. Eliminate the below smatch warning: drivers/mmc/mmc.c:3118 mmc_init_device() warn: variable dereferenced before check 'm' (see line 3116) Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu(a)amd.com> --- drivers/mmc/mmc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 0b7c0be8cb..210703ea46 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -3113,10 +3113,12 @@ int mmc_init_device(int num) } m = mmc_get_mmc_dev(dev); - m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */ - if (!m) return 0; + + /* Initialising user set speed mode */ + m->user_speed_mode = MMC_MODES_END; + if (m->preinit) mmc_start_init(m); -- 2.17.1

4 3

[PATCH] mmc: dwmmc: only clear handled interrupts
by John Keeping 25 Oct '22

25 Oct '22

Unconditionally clearing DTO when RXDR is set leads to spurious timeouts in FIFO mode transfers if events occur in the following order: mask = dwmci_readl(host, DWMCI_RINTSTS); // Hardware asserts DWMCI_INTMSK_DTO here dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_DTO); if (mask & DWMCI_INTMSK_DTO) { // Unreachable as DTO is cleared without being handled! return 0; } Only clear interrupts that we have seen and are handling so that DTO is not missed. Signed-off-by: John Keeping <john(a)metanate.com> --- drivers/mmc/dw_mmc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4232c5eb8c..5085a3b491 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -168,7 +168,8 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) if (data->flags == MMC_DATA_READ && (mask & (DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO))) { dwmci_writel(host, DWMCI_RINTSTS, - DWMCI_INTMSK_RXDR | DWMCI_INTMSK_DTO); + mask & (DWMCI_INTMSK_RXDR | + DWMCI_INTMSK_DTO)); while (size) { ret = dwmci_fifo_ready(host, DWMCI_FIFO_EMPTY, -- 2.37.3

5 4

[PATCH 1/3] mmc: stm32_sdmmc2: add dual data rate support
by Yann Gautier 25 Oct '22

25 Oct '22

To support dual data rate with STM32 sdmmc2 driver, the dedicated bit (DDR - BIT(18)) needs to be set in the CLKRC register. Clock bypass (no divider) is not allowed in this case. This is required for the eMMC DDR modes. Signed-off-by: Yann Gautier <yann.gautier(a)foss.st.com> --- drivers/mmc/stm32_sdmmc2.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index bfce8a2e4a..3cfa5a66f1 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -598,13 +598,16 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev) * clk_div > 0 and NEGEDGE = 1 => command and data generated on * SDMMCCLK falling edge */ - if (desired && ((sys_clock > desired) || + if (desired && (sys_clock > desired || mmc->ddr_mode || IS_RISING_EDGE(plat->clk_reg_msk))) { clk = DIV_ROUND_UP(sys_clock, 2 * desired); if (clk > SDMMC_CLKCR_CLKDIV_MAX) clk = SDMMC_CLKCR_CLKDIV_MAX; } + if (mmc->ddr_mode) + clk |= SDMMC_CLKCR_DDR; + if (mmc->bus_width == 4) clk |= SDMMC_CLKCR_WIDBUS_4; if (mmc->bus_width == 8) -- 2.25.1

3 6

[PATCH v2 0/2] mmc: Add support for F_SDH30_E51
by Kunihiko Hayashi 25 Oct '22

25 Oct '22

This series adds a new quirk "SUPPORT_SINGLE" for single transaction to sdhci framework and Socionext F_SDH30_E51 IP support to f_sdh30 driver. Changes since v1: - Fix register settings for false case in f_sdh30_e51_init() - Remove "|" operator for quirks initialization - Add Reviewed-by tag Kunihiko Hayashi (2): mmc: sdhci: Add new quirks for SUPPORT_SINGLE mmc: f_sdh30: Add support for F_SDH30_E51 drivers/mmc/Kconfig | 4 +-- drivers/mmc/f_sdh30.c | 66 +++++++++++++++++++++++++++++++++++++++++-- drivers/mmc/sdhci.c | 8 ++++-- include/sdhci.h | 1 + 4 files changed, 72 insertions(+), 7 deletions(-) -- 2.17.1

2 4

[PATCH] mmc: ftsdc010: make command timeout 250 ms as in the comment
by Sergei Antonov 25 Oct '22

25 Oct '22

Get rid of discrepancy beween comment /* 250 ms */ and code which shifts by 4 thus dividing by 16. So change code to shift by 2 and make the timeout value 250 ms. Signed-off-by: Sergei Antonov <saproj(a)gmail.com> --- drivers/mmc/ftsdc010_mci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 570d54cf9d8f..cabb747fbbdb 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -30,7 +30,7 @@ #include <syscon.h> #include <linux/err.h> -#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */ +#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */ #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */ #if CONFIG_IS_ENABLED(OF_PLATDATA) -- 2.34.1

3 2

[PATCH v3 03/19] imx: kontron-sl-mx8mm: Remove custom board_boot_order() workaround
by Frieder Schrempf 24 Oct '22

24 Oct '22

From: Frieder Schrempf <frieder.schrempf(a)kontron.de> Nowadays detecting the SPI NOR as boot device from the ROMAPI is fixed and works even if the SPI NOR is used as fallback boot device. Therefore we don't need this workaround anymore. Signed-off-by: Frieder Schrempf <frieder.schrempf(a)kontron.de> Reviewed-by: Fabio Estevam <festevam(a)denx.de> --- Changes in v3: * none Changes in v2: * new patch --- board/kontron/sl-mx8mm/spl.c | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index c379d37f1e8..2a562f4ac97 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -238,25 +238,3 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } - -void board_boot_order(u32 *spl_boot_list) -{ - u32 bootdev = spl_boot_device(); - - /* - * The default boot fuse settings use the SD card (MMC2) as primary - * boot device, but allow SPI NOR as a fallback boot device. - * We can't detect the fallback case and spl_boot_device() will return - * BOOT_DEVICE_MMC2 despite the actual boot device being SPI NOR. - * Therefore we try to load U-Boot proper vom SPI NOR after loading - * from MMC has failed. - */ - spl_boot_list[0] = bootdev; - - switch (bootdev) { - case BOOT_DEVICE_MMC1: - case BOOT_DEVICE_MMC2: - spl_boot_list[1] = BOOT_DEVICE_SPI; - break; - } -} -- 2.37.2

4 36

[PATCH v3 0/8] arm: dts: imx: sync device trees with upstream linux kernel part 1
by Marcel Ziswiler 24 Oct '22

24 Oct '22

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> This series synchronises them imx device trees with the upstream Linux kernel (v6.0-rc1). I split it into two parts. This is part 1. It also fixes a few issues as discussed during/after the pre-mature application of my first series [1]. I am not touching kontron-sl-mx6ul as Frieder already took care of those [2]. Feedback welcome. Thanks! [1] https://patchwork.ozlabs.org/project/uboot/cover/20220721132748.1052244-1-m… [2] https://patchwork.ozlabs.org/project/uboot/cover/20220823142917.306176-1-fr… Changes in v3: - Incorporate feedback from Jesse. Changes in v2: - imxrt1050: Re-added DDR timings aka semc node as pointed out by Fabio. Thanks! - imx8ulp: Re-added s400_mu device tree node. Marcel Ziswiler (8): vf610: synchronise device tree with linux imxrt1020: fix lpuart issue in common u-boot device tree imxrt1050: synchronise device tree with linux imx8ulp: synchronise device tree with linux imx8mq: synchronise device tree with linux imx8mp: synchronise device tree with linux imx8mn: synchronise device tree with linux imx8mm: synchronise device tree with linux arch/arm/dts/imx8mm-beacon-baseboard.dtsi | 4 +- arch/arm/dts/imx8mm-evk.dtsi | 43 ++ arch/arm/dts/imx8mm-icore-mx8mm.dtsi | 12 +- arch/arm/dts/imx8mm-mx8menlo.dts | 4 +- arch/arm/dts/imx8mm-u-boot.dtsi | 2 +- arch/arm/dts/imx8mm-venice-gw700x.dtsi | 24 +- arch/arm/dts/imx8mm-venice-gw7901.dts | 8 +- arch/arm/dts/imx8mm-venice-gw7902.dts | 10 +- arch/arm/dts/imx8mm-venice-gw7903.dts | 6 +- arch/arm/dts/imx8mm-verdin.dtsi | 10 +- arch/arm/dts/imx8mn-beacon-baseboard.dtsi | 4 +- arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 2 +- .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 2 +- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 2 +- arch/arm/dts/imx8mn-evk.dtsi | 45 +- .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 2 +- arch/arm/dts/imx8mn-var-som-symphony.dts | 6 +- arch/arm/dts/imx8mn-venice-gw7902.dts | 8 +- arch/arm/dts/imx8mn-venice-u-boot.dtsi | 2 +- arch/arm/dts/imx8mn.dtsi | 13 +- arch/arm/dts/imx8mp-dhcom-pdk2.dts | 27 +- arch/arm/dts/imx8mp-dhcom-som.dtsi | 20 +- arch/arm/dts/imx8mp-evk.dts | 126 ++-- arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 48 +- arch/arm/dts/imx8mp-u-boot.dtsi | 2 +- arch/arm/dts/imx8mp-venice-gw74xx.dts | 116 ++-- arch/arm/dts/imx8mp-verdin.dtsi | 14 +- arch/arm/dts/imx8mp.dtsi | 33 +- arch/arm/dts/imx8mq-evk.dts | 43 ++ arch/arm/dts/imx8mq-u-boot.dtsi | 10 +- arch/arm/dts/imx8mq.dtsi | 15 +- arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 15 +- arch/arm/dts/imx8ulp-evk.dts | 191 +----- arch/arm/dts/imx8ulp-pinfunc.h | 4 +- arch/arm/dts/imx8ulp.dtsi | 564 +++++------------- arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 7 +- arch/arm/dts/imxrt1020-evk.dts | 1 - arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 162 ++++- arch/arm/dts/imxrt1050-evk.dts | 257 +------- arch/arm/dts/imxrt1050-pinfunc.h | 2 +- arch/arm/dts/imxrt1050.dtsi | 168 +++--- arch/arm/dts/vf610-pinfunc.h | 2 +- include/dt-bindings/clock/imx8mp-clock.h | 13 +- include/dt-bindings/clock/imx8ulp-clock.h | 49 +- include/dt-bindings/clock/imxrt1050-clock.h | 9 +- include/dt-bindings/interconnect/imx8mm.h | 50 ++ include/dt-bindings/interconnect/imx8mn.h | 41 ++ include/dt-bindings/power/imx8mp-power.h | 15 +- include/dt-bindings/power/imx8ulp-power.h | 26 + include/dt-bindings/reset/imx8mp-reset.h | 50 ++ include/dt-bindings/reset/imx8mq-reset.h | 61 +- include/dt-bindings/reset/imx8ulp-pcc-reset.h | 59 ++ 52 files changed, 1153 insertions(+), 1256 deletions(-) create mode 100644 include/dt-bindings/interconnect/imx8mm.h create mode 100644 include/dt-bindings/interconnect/imx8mn.h create mode 100644 include/dt-bindings/power/imx8ulp-power.h create mode 100644 include/dt-bindings/reset/imx8mp-reset.h create mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h -- 2.35.1

6 17

[PATCH v4 1/5] imx8m: USDHC3 base address definition for i.MX8MP
by Martyn Welch 24 Oct '22

24 Oct '22

The i.MX8MP also has USDHC3, allow access to the relvant base address definition. Signed-off-by: Martyn Welch <martyn.welch(a)collabora.com> --- Changes in v2: - None Changes in v3: - None Changes in v4: - None arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 29d5baaab8..c46d4f7e00 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -47,7 +47,7 @@ #define USDHC1_BASE_ADDR 0x30B40000 #define USDHC2_BASE_ADDR 0x30B50000 #define QSPI0_AMBA_BASE 0x08000000 -#ifdef CONFIG_IMX8MM +#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MP) #define USDHC3_BASE_ADDR 0x30B60000 #endif #define UART_BASE_ADDR(n) ( \ -- 2.35.1

2 6