October 2022 - U-Boot

[PATCH v2 0/4] Update Microchip PolarFire SoC
by Padmarao Begari 26 Oct '22

26 Oct '22

This patch set updates Microchip PolarFire SoC Icicle Kit support of RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://source.denx.de/u-boot/u-boot) at commit id d843273a8022e70ccbdb6ad446b3335c3753e84f The memory device node is updated based on the latest FPGA reference design v2022.10 and a small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, add Microchip QSPI driver. Changes in v2: - Add Co-developed-by with patch - Replace spi-nand with flash in device node - Add board details for QSPI NAND - Rename QSPI driver file with microchip-coreqspi - Add microchip,coreqspi-rtl-v2 to the compatible list - Use MICROCHIP_COREQSPI instead of MICROCHIP_QSPI in kconfig Padmarao Begari (4): riscv: dts: Update memory configuration riscv: dts: Add QSPI NAND device node spi: Add Microchip PolarFire SoC QSPI driver riscv: Update Microchip MPFS Icicle Kit support arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 85 ++-- board/microchip/mpfs_icicle/Kconfig | 7 + configs/microchip_mpfs_icicle_defconfig | 1 + drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/microchip_coreqspi.c | 505 +++++++++++++++++++ 6 files changed, 549 insertions(+), 56 deletions(-) create mode 100644 drivers/spi/microchip_coreqspi.c -- 2.25.1

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[PATCH v3 0/6] eficonfig: add UEFI Secure Boot key maintenance interface
by Masahisa Kojima 26 Oct '22

26 Oct '22

This series adds the UEFI Secure Boot key maintenance interface to the eficonfig command. User can enroll and delete the PK, KEK, db and dbx. Source code can be cloned with: $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git -b kojima/eficonfig_sbkey_v3 [Major Changes] - rebased on top of u-boot/master Masahisa Kojima (6): eficonfig: refactor eficonfig_select_file_handler() eficonfig: expose append entry function eficonfig: add UEFI Secure Boot Key enrollment interface eficonfig: add "Show/Delete Signature Database" menu entry test/eficonfig: support secure boot key maintenance menu test: add test for eficonfig secure boot key management cmd/Makefile | 3 + cmd/eficonfig.c | 48 +- cmd/eficonfig_sbkey.c | 751 ++++++++++++++++++ include/efi_config.h | 10 + test/py/tests/test_eficonfig/conftest.py | 84 +- test/py/tests/test_eficonfig/defs.py | 14 + .../py/tests/test_eficonfig/test_eficonfig.py | 4 +- .../test_eficonfig/test_eficonfig_sbkey.py | 472 +++++++++++ 8 files changed, 1360 insertions(+), 26 deletions(-) create mode 100644 cmd/eficonfig_sbkey.c create mode 100644 test/py/tests/test_eficonfig/defs.py create mode 100644 test/py/tests/test_eficonfig/test_eficonfig_sbkey.py -- 2.17.1

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[PATCH v1 0/3] Implement Tegra Timer with dependencies
by Svyatoslav Ryhel 26 Oct '22

26 Oct '22

- rework clock_osc_freq detection as it is needed for timer - implement timer for ARMv7 Tegra devices - set timer to be selected automatically Svyatoslav Ryhel (3): ARM: tegra: remap clock_osc_freq for all Tegra family drivers: timer: add timer driver for ARMv7 based Tegra devices ARM: tegra: include timer as default option arch/arm/Kconfig | 1 + arch/arm/include/asm/arch-tegra/clock.h | 9 +- arch/arm/mach-tegra/Kconfig | 2 + arch/arm/mach-tegra/clock.c | 17 +++- arch/arm/mach-tegra/cpu.c | 70 ++++++++++--- arch/arm/mach-tegra/tegra114/clock.c | 13 +-- arch/arm/mach-tegra/tegra124/clock.c | 13 +-- arch/arm/mach-tegra/tegra20/clock.c | 4 +- arch/arm/mach-tegra/tegra210/clock.c | 22 +---- arch/arm/mach-tegra/tegra30/clock.c | 10 +- drivers/timer/Kconfig | 8 ++ drivers/timer/Makefile | 1 + drivers/timer/tegra-timer.c | 124 ++++++++++++++++++++++++ drivers/usb/host/ehci-tegra.c | 46 +++++++-- include/configs/tegra-common.h | 6 -- 15 files changed, 267 insertions(+), 79 deletions(-) create mode 100644 drivers/timer/tegra-timer.c -- 2.34.1

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Re: [PATCH 3/6] net: (actually/better) deal with CVE-2022-{30790, 30552}
by Artur Łącki 26 Oct '22

26 Oct '22

I tested these patches with my exploit. At the moment it looks like the vulnerability has been fixed.

2 1

[PATCH v4 0/6] Support UEFI SPI I/O protocol
by Paul Barker 25 Oct '22

25 Oct '22

These patches add support for the UEFI SPI I/O protocol defined in the UEFI Platform Initialization (PI) Specification, Version 1.7 Errata A (April 2020). This allows a UEFI application to interact with devices on the SPI bus. This support is initially intended to be used to communicate with SPI devices from "pre-boot" UEFI applications which perform setup before the main OS is loaded. Other use cases may also be supported, however this is not intended to be a replacement for UEFI capsule updates. The "pre-boot" UEFI application which we are currently developing will interact with a Micron Authenta[1] flash device, sending vendor-specific commands over the SPI bus to make use of Authenta security features, to verify flash integrity and to generate ephemeral keys based on the flash contents. The code here is self-contained and easy to enable/disable at compile time. Compilation testing with am335x_evm_defconfig shows that the size of u-boot.img increases by less than 2kB when CONFIG_EFI_SPI_PROTOCOL is enabled. [1]: https://www.micron.com/-/media/client/global/documents/products/product-fly… Changes since v3: * Add implementation of spi_set_speed() so we can use this in efi_spi_io_transaction(). * Rename convert_efi_string() to efi_convert_string() and move to efi_string.c as a common helper function. * Call spi_set_speed() instead of manually de-referencing the function pointer in struct dm_spi_ops. * Don't call efi_delete_handle() in destroy_efi_spi_peripheral(). * Use '%pUl' to print guid string. * Split efi_selftest changes into a separate patch. Changes since v2: * Added description to efi_spi_protocol.h. * Moved definition of EFI_SPI_CONFIGURATION_GUID to efi_api.h and added it to the list in lib/uuid.c. * Fixed UEFI GUID byte order in test.dts and in debug output. * Use log_debug() instead of printf() for debug output. * Add test cases to confirm that efi_legacy_spi_controller_protocol functions return EFI_UNSUPPORTED (as they are not currently implemented) Changes since v1: * Skip emulated SPI peripherals. These appear as duplicates within the list of devices on the bus when using the sandbox SPI drivers. * Make most printf statements debug only. * Add efi_seltest unit test. * Do not enable config EFI_SPI_PROTOCOL by default. * Mark functions with EFIAPI where necessary. * Handle debug_transaction argument to efi_spi_io_transaction(). * Handle a value of zero for target->max_read_size & target->max_write_size. * Probe inactive SPI devices when initializing the EFI SPI protocol to ensure that dev_get_parent_priv() returns valid data and the exported devices are ready to use. Paul Barker (6): spi: Implement spi_set_speed efi: Add string conversion helper efi_loader: Add SPI I/O protocol support efi_selftest: Add tests for SPI protocol support arm: dts: am335x-sancloud-bbe-lite: UEFI SPI export am335x_evm_defconfig: Enable Micron SPI flash support MAINTAINERS | 7 + arch/arm/dts/am335x-sancloud-bbe-lite.dts | 10 +- arch/sandbox/dts/test.dts | 13 + configs/am335x_evm_defconfig | 1 + drivers/spi/spi-uclass.c | 15 + include/efi_api.h | 4 + include/efi_loader.h | 7 +- include/efi_spi_protocol.h | 166 ++++++ include/spi.h | 2 +- lib/efi_loader/Kconfig | 8 + lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_setup.c | 6 + lib/efi_loader/efi_spi_protocol.c | 590 +++++++++++++++++++ lib/efi_loader/efi_string.c | 24 + lib/efi_selftest/Makefile | 1 + lib/efi_selftest/efi_selftest_spi_protocol.c | 284 +++++++++ lib/uuid.c | 4 + 17 files changed, 1139 insertions(+), 4 deletions(-) create mode 100644 include/efi_spi_protocol.h create mode 100644 lib/efi_loader/efi_spi_protocol.c create mode 100644 lib/efi_selftest/efi_selftest_spi_protocol.c -- 2.25.1

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Pull request: u-boot-spi/master
by Jagan Teki 25 Oct '22

25 Oct '22

Hi Tom, Please pull this PR. Summary: - Add s28hl512t, s28hl01gt (Takahiro) - Rework s25hx_t_post_bfpt_fixup() (Takahiro) CI: https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/13925 thanks, Jagan. The following changes since commit 7723828c97bc107d2fba976fc50403ac8747f1bc: Merge branch '2022-10-21-enforce-some-DM-migrations' (2022-10-21 15:32:45 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-spi.git master for you to fetch changes up to 622b5d356136f9172db7fe7ba240cd9e45097a19: cmd: sf: Handle unaligned 'update' start offset (2022-10-25 10:17:33 +0530) ---------------------------------------------------------------- Marek Vasut (1): cmd: sf: Handle unaligned 'update' start offset Takahiro Kuwano (8): mtd: spi-nor-core: Rename s28hs512t prefix mtd: spi-nor-core: Rename configuration macro for S28 support mtd: spi-nor-ids: Add s28hl512t, s28hl01gt, and s28hs01gt IDs mtd: spi-nor-core: Default to addr_width of 3 for configurable widths mtd: spi-nor-core: Track flash's internal address mode mtd: spi-nor-core: Rework spansion_read/write_any_reg() to use addr_mode_nbytes mtd: spi-nor-core: Rework s25hx_t_post_bfpt_fixup() for flash's internal address mode mtd: spi-nor-core: Fix index value for SCCR dwords cmd/sf.c | 18 +++++--- configs/j721s2_evm_a72_defconfig | 2 +- configs/j721s2_evm_r5_defconfig | 2 +- drivers/mtd/spi/Kconfig | 10 ++--- drivers/mtd/spi/spi-nor-core.c | 92 ++++++++++++++++++++++++---------------- drivers/mtd/spi/spi-nor-ids.c | 5 ++- include/linux/mtd/spi-nor.h | 5 +++ 7 files changed, 83 insertions(+), 51 deletions(-)

2 1

arm: hello_world example application not working on RPI1
by Patrick Zacharias 25 Oct '22

25 Oct '22

Hello, I tried getting examples/standalone/hello_world to run as of 1e892ef0b59a4a04971ac23619b95917020b3e18 I installed the Ubuntu (20.04 LTS) ARM toolchain (I tried it with a Linaro toolchain as well) and built the source code using "make rpi_defconfig" Afterwards, I used menuconfig to enable the build of the examples. I created a boot.scr file using following script: "fatload mmc 0:1 $loadaddr /uEnv.txt env import -t $loadaddr $filesize run bootcmd" and converted it using mkimage. The content of the uEnv.txt is as following: "bootcmd=mmc rescan; echo Test ${loadaddr} end; load mmc 0:1 0x0c100000 hello_world.bin; go 0x0c100000" I copied u-boot.bin, boot.scr and uEnv.txt to the SD card (over the existing parition created by Raspbian). And adjusted the config.txt to read: "kernel=u-boot.bin" U-Boot shows up, however after the program loaded (and go is executed), the Raspberry Pi freezes. I tried this with tftp as well and with and without ELF files (using "bootelf"). The result remains the same. Booting the EFI applications using "bootefi" works. Additionally, when trying to build U-Boot using clang-12, I ran into two errors. The first one was in arch/arm/lib/relocate.S, where it complains about the symbol "relocate_vectors" first being declared as weak, then again as global. "error: relocate_vectors changed binding to STB_GLOBAL" To fix this, I removed the .weak line and renamed ENTRY to WEAK. Afterwards, U-Boot itself built, but the hello_world application didn't find any of the exported functions. (EXPORT_FUNC is probably just a stub for clang?) Greetings, Patrick

1 0

[PATCH] arm64: dts: meson: nanopi-k2: readd PHY reset properties
by Christian Hewitt 25 Oct '22

25 Oct '22

The sync of device-tree/bindings in 11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some GXBB boards; the PHY seems to need proper reset timing to function in u-boot and Linux. Re-add the old PHY reset binding for dwmac until we support new bindings in the PHY node. This borrows the same fix applied to the Odroid C2 board [0]. [0] https://lists.denx.de/pipermail/u-boot/2021-April/446658.html Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2") Signed-off-by: Christian Hewitt <christianshewitt(a)gmail.com> --- arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi b/arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi index c35158d7e9..2a245bbe7f 100644 --- a/arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi +++ b/arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi @@ -5,3 +5,10 @@ */ #include "meson-gx-u-boot.dtsi" + +&ethmac { + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; +}; + -- 2.17.1

2 1

[PATCH] riscv: Rename Andes PLIC to PLICSW
by Yu Chien Peter Lin 25 Oct '22

25 Oct '22

As PLICSW is used to trigger the software interrupt, we should rename Andes PLIC configuration and file name to reflect the usage. This patch also updates PLMT and PLICSW compatible strings to be consistent with OpenSBI fdt driver. Signed-off-by: Yu Chien Peter Lin <peterlin(a)andestech.com> --- arch/riscv/Kconfig | 6 ++--- arch/riscv/cpu/ax25/Kconfig | 2 +- arch/riscv/dts/ae350-u-boot.dtsi | 2 +- arch/riscv/dts/ae350_32.dts | 6 ++--- arch/riscv/dts/ae350_64.dts | 6 ++--- arch/riscv/include/asm/global_data.h | 4 +-- arch/riscv/include/asm/syscon.h | 2 +- arch/riscv/lib/Makefile | 2 +- .../lib/{andes_plic.c => andes_plicsw.c} | 26 +++++++++---------- 9 files changed, 28 insertions(+), 28 deletions(-) rename arch/riscv/lib/{andes_plic.c => andes_plicsw.c} (76%) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8f9578171d..4d64e9be3f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -199,7 +199,7 @@ config SIFIVE_CACHE help This enables the operations to configure SiFive cache -config ANDES_PLIC +config ANDES_PLICSW bool depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP @@ -207,8 +207,8 @@ config ANDES_PLIC select SPL_REGMAP if SPL select SPL_SYSCON if SPL help - The Andes PLIC block holds memory-mapped claim and pending registers - associated with software interrupt. + The Andes PLICSW block holds memory-mapped claim and pending + registers associated with software interrupt. config SMP bool "Symmetric Multi-Processing" diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 941d963ece..4a7295d30c 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -4,7 +4,7 @@ config RISCV_NDS imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) + imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) imply SPL_CPU imply SPL_OPENSBI diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi index 0d4201cfae..7011f59831 100644 --- a/arch/riscv/dts/ae350-u-boot.dtsi +++ b/arch/riscv/dts/ae350-u-boot.dtsi @@ -36,7 +36,7 @@ soc { u-boot,dm-spl; - plic1: interrupt-controller@e6400000 { + plicsw: interrupt-controller@e6400000 { u-boot,dm-spl; }; diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 083f676333..96ef8bd8dd 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -146,8 +146,8 @@ &CPU3_intc 11 &CPU3_intc 9>; }; - plic1: interrupt-controller@e6400000 { - compatible = "riscv,plic1"; + plicsw: interrupt-controller@e6400000 { + compatible = "andestech,plicsw"; #interrupt-cells = <1>; interrupt-controller; reg = <0xe6400000 0x400000>; @@ -159,7 +159,7 @@ }; plmt0@e6000000 { - compatible = "riscv,plmt0"; + compatible = "andestech,plmt0"; interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7 &CPU2_intc 7 diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index 74cff9122d..cddbaec98a 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -146,8 +146,8 @@ &CPU3_intc 11 &CPU3_intc 9>; }; - plic1: interrupt-controller@e6400000 { - compatible = "riscv,plic1"; + plicsw: interrupt-controller@e6400000 { + compatible = "andestech,plicsw"; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe6400000 0x0 0x400000>; @@ -159,7 +159,7 @@ }; plmt0@e6000000 { - compatible = "riscv,plmt0"; + compatible = "andestech,plmt0"; interrupts-extended = <&CPU0_intc 7 &CPU1_intc 7 &CPU2_intc 7 diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 858594a191..6fdc86dd8b 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -21,8 +21,8 @@ struct arch_global_data { #if CONFIG_IS_ENABLED(SIFIVE_CLINT) void __iomem *clint; /* clint base address */ #endif -#ifdef CONFIG_ANDES_PLIC - void __iomem *plic; /* plic base address */ +#ifdef CONFIG_ANDES_PLICSW + void __iomem *plicsw; /* plic base address */ #endif #if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h index c3629e4b53..f2b37975f3 100644 --- a/arch/riscv/include/asm/syscon.h +++ b/arch/riscv/include/asm/syscon.h @@ -13,7 +13,7 @@ enum { RISCV_NONE, RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */ - RISCV_SYSCON_PLIC, /* Platform Level Interrupt Controller (PLIC) */ + RISCV_SYSCON_PLICSW, /* Andes PLICSW */ }; #endif /* _ASM_SYSCON_H */ diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 06020fcc2a..d6a8ae9728 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -13,7 +13,7 @@ obj-y += cache.o obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o -obj-$(CONFIG_ANDES_PLIC) += andes_plic.o +obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o else obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plicsw.c similarity index 76% rename from arch/riscv/lib/andes_plic.c rename to arch/riscv/lib/andes_plicsw.c index 1eabcacd09..324eb445aa 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plicsw.c @@ -37,8 +37,8 @@ static int enable_ipi(int hart) unsigned int en; en = ENABLE_HART_IPI << hart; - writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); - writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic + 0x4, hart)); + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart)); + writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw + 0x4, hart)); return 0; } @@ -46,14 +46,14 @@ static int enable_ipi(int hart) int riscv_init_ipi(void) { int ret; - long *base = syscon_get_first_range(RISCV_SYSCON_PLIC); + long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW); ofnode node; struct udevice *dev; u32 reg; if (IS_ERR(base)) return PTR_ERR(base); - gd->arch.plic = base; + gd->arch.plicsw = base; ret = uclass_find_first_device(UCLASS_CPU, &dev); if (ret) @@ -88,7 +88,7 @@ int riscv_send_ipi(int hart) { unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); - writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, + writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw, gd->arch.boot_hart)); return 0; @@ -98,8 +98,8 @@ int riscv_clear_ipi(int hart) { u32 source_id; - source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); - writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart)); + source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plicsw, hart)); + writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plicsw, hart)); return 0; } @@ -108,21 +108,21 @@ int riscv_get_ipi(int hart, int *pending) { unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); - *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw, gd->arch.boot_hart)); *pending = !!(*pending & ipi); return 0; } -static const struct udevice_id andes_plic_ids[] = { - { .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC }, +static const struct udevice_id andes_plicsw_ids[] = { + { .compatible = "andestech,plicsw", .data = RISCV_SYSCON_PLICSW }, { } }; -U_BOOT_DRIVER(andes_plic) = { - .name = "andes_plic", +U_BOOT_DRIVER(andes_plicsw) = { + .name = "andes_plicsw", .id = UCLASS_SYSCON, - .of_match = andes_plic_ids, + .of_match = andes_plicsw_ids, .flags = DM_FLAG_PRE_RELOC, }; -- 2.34.1

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[PATCH v3] imx: imx8qm-rom7720: switch to binman
by Oliver Graute 25 Oct '22

25 Oct '22

Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> --- Changes for v3 - just rebased to master Changes for v2 - just rebased to master arch/arm/dts/imx8qm-rom7720-a1.dts | 1 + arch/arm/dts/imx8qm-u-boot.dtsi | 133 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 1 + .../advantech/imx8qm_rom7720_a1/imximage.cfg | 4 +- configs/imx8qm_rom7720_a1_4G_defconfig | 2 +- doc/board/advantech/imx8qm-rom7720-a1.rst | 3 +- 6 files changed, 139 insertions(+), 5 deletions(-) create mode 100644 arch/arm/dts/imx8qm-u-boot.dtsi diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts b/arch/arm/dts/imx8qm-rom7720-a1.dts index d1f2fff869..332d441c6d 100644 --- a/arch/arm/dts/imx8qm-rom7720-a1.dts +++ b/arch/arm/dts/imx8qm-rom7720-a1.dts @@ -10,6 +10,7 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" +#include "imx8qm-u-boot.dtsi" / { model = "Advantech iMX8QM Qseven series"; diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi new file mode 100644 index 0000000000..5da420ece6 --- /dev/null +++ b/arch/arm/dts/imx8qm-u-boot.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +/ { + binman: binman { + multiple-images; + }; +}; + +&binman { + u-boot-spl-ddr { + align = <4>; + align-size = <4>; + filename = "u-boot-spl-ddr.bin"; + pad-byte = <0xff>; + + u-boot-spl { + align-end = <4>; + filename = "u-boot-spl.bin"; + }; + }; + + spl { + filename = "spl.bin"; + + mkimage { + args = "-n spl/u-boot-spl.cfgout -T imx8image -e 0x100000"; + + blob { + filename = "u-boot-spl-ddr.bin"; + }; + }; + }; + + itb { + filename = "u-boot.itb"; + + fit { + description = "Configuration to load ATF before U-Boot"; + fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>; + fit,fdt-list = "of-list"; + #address-cells = <1>; + + images { + uboot { + arch = "arm64"; + compression = "none"; + description = "U-Boot (64-bit)"; + load = <CONFIG_SYS_TEXT_BASE>; + type = "standalone"; + + uboot_blob { + filename = "u-boot-nodtb.bin"; + type = "blob-ext"; + }; + }; + + atf { + arch = "arm64"; + compression = "none"; + description = "ARM Trusted Firmware"; + entry = <0x00910000>; + load = <0x00091000>; + type = "firmware"; + + atf_blob { + filename = "bl31.bin"; + type = "blob-ext"; + }; + }; + + scfw { + arch = "arm64"; + compression = "none"; + description = "System Controler Firmware"; + type = "firmware"; + + scfw_blob { + filename = "mx8qm-val-scfw-tcm.bin"; + type = "blob-ext"; + }; + }; + + seco { + arch = "arm64"; + compression = "none"; + description = "Seco Firmware"; + type = "firmware"; + + seco_blob { + filename = "mx8qm-ahab-container.img"; + type = "blob-ext"; + }; + }; + + fdt { + filename = "imx8qm-rom7720-a1"; + type = "flat_dt"; + compression = "none"; + + uboot_fdt_blob { + filename = "u-boot.dtb"; + type = "blob-ext"; + }; + }; + }; + + configurations { + default = "conf"; + + conf { + filename = "imx8qm-rom7720-a1"; + fdt = "fdt"; + firmware = "uboot"; + loadables = "atf"; + }; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl { + filename = "spl.bin"; + offset = <0x0>; + type = "blob-ext"; + }; + }; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index abb03340d8..71abbb33ea 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -82,6 +82,7 @@ config TARGET_CONGA_QMX8 config TARGET_IMX8QM_ROM7720_A1 bool "Support i.MX8QM ROM-7720-A1" + select BINMAN select BOARD_LATE_INIT select SUPPORT_SPL select IMX8QM diff --git a/board/advantech/imx8qm_rom7720_a1/imximage.cfg b/board/advantech/imx8qm_rom7720_a1/imximage.cfg index 5ecde0c530..43035088e3 100644 --- a/board/advantech/imx8qm_rom7720_a1/imximage.cfg +++ b/board/advantech/imx8qm_rom7720_a1/imximage.cfg @@ -4,8 +4,8 @@ */ -/* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 +BOOT_FROM sd + /* SoC type IMX8QM */ SOC_TYPE IMX8QM /* Append seco container image */ diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig index 3b099761a9..ed79cb732f 100644 --- a/configs/imx8qm_rom7720_a1_4G_defconfig +++ b/configs/imx8qm_rom7720_a1_4G_defconfig @@ -21,7 +21,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi" diff --git a/doc/board/advantech/imx8qm-rom7720-a1.rst b/doc/board/advantech/imx8qm-rom7720-a1.rst index bd4be1dbeb..953cf01fde 100644 --- a/doc/board/advantech/imx8qm-rom7720-a1.rst +++ b/doc/board/advantech/imx8qm-rom7720-a1.rst @@ -57,8 +57,7 @@ Build U-Boot $ export ATF_LOAD_ADDR=0x80000000 $ export BL33_LOAD_ADDR=0x80020000 $ make imx8qm_rom7720_a1_4G_defconfig - $ make u-boot.bin - $ make flash.bin + $ make Flash the binary into the SD card --------------------------------- -- 2.17.1

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