October 2022 - U-Boot

Re: [PATCH v3 2/4] riscv: dts: Add QSPI NAND device node
by Rick Chen 28 Oct '22

28 Oct '22

> From: Padmarao Begari <padmarao.begari(a)microchip.com> > Sent: Thursday, October 27, 2022 2:02 PM > To: u-boot(a)lists.denx.de; jagan(a)amarulasolutions.com; Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; bmeng.cn(a)gmail.com > Cc: cyril.jean(a)microchip.com; conor.dooley(a)microchip.com; valentina.fernandezalanis(a)microchip.com; nagasuresh.relli(a)microchip.com; Padmarao Begari <padmarao.begari(a)microchip.com> > Subject: [PATCH v3 2/4] riscv: dts: Add QSPI NAND device node > > Add QSPI NAND device node to the Microchip PolarFire SoC Icicle kit device tree. > > The Winbond NAND flash memory can be connected to the Icicle Kit by using the Mikroe Flash 5 click board and the Pi 3 Click shield. > > Signed-off-by: Padmarao Begari <padmarao.begari(a)microchip.com> > Reviewed-by: Conor Dooley <conor.dooley(a)microchip.com> > --- > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) Reviewed-by: Rick Chen <rick(a)andestech.com>

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Re: [PATCH v3 1/4] riscv: dts: Update memory configuration
by Rick Chen 28 Oct '22

28 Oct '22

> From: Padmarao Begari <padmarao.begari(a)microchip.com> > Sent: Thursday, October 27, 2022 2:02 PM > To: u-boot(a)lists.denx.de; jagan(a)amarulasolutions.com; Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com>; bmeng.cn(a)gmail.com > Cc: cyril.jean(a)microchip.com; conor.dooley(a)microchip.com; valentina.fernandezalanis(a)microchip.com; nagasuresh.relli(a)microchip.com; Padmarao Begari <padmarao.begari(a)microchip.com> > Subject: [PATCH v3 1/4] riscv: dts: Update memory configuration > > In the v2022.10 Icicle reference design, the seg registers have been changed, resulting in a required change to the memory map. > A small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, so that it can cache its payload between reboots of a specific context. > > Co-developed-by: Conor Dooley <conor.dooley(a)microchip.com> > Signed-off-by: Conor Dooley <conor.dooley(a)microchip.com> > Signed-off-by: Padmarao Begari <padmarao.begari(a)microchip.com> > Reviewed-by: Conor Dooley <conor.dooley(a)microchip.com> > --- > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 75 +++++--------------- > 1 file changed, 17 insertions(+), 58 deletions(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

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Re: [PATCH] rpi: copy the eMMC controller configuration from firmware-supplied DT
by Jian-Hong Pan 28 Oct '22

28 Oct '22

Ilya K <me(a)0upti.me> 於 2022年10月27日週四晚上7:48寫道： > > FWIW, my vote is for the revised series. Also, we've been shipping both patches downstream in NixOS for a while now, and had no issues with either. > > 27.10.2022, 09:27, "Peter Robinson" <pbrobinson(a)gmail.com>: > > Adding Matthias as the RPi maintainer. > > There was also this patch series which fixed it and a few other things > from the firmware DT [1] which is likely a better fix TBH. > > Either way Matthias can we get one of these upstream as even the RPi4 > Model B has moved to the newer rev of the SoCs so it's not a nice > experience for users if they're not aware of the differences/problems. > > Peter > > [1] https://lists.denx.de/pipermail/u-boot/2022-August/491455.html Great! This patch series looks nice, too. Jian-Hong Pan > On Wed, Oct 26, 2022 at 12:23 PM Jian-Hong Pan <jhp(a)endlessos.org> wrote: > > > From: Ilya Katsnelson <me(a)0upti.me> > > The RPi firmware adjusts the onboard eMMC controller's DMA mapping > ranges of the FDT for each BCM2711 SoC revisions on the Pi 4 and RPi 400 > automatically. > > If the following kernel does not boot with the correct eMMC controller's > DMA mapping ranges, the system on the SD card will boot failed and show > these error messages: > > mmc1: invalid bus width > mmc1: error -22 whilst initialising SD card > > This patch carries the adjustment from RPi firmware to the new loaded > FDT for the following kernel. > > Link: https://lists.denx.de/pipermail/u-boot/2021-September/462006.html > Fixed: https://bugzilla.kernel.org/show_bug.cgi?id=213753 > Signed-off-by: Ilya Katsnelson <me(a)0upti.me> > Signed-off-by: Jian-Hong Pan <jhp(a)endlessos.org> > --- > The code of this patch comes from "[RFC PATCH] rpi: copy the EMMC > controller configuration from firmware-supplied DT" [1] basically. > I only add the message and some modifcation: > > * Fix the build failed error: > board/raspberrypi/rpi/rpi.c: In function 'copy_emmc_config': > board/raspberrypi/rpi/rpi.c:553:9: warning: dereferencing 'void *' pointer > 553 | *fw_value = fdt_getprop(fw_fdt, fw_emmc_node, "dma-ranges", &length); > | ^~~~~~~~~ > board/raspberrypi/rpi/rpi.c:553:19: error: invalid use of void expression > 553 | *fw_value = fdt_getprop(fw_fdt, fw_emmc_node, "dma-ranges", &length); > | ^ > make[1]: *** [scripts/Makefile.build:258: board/raspberrypi/rpi/rpi.o] Error 1 > > * Replace "EMMC" to "eMMC". > > * Replace the printf with log_[levels]. > > So, I keep "Ilya Katsnelson <me(a)0upti.me>" as the author. > > [1]: https://lists.denx.de/pipermail/u-boot/2021-September/462006.html > > board/raspberrypi/rpi/rpi.c | 63 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 63 insertions(+) > > diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c > index 00afb352bd..d7ff8e269e 100644 > --- a/board/raspberrypi/rpi/rpi.c > +++ b/board/raspberrypi/rpi/rpi.c > @@ -504,6 +504,67 @@ void *board_fdt_blob_setup(int *err) > return (void *)fw_dtb_pointer; > } > > +void copy_emmc_config(void *our_fdt) > +{ > + /* > + * As of 2021-09-28, the Pi 4 has two different revisions, one using a > + * B0 stepping of the BCM2711 SoC, and one using a C0 stepping. > + * > + * The two SoC versions have different, incompatible DMA mappings for > + * the on-board eMMC controller, which would normally make them require > + * two different DTs. > + * > + * Unfortunately for us, the different revisions don't actually _use_ > + * different DTs - instead, the proprietary stage0 bootloader reads the DT, > + * patches it in-memory, then passes the corrected DT to the OS. > + * > + * In our case, the OS is actually U-Boot, and U-Boot can choose to > + * completely disregard the firmware-supplied DT and load a custom one > + * instead, which is used by, e.g., NixOS. > + * > + * When that happens, the DT patches applied by the firmware are also > + * thrown out, which leads to BCM2711C0 boards being unable to boot > + * due to them trying to use the hardcoded DMA mappings in the DT > + * (which are for the B0 revision). > + * > + * Work around that by manually copying the DMA region setup from the > + * firmware-provided DT into whatever DT we're actually being asked > + * to load. > + */ > + void *fw_fdt = (void *)fw_dtb_pointer; > + int fw_emmc_node; > + int our_emmc_node; > + int length; > + const void *fw_value; > + int result; > + > + fw_emmc_node = fdt_path_offset(fw_fdt, "emmc2bus"); > + if (fw_emmc_node < 0) { > + log_info("RPi: Failed to find eMMC config in FW DT: %d\n", fw_emmc_node); > + return; > + } > + > + our_emmc_node = fdt_path_offset(our_fdt, "emmc2bus"); > + if (our_emmc_node < 0) { > + log_info("RPi: Failed to find eMMC config in our DT: %d\n", our_emmc_node); > + return; > + } > + > + fw_value = fdt_getprop(fw_fdt, fw_emmc_node, "dma-ranges", &length); > + if (!fw_value) { > + log_info("RPi: Failed to get eMMC DMA ranges property from FW DT: %d\n", length); > + return; > + } > + > + result = fdt_setprop(our_fdt, our_emmc_node, "dma-ranges", fw_value, length); > + if (result != 0) { > + log_warning("RPi: Failed to set eMMC DMA ranges property in our DT: %d\n", result); > + return; > + } > + > + log_debug("RPi: successfully copied FW DT eMMC configuration to our DT!\n"); > +} > + > int ft_board_setup(void *blob, struct bd_info *bd) > { > int node; > @@ -518,5 +579,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) > EFI_RESERVED_MEMORY_TYPE); > #endif > > + copy_emmc_config(blob); > + > return 0; > } > -- > 2.38.1 >

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[PATCH v7 0/8] Add MV88E6xxx DSA driver and use on gwventana
by Tim Harvey 28 Oct '22

28 Oct '22

This series adds a DSA driver for the MV88E6xxx based on drivers/net/phy/mv88e61xx and uses it in the gwventana_gw5904_defconfig. The hope is that the other three boards that use the MV88E61xx driver can move to this as well eventually so that we can remove the non-dm driver and the 4 Kconfig options it requires. The MV88E6xxx has an MDIO interface thus DM_MDIO must be used so support for a UCLASS_MDIO driver is added to the fec_mxc ethernet driver in a way that allows a fallback to the previous non DM_MDIO case as there are many boards out there using this driver that define DM_MDIO but do not have the required dt props for a DM_MDIO driver which would cause a regression. Additionally some other patches are here suggested by Vladimir: - ensure MDIO children are scanned on post-bind is needed - sanity check DSA driver required ops are present - allow DSA drivers to not require xmit/recv functions - remove unecessary xmit/recv functions from ksz9477 driver v7: - rebase on master - update commit short msg (s/MV88E61xx/MV88E6xxx) - replace inline smi_cmd* with macros using logical operators - replace bitfield_replace with logical operators for readibility - removed some unused register definitions - config switch based SERDES mode once in probe vs port_enable - rework port_enable to clean up and: - enable energy-detect for all non fixed PHY ports - configure RGMII delays based on interface type - add Vladimir's rb tag to patch 8 v6: - update commit messages - squash accidently change to mv88e6xxx driver into previous patch - remove unused dt label for cpu port - removed unnecessary semicolon - update commit msg (s/MV88E61xx/MV88E6xxx) - remove GbE from commit msg and Kconfig desc - squash accidental change from patch 7 into patch 6 - added error print on failure to read switch id - mv88e6xxx_probe: - check for switch enabled - remove unused variable enabled - remove unnecessary call to dsa_set_tagging - port_probe: - new function to configure phy features by calling phy_config - port_enable: - only enable energy-detect sensing on phy ports - add phy/cmode verification mistmatch warning - remove mv88e6xxx_fixed_port_setup() - always force link up for fixed ports - always set SERDES mode regardless of cpu port - remove unnecessary setting of CPUDEST - port_disable: - remove pointless error check - removed unnecessary priv data for mdio controller - fix indentation - change variable name for clarity v5: - fix typo in defconfig update - added support for MV88E6320 - added Fabio's rb tag v4: - use standard Linux internal MDIO dt structure - use PHY_FIXED_ID define - rename to mv88e6xxx - sort includes alphabetically - remove dsa term from function names - reduce indentation level and remove unecessary code in of probe_mdio function - rename pdev to mdev to represent mdio device v3: - fix mdios node in dt - add Vladimir's rb tag's v2: - added Ramon's rb tag's to first two patches - add patches for dsa-uclass to sanity check ops and make xmit/recv optional - fec: fix fallback for non conforming DM_MDIO dts - mv88e61xx: - rebase on v2022.07-rc2 (use ofnode_get_phy_node) - remove unused commented out fields from struct - remove unused PORT_MASK macro - remove phy from priv struct name - refactor code from original drivers/net/phy/mv88e61xx with suggestions from review to consolidate some functions into mv88e61xx_dsa_port_enable - remove unecessary skiping of disabling of CPU port - remove unecessary dev_set_parent_priv - remove unnecessary static init flag - replace debug with a dev_warn if switch device-id unsupported - remove unnecessary xmit/recv functions as we rely on the fact that only a single port is active instead of mangling packets Tested on a Gateworks GW5904 which has a Marvell 88E6176 switch hanging off the IMX6 FEC. Best Regards, Tim Tim Harvey (8): net: mdio-uclass: scan for dm mdio children on post-bind net: dsa: move cpu port probe to dsa_post_probe net: dsa: ensure dsa driver has proper ops net: dsa: allow rcv() and xmit() to be optional net: ksz9477: remove unnecessary xmit and recv functions net: fec: add support for DM_MDIO net: add MV88E6xxx DSA driver board: gw_ventana: enable MV88E61XX DSA support arch/arm/dts/imx6qdl-gw5904.dtsi | 32 +- board/gateworks/gw_ventana/gw_ventana.c | 50 +- configs/gwventana_gw5904_defconfig | 7 +- drivers/net/Kconfig | 7 + drivers/net/Makefile | 1 + drivers/net/fec_mxc.c | 90 ++- drivers/net/ksz9477.c | 23 - drivers/net/mv88e6xxx.c | 795 ++++++++++++++++++++++++ net/dsa-uclass.c | 55 +- net/mdio-uclass.c | 4 + 10 files changed, 992 insertions(+), 72 deletions(-) create mode 100644 drivers/net/mv88e6xxx.c -- 2.25.1

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[PATCH] lib: fix buggy strcmp and strncmp
by Rasmus Villemoes 27 Oct '22

27 Oct '22

There are two problems with both strcmp and strncmp: (1) The C standard is clear that the contents should be compared as "unsigned char": The sign of a nonzero value returned by the comparison functions memcmp, strcmp, and strncmp is determined by the sign of the difference between the values of the first pair of characters (both interpreted as unsigned char) that differ in the objects being compared. (2) The difference between two char (or unsigned char) values can range from -255 to +255; so that's (due to integer promotion) the range of values we could get in the *cs-*ct expressions, but when that is then shoe-horned into an 8-bit quantity the sign may of course change. The impact is somewhat limited by the way these functions are used in practice: - Most of the time, one is only interested in equality (or for strncmp, "starts with"), and the existing functions do correctly return 0 if and only if the strings are equal [for strncmp, up to the given bound]. - Also most of the time, the strings being compared only consist of ASCII characters, i.e. have values in the range [0, 127], and in that case it doesn't matter if they are interpreted as signed or unsigned char, and the possible difference range is bounded to [-127, 127] which does fit the signed char. For size, one could implement strcmp() in terms of strncmp() - just make it "return strncmp(a, b, (size_t)-1);". However, performance of strcmp() does matter somewhat, since it is used all over when parsing and matching DT nodes and properties, so let's find some other place to save those ~30 bytes. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- Please double- and triple-check before applying. I've tested these against my libc's strcmp() and strncmp() for thousands of random strings, but I may very well have messed up when copy-pasting back to lib/string.c. lib/string.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/lib/string.c b/lib/string.c index 78bd65c413..ecea755f40 100644 --- a/lib/string.c +++ b/lib/string.c @@ -206,16 +206,20 @@ size_t strlcat(char *dest, const char *src, size_t size) * @cs: One string * @ct: Another string */ -int strcmp(const char * cs,const char * ct) +int strcmp(const char *cs, const char *ct) { - register signed char __res; + int ret; while (1) { - if ((__res = *cs - *ct++) != 0 || !*cs++) + unsigned char a = *cs++; + unsigned char b = *ct++; + + ret = a - b; + if (ret || !b) break; } - return __res; + return ret; } #endif @@ -226,17 +230,20 @@ int strcmp(const char * cs,const char * ct) * @ct: Another string * @count: The maximum number of bytes to compare */ -int strncmp(const char * cs,const char * ct,size_t count) +int strncmp(const char *cs, const char *ct, size_t count) { - register signed char __res = 0; + int ret = 0; + + while (count--) { + unsigned char a = *cs++; + unsigned char b = *ct++; - while (count) { - if ((__res = *cs - *ct++) != 0 || !*cs++) + ret = a - b; + if (ret || !b) break; - count--; } - return __res; + return ret; } #endif -- 2.37.2

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[PATCH v2] imx: imx8qm: imx8qm_mek switch to binman
by Oliver Graute 27 Oct '22

27 Oct '22

Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> --- arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 2 ++ arch/arm/mach-imx/imx8/Kconfig | 1 + board/freescale/imx8qm_mek/README | 2 +- configs/imx8qm_2ek_defconfig | 2 ++ 4 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index a95209e141..eefdccf992 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright 2018, 2021 NXP */ +#include "imx8qm-u-boot.dtsi" + &{/imx8qm-pm} { u-boot,dm-spl; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 23a7fcf361..4ccbabf506 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -68,6 +68,7 @@ config TARGET_GIEDI config TARGET_IMX8QM_MEK bool "Support i.MX8QM MEK board" + select BINMAN select BOARD_LATE_INIT select IMX8QM select FSL_CAAM diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README index 570ed7e210..b1a4c6cc82 100644 --- a/board/freescale/imx8qm_mek/README +++ b/board/freescale/imx8qm_mek/README @@ -40,7 +40,7 @@ And copy the following firmwares to U-Boot folder: Build U-Boot ============ $ make imx8qm_mek_defconfig -$ make flash.bin +$ make Flash the binary into the SD card ================================= diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index b973b809be..25b51cf1ec 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -23,6 +23,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=3 -- 2.17.1

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[PATCH v1] imx: imx8qm: imx8qm_mek switch to binman
by Oliver Graute 27 Oct '22

27 Oct '22

Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> --- arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 2 ++ arch/arm/mach-imx/imx8/Kconfig | 1 + board/freescale/imx8qm_mek/README | 2 +- board/freescale/imx8qm_mek/imximage.cfg | 2 +- configs/imx8qm_mek_defconfig | 2 ++ 5 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index a95209e141..eefdccf992 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -3,6 +3,8 @@ * Copyright 2018, 2021 NXP */ +#include "imx8qm-u-boot.dtsi" + &{/imx8qm-pm} { u-boot,dm-spl; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 23a7fcf361..4ccbabf506 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -68,6 +68,7 @@ config TARGET_GIEDI config TARGET_IMX8QM_MEK bool "Support i.MX8QM MEK board" + select BINMAN select BOARD_LATE_INIT select IMX8QM select FSL_CAAM diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README index 570ed7e210..b1a4c6cc82 100644 --- a/board/freescale/imx8qm_mek/README +++ b/board/freescale/imx8qm_mek/README @@ -40,7 +40,7 @@ And copy the following firmwares to U-Boot folder: Build U-Boot ============ $ make imx8qm_mek_defconfig -$ make flash.bin +$ make Flash the binary into the SD card ================================= diff --git a/board/freescale/imx8qm_mek/imximage.cfg b/board/freescale/imx8qm_mek/imximage.cfg index 71612678c9..46ca3bf817 100644 --- a/board/freescale/imx8qm_mek/imximage.cfg +++ b/board/freescale/imx8qm_mek/imximage.cfg @@ -5,7 +5,7 @@ /* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 +BOOT_FROM sd /* SoC type IMX8QM */ SOC_TYPE IMX8QM /* Append seco container image */ diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index b973b809be..25b51cf1ec 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -23,6 +23,8 @@ CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTDELAY=3 -- 2.17.1

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[PATCH 00/11] AM68 SK: Add initial support for AM68 Starter Kit
by Sinthu Raja 27 Oct '22

27 Oct '22

From: Sinthu Raja <sinthu.raja(a)ti.com> AM68 Starter Kit (SK) is a low cost, small form factor board designed for TI’s J721S2/AM68 SoC. TI’s J721S2/AM68 SoC comprises of dual core A72, high performance vision accelerators, hardware accelerators, latest C71x DSP, high bandwidth real-time IPs for capture and display. The SoC is power optimized to provide best in class performance for industrial and automotive applications. Refer below link to J721S2/AM68 Technical Reference Manual for further details: http://www.ti.com/lit/pdf/spruj28 AM68 SK supports the following interfaces: * 16 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x1 USB 3.1 Type-C port * x2 USB 3.1 Type-A ports * x1 PCIe M.2 M Key * 512 Mbit OSPI flash * x2 CSI2 Camera interface (RPi and TI Camera connector) * 40-pin Raspberry Pi GPIO header This series of patch add initial support for AM68 starter kit. Design files can be referrred from https://www.ti.com/lit/zip/SPRR463 Sinthu Raja (11): configs: j721s2_evm_r5: Enable support for building multiple dtbs into FIT configs: j721s2_evm_a72: Enable support for building multiple dtbs into FIT configs: j721s2_evm: Enable configs to store env in MMC FAT partition board: ti: j721s2: Add support to update board_name for am68-sk board: ti: j721s2: Enable support for reading EEPROM at next alternate address board: ti: j721s2: Add support for detecting multiple device trees arm: j721s2: Add support for selecting DT based on EEPROM arm: dts: Add initial support for AM68 Starter Kit System on Module arm: dts: Add support for A72 specific AM68 Starter Kit Base Board arm: dts: k3-am68-sk: Add r5 specific dt support include: configs: Update env for selecting right dtb arch/arm/dts/Makefile | 4 +- .../arm/dts/k3-am68-sk-base-board-u-boot.dtsi | 216 ++++++++++ arch/arm/dts/k3-am68-sk-base-board.dts | 395 ++++++++++++++++++ arch/arm/dts/k3-am68-sk-r5-base-board.dts | 226 ++++++++++ arch/arm/dts/k3-am68-sk-som.dtsi | 167 ++++++++ arch/arm/mach-k3/j721s2_init.c | 59 +++ board/ti/j721s2/evm.c | 32 +- configs/j721s2_evm_a72_defconfig | 5 +- configs/j721s2_evm_r5_defconfig | 4 + include/configs/j721s2_evm.h | 4 + 10 files changed, 1105 insertions(+), 7 deletions(-) create mode 100644 arch/arm/dts/k3-am68-sk-base-board-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am68-sk-base-board.dts create mode 100644 arch/arm/dts/k3-am68-sk-r5-base-board.dts create mode 100644 arch/arm/dts/k3-am68-sk-som.dtsi -- 2.36.1

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[PATCH v1] spi: nuvoton: add NPCM PSPI controller driver
by Jim Liu 27 Oct '22

27 Oct '22

Add Nuvoton NPCM BMC Peripheral SPI controller driver. NPCM750 include two general-purpose SPI interface. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/npcm_pspi.c | 226 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 232 insertions(+) create mode 100644 drivers/spi/npcm_pspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1e515cb2b..4e4e05f849 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -289,6 +289,11 @@ config NPCM_FIU_SPI This enables support for the Flash Interface Unit SPI controller in master mode. +config NPCM_PSPI + bool "PSPI driver for Nuvoton NPCM SoC" + help + PSPI driver for NPCM SoC + config NXP_FSPI bool "NXP FlexSPI driver" depends on SPI_MEM diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06e81b465b..1b843636bc 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o +obj-$(CONFIG_NPCM_PSPI) += npcm_pspi.o obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c new file mode 100644 index 0000000000..bd9ac65411 --- /dev/null +++ b/drivers/spi/npcm_pspi.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology. + */ + +#include <common.h> +#include <dm.h> +#include <spi.h> +#include <clk.h> +#include <asm/gpio.h> +#include <linux/iopoll.h> + +#define MAX_DIV 127 + +/* Register offsets */ +#define PSPI_DATA 0 +#define PSPI_CTL1 2 +#define PSPI_STAT 4 + +/* PSPI_CTL1 fields */ +#define PSPI_CTL1_SPIEN BIT(0) +#define PSPI_CTL1_SCM BIT(7) +#define PSPI_CTL1_SCIDL BIT(8) +#define PSPI_CTL1_SCDV_MASK GENMASK(15, 9) +#define PSPI_CTL1_SCDV_SHIFT 9 + +/* PSPI_STAT fields */ +#define PSPI_STAT_BSY BIT(0) +#define PSPI_STAT_RBF BIT(1) + +struct npcm_pspi_priv { + void __iomem *base; + struct clk clk; + struct gpio_desc cs_gpio; + u32 max_hz; +}; + +static inline void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + + dm_gpio_set_value(&priv->cs_gpio, 0); +} + +static inline void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + + dm_gpio_set_value(&priv->cs_gpio, 1); +} + +static inline void npcm_pspi_enable(struct npcm_pspi_priv *priv) +{ + u16 val; + + val = readw(priv->base + PSPI_CTL1); + val |= PSPI_CTL1_SPIEN; + writew(val, priv->base + PSPI_CTL1); +} + +static inline void npcm_pspi_disable(struct npcm_pspi_priv *priv) +{ + u16 val; + + val = readw(priv->base + PSPI_CTL1); + val &= ~PSPI_CTL1_SPIEN; + writew(val, priv->base + PSPI_CTL1); +} + +static int npcm_pspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + void __iomem *base = priv->base; + const u8 *tx = dout; + u8 *rx = din; + u32 bytes = bitlen / 8; + u8 tmp; + u32 val; + int i, ret = 0; + + npcm_pspi_enable(priv); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + for (i = 0; i < bytes; i++) { + /* Making sure we can write */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + !(val & PSPI_STAT_BSY), + 1000000); + if (ret < 0) + break; + + if (tx) + writeb(*tx++, base + PSPI_DATA); + else + writeb(0, base + PSPI_DATA); + + /* Wait till write completed */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + !(val & PSPI_STAT_BSY), + 1000000); + if (ret < 0) + break; + + /* Wait till read buffer full */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + (val & PSPI_STAT_RBF), + 1000000); + if (ret < 0) + break; + + tmp = readb(base + PSPI_DATA); + if (rx) + *rx++ = tmp; + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + npcm_pspi_disable(priv); + + return ret; +} + +static int npcm_pspi_set_speed(struct udevice *bus, uint speed) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + ulong apb_clock; + u32 divisor; + u16 val; + + apb_clock = clk_get_rate(&priv->clk); + if (!apb_clock) + return -EINVAL; + + if (speed > priv->max_hz) + speed = priv->max_hz; + + divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed) - 1); + if (divisor > MAX_DIV) + divisor = MAX_DIV; + + val = readw(priv->base + PSPI_CTL1); + val &= ~PSPI_CTL1_SCDV_MASK; + val |= divisor << PSPI_CTL1_SCDV_SHIFT; + writew(val, priv->base + PSPI_CTL1); + + debug("%s: apb_clock=%lu speed=%d divisor=%u\n", + __func__, apb_clock, speed, divisor); + + return 0; +} + +static int npcm_pspi_set_mode(struct udevice *bus, uint mode) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + u16 pspi_mode, val; + + switch (mode & (SPI_CPOL | SPI_CPHA)) { + case SPI_MODE_0: + pspi_mode = 0; + break; + case SPI_MODE_1: + pspi_mode = PSPI_CTL1_SCM; + break; + case SPI_MODE_2: + pspi_mode = PSPI_CTL1_SCIDL; + break; + case SPI_MODE_3: + pspi_mode = PSPI_CTL1_SCIDL | PSPI_CTL1_SCM; + break; + default: + break; + } + + val = readw(priv->base + PSPI_CTL1); + val &= ~(PSPI_CTL1_SCIDL | PSPI_CTL1_SCM); + val |= pspi_mode; + writew(val, priv->base + PSPI_CTL1); + + return 0; +} + +static int npcm_pspi_probe(struct udevice *bus) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + int node = dev_of_offset(bus); + int ret; + + ret = clk_get_by_index(bus, 0, &priv->clk); + if (ret < 0) + return ret; + + priv->base = dev_read_addr_ptr(bus); + priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); + gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0, + &priv->cs_gpio, GPIOD_IS_OUT); + + return 0; +} + +static const struct dm_spi_ops npcm_pspi_ops = { + .xfer = npcm_pspi_xfer, + .set_speed = npcm_pspi_set_speed, + .set_mode = npcm_pspi_set_mode, +}; + +static const struct udevice_id npcm_pspi_ids[] = { + { .compatible = "nuvoton,npcm845-pspi"}, + { .compatible = "nuvoton,npcm750-pspi"}, + { } +}; + +U_BOOT_DRIVER(npcm_pspi) = { + .name = "npcm_pspi", + .id = UCLASS_SPI, + .of_match = npcm_pspi_ids, + .ops = &npcm_pspi_ops, + .priv_auto = sizeof(struct npcm_pspi_priv), + .probe = npcm_pspi_probe, +}; -- 2.17.1

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Re: [PATCH v1] spi: nuvoton: add NPCM PSPI controller driver
by Jim Liu 27 Oct '22

27 Oct '22

Hi Jagan My upstream topic status is Awaiting Upstream. but now Meta needs to use this driver. What could I do to make it merge fast? Best regards, Jim On Thu, Oct 27, 2022 at 2:57 PM JJLIU0(a)nuvoton.com <JJLIU0(a)nuvoton.com> wrote: > > fyi > > -----Original Message----- > From: Jim Liu <jim.t90615(a)gmail.com> > Sent: Tuesday, May 31, 2022 6:14 PM > To: CS20 JJLiu0 <JJLIU0(a)nuvoton.com>; jagan(a)amarulasolutions.com; CS20 YSChu <YSCHU(a)nuvoton.com>; CS20 KWLiu <KWLIU(a)nuvoton.com> > Cc: u-boot(a)lists.denx.de > Subject: [PATCH v1] spi: nuvoton: add NPCM PSPI controller driver > > Add Nuvoton NPCM BMC Peripheral SPI controller driver. > NPCM750 include two general-purpose SPI interface. > > Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> > --- > drivers/spi/Kconfig | 5 + > drivers/spi/Makefile | 1 + > drivers/spi/npcm_pspi.c | 226 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 232 insertions(+) > create mode 100644 drivers/spi/npcm_pspi.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1e515cb2b..4e4e05f849 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -289,6 +289,11 @@ config NPCM_FIU_SPI > This enables support for the Flash Interface Unit SPI controller > in master mode. > > +config NPCM_PSPI > + bool "PSPI driver for Nuvoton NPCM SoC" > + help > + PSPI driver for NPCM SoC > + > config NXP_FSPI > bool "NXP FlexSPI driver" > depends on SPI_MEM > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06e81b465b..1b843636bc 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -48,6 +48,7 @@ obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o > obj-$(CONFIG_MXC_SPI) += mxc_spi.o > obj-$(CONFIG_MXS_SPI) += mxs_spi.o > obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o > +obj-$(CONFIG_NPCM_PSPI) += npcm_pspi.o > obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o > obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o > obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c new file mode 100644 index 0000000000..bd9ac65411 > --- /dev/null > +++ b/drivers/spi/npcm_pspi.c > @@ -0,0 +1,226 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2021 Nuvoton Technology. > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <spi.h> > +#include <clk.h> > +#include <asm/gpio.h> > +#include <linux/iopoll.h> > + > +#define MAX_DIV 127 > + > +/* Register offsets */ > +#define PSPI_DATA 0 > +#define PSPI_CTL1 2 > +#define PSPI_STAT 4 > + > +/* PSPI_CTL1 fields */ > +#define PSPI_CTL1_SPIEN BIT(0) > +#define PSPI_CTL1_SCM BIT(7) > +#define PSPI_CTL1_SCIDL BIT(8) > +#define PSPI_CTL1_SCDV_MASK GENMASK(15, 9) > +#define PSPI_CTL1_SCDV_SHIFT 9 > + > +/* PSPI_STAT fields */ > +#define PSPI_STAT_BSY BIT(0) > +#define PSPI_STAT_RBF BIT(1) > + > +struct npcm_pspi_priv { > + void __iomem *base; > + struct clk clk; > + struct gpio_desc cs_gpio; > + u32 max_hz; > +}; > + > +static inline void spi_cs_activate(struct udevice *dev) { > + struct udevice *bus = dev->parent; > + struct npcm_pspi_priv *priv = dev_get_priv(bus); > + > + dm_gpio_set_value(&priv->cs_gpio, 0); > +} > + > +static inline void spi_cs_deactivate(struct udevice *dev) { > + struct udevice *bus = dev->parent; > + struct npcm_pspi_priv *priv = dev_get_priv(bus); > + > + dm_gpio_set_value(&priv->cs_gpio, 1); > +} > + > +static inline void npcm_pspi_enable(struct npcm_pspi_priv *priv) { > + u16 val; > + > + val = readw(priv->base + PSPI_CTL1); > + val |= PSPI_CTL1_SPIEN; > + writew(val, priv->base + PSPI_CTL1); > +} > + > +static inline void npcm_pspi_disable(struct npcm_pspi_priv *priv) { > + u16 val; > + > + val = readw(priv->base + PSPI_CTL1); > + val &= ~PSPI_CTL1_SPIEN; > + writew(val, priv->base + PSPI_CTL1); > +} > + > +static int npcm_pspi_xfer(struct udevice *dev, unsigned int bitlen, > + const void *dout, void *din, unsigned long flags) { > + struct udevice *bus = dev->parent; > + struct npcm_pspi_priv *priv = dev_get_priv(bus); > + void __iomem *base = priv->base; > + const u8 *tx = dout; > + u8 *rx = din; > + u32 bytes = bitlen / 8; > + u8 tmp; > + u32 val; > + int i, ret = 0; > + > + npcm_pspi_enable(priv); > + > + if (flags & SPI_XFER_BEGIN) > + spi_cs_activate(dev); > + > + for (i = 0; i < bytes; i++) { > + /* Making sure we can write */ > + ret = readb_poll_timeout(base + PSPI_STAT, val, > + !(val & PSPI_STAT_BSY), > + 1000000); > + if (ret < 0) > + break; > + > + if (tx) > + writeb(*tx++, base + PSPI_DATA); > + else > + writeb(0, base + PSPI_DATA); > + > + /* Wait till write completed */ > + ret = readb_poll_timeout(base + PSPI_STAT, val, > + !(val & PSPI_STAT_BSY), > + 1000000); > + if (ret < 0) > + break; > + > + /* Wait till read buffer full */ > + ret = readb_poll_timeout(base + PSPI_STAT, val, > + (val & PSPI_STAT_RBF), > + 1000000); > + if (ret < 0) > + break; > + > + tmp = readb(base + PSPI_DATA); > + if (rx) > + *rx++ = tmp; > + } > + > + if (flags & SPI_XFER_END) > + spi_cs_deactivate(dev); > + > + npcm_pspi_disable(priv); > + > + return ret; > +} > + > +static int npcm_pspi_set_speed(struct udevice *bus, uint speed) { > + struct npcm_pspi_priv *priv = dev_get_priv(bus); > + ulong apb_clock; > + u32 divisor; > + u16 val; > + > + apb_clock = clk_get_rate(&priv->clk); > + if (!apb_clock) > + return -EINVAL; > + > + if (speed > priv->max_hz) > + speed = priv->max_hz; > + > + divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed) - 1); > + if (divisor > MAX_DIV) > + divisor = MAX_DIV; > + > + val = readw(priv->base + PSPI_CTL1); > + val &= ~PSPI_CTL1_SCDV_MASK; > + val |= divisor << PSPI_CTL1_SCDV_SHIFT; > + writew(val, priv->base + PSPI_CTL1); > + > + debug("%s: apb_clock=%lu speed=%d divisor=%u\n", > + __func__, apb_clock, speed, divisor); > + > + return 0; > +} > + > +static int npcm_pspi_set_mode(struct udevice *bus, uint mode) { > + struct npcm_pspi_priv *priv = dev_get_priv(bus); > + u16 pspi_mode, val; > + > + switch (mode & (SPI_CPOL | SPI_CPHA)) { > + case SPI_MODE_0: > + pspi_mode = 0; > + break; > + case SPI_MODE_1: > + pspi_mode = PSPI_CTL1_SCM; > + break; > + case SPI_MODE_2: > + pspi_mode = PSPI_CTL1_SCIDL; > + break; > + case SPI_MODE_3: > + pspi_mode = PSPI_CTL1_SCIDL | PSPI_CTL1_SCM; > + break; > + default: > + break; > + } > + > + val = readw(priv->base + PSPI_CTL1); > + val &= ~(PSPI_CTL1_SCIDL | PSPI_CTL1_SCM); > + val |= pspi_mode; > + writew(val, priv->base + PSPI_CTL1); > + > + return 0; > +} > + > +static int npcm_pspi_probe(struct udevice *bus) { > + struct npcm_pspi_priv *priv = dev_get_priv(bus); > + int node = dev_of_offset(bus); > + int ret; > + > + ret = clk_get_by_index(bus, 0, &priv->clk); > + if (ret < 0) > + return ret; > + > + priv->base = dev_read_addr_ptr(bus); > + priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); > + gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0, > + &priv->cs_gpio, GPIOD_IS_OUT); > + > + return 0; > +} > + > +static const struct dm_spi_ops npcm_pspi_ops = { > + .xfer = npcm_pspi_xfer, > + .set_speed = npcm_pspi_set_speed, > + .set_mode = npcm_pspi_set_mode, > +}; > + > +static const struct udevice_id npcm_pspi_ids[] = { > + { .compatible = "nuvoton,npcm845-pspi"}, > + { .compatible = "nuvoton,npcm750-pspi"}, > + { } > +}; > + > +U_BOOT_DRIVER(npcm_pspi) = { > + .name = "npcm_pspi", > + .id = UCLASS_SPI, > + .of_match = npcm_pspi_ids, > + .ops = &npcm_pspi_ops, > + .priv_auto = sizeof(struct npcm_pspi_priv), > + .probe = npcm_pspi_probe, > +}; > -- > 2.17.1 > > ________________________________ > ________________________________ > The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

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