October 2022 - U-Boot

[PATCH] Revert "pinctrl: zynqmp: Add support for output-enable and bias-high-impedance"
by Michal Simek 25 Oct '22

25 Oct '22

This reverts commit 123462e5e534d6e17b1b7d2006734bbe54b03e0a. On systems with older PMUFW using these pinctrl properties can cause system hang because there is missing feature autodetection. When it is implemented support for these two properties should go back. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- https://lore.kernel.org/all/9b7fac69-265e-52f2-21e4-83d9da0f257b@amd.com/ --- drivers/pinctrl/pinctrl-zynqmp.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 52d428f566fc..7c5a02db1b98 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -467,10 +467,6 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, pin); break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - param = PM_PINCTRL_CONFIG_TRI_STATE; - arg = PM_PINCTRL_TRI_STATE_ENABLE; - ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); - break; case PIN_CONFIG_LOW_POWER_MODE: /* * This cases are mentioned in dts but configurable @@ -479,11 +475,6 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, */ ret = 0; break; - case PIN_CONFIG_OUTPUT_ENABLE: - param = PM_PINCTRL_CONFIG_TRI_STATE; - arg = PM_PINCTRL_TRI_STATE_DISABLE; - ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); - break; default: dev_warn(dev, "unsupported configuration parameter '%u'\n", param); -- 2.36.1

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[PATCH] arm64: zynqmp: Disable watchdog by default for virt platform
by Michal Simek 25 Oct '22

25 Oct '22

Disable watchdog based on request in past that not all Linux rootfs have proper utilities ready to service it. Enable it if your rootfs have proper watchdog handling. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- configs/xilinx_zynqmp_virt_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 150a4d43bc86..9765116a4f58 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -83,7 +83,6 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y -CONFIG_CMD_WDT=y CONFIG_BOOTP_MAY_FAIL=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_TFTPPUT=y @@ -232,7 +231,6 @@ CONFIG_SPLASH_SCREEN=y CONFIG_BMP_16BPP=y CONFIG_BMP_24BPP=y CONFIG_BMP_32BPP=y -CONFIG_WDT=y CONFIG_PANIC_HANG=y CONFIG_TPM=y CONFIG_SPL_GZIP=y -- 2.36.1

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[PATCH] ARM: zynq: DT: Enable all FCLKs by default
by Michal Simek 25 Oct '22

25 Oct '22

From: Christian Kohn <christian.kohn(a)xilinx.com> The fclk-enable property is set to 0 which disables all FCLKs. Enable all FCLKs so they can be used as clock sources in the programmable logic. Signed-off-by: Christian Kohn <christian.kohn(a)xilinx.com> Acked-by: Soren Brinkmann <soren.brinkmann(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynq-7000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index edc147d63f1e..f72ef526f057 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -340,7 +340,7 @@ u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0>; + fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", -- 2.36.1

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[PATCH] microblaze: Make extended addressing support default
by Michal Simek 25 Oct '22

25 Oct '22

From: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Axi qspi controller supports 32-bit & 24-bit addressing modes for micron, macronix & spansion flash parts. But for winbond flashes it only supports 24-bit addressing mode. Enable CONFIG_SPI_FLASH_BAR to use extended addressing mode to make 32-bit addressing mode work on all flashes. Signed-off-by: T Karthik Reddy <t.karthik.reddy(a)xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- configs/microblaze-generic_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 0f650e59073f..c993cca3c5cb 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -80,6 +80,7 @@ CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_SECT=2048 +CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y -- 2.36.1

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[PATCH] arm64: versal: Add missing BOOT_MODE_POR_X macros
by Michal Simek 25 Oct '22

25 Oct '22

The commit bf8dae5fcf40 ("spi: cadence-qspi: reset qspi flash for versal platform") added reference to BOOT_MODE_POR_X but forget to add them. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/mach-versal/include/mach/hardware.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h index 000af974e867..aa41155e9dc7 100644 --- a/arch/arm/mach-versal/include/mach/hardware.h +++ b/arch/arm/mach-versal/include/mach/hardware.h @@ -97,3 +97,5 @@ struct crp_regs { #define MIO_PIN_12 0xF1060030 #define BANK0_OUTPUT 0xF1020040 #define BANK0_TRI 0xF1060200 +#define BOOT_MODE_POR_0 0xF1020204 +#define BOOT_MODE_POR_1 0xF1020208 -- 2.36.1

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[PATCH] ARM: dts: imx8mq-kontron-pitx-imx8m: Remove off-on-delay-us property
by Heiko Thiery 25 Oct '22

25 Oct '22

U-Boot is not able to store the environment variables in the SD card. Remove the off-on-delay-us property to fix the regression. Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- The same change is done in the linux dts file. arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts b/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts index a91c136797..21442e04a6 100644 --- a/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts +++ b/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts @@ -51,7 +51,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <20000>; enable-active-high; }; }; -- 2.30.2

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[PATCH 016/347] FogBugz #516535: Fix QSPI write issues
by Jit Loon Lim 25 Oct '22

25 Oct '22

From: Chee Hong Ang <chee.hong.ang(a)intel.com> QSPI driver perform chip select on every flash read/write access. The driver need to disable/enable the QSPI controller while performing chip select. This may cause some data lost especially the QSPI controller is configured to run at slower speed as it may take longer time to access the flash device. This patch prevent the driver from disable/enable the QSPI controller too soon and inadvertently halting any ongoing flash read/write access by ensuring the QSPI controller is always in idle mode after each read/write access. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> --- drivers/spi/cadence_qspi_apb.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 2cdf4c9c9f..5e03495f45 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -858,13 +858,9 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat, writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + CQSPI_REG_INDIRECTRD); - /* Check indirect done status */ - ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD, - CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0); - if (ret) { - printf("Indirect read clear completion error (%i)\n", ret); - goto failrd; - } + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; return 0; @@ -1031,6 +1027,11 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat, if (bounce_buf) free(bounce_buf); + + /* Wait til QSPI is idle */ + if (!cadence_qspi_wait_idle(plat->regbase)) + return -EIO; + return 0; failwr: -- 2.25.1

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Re: question about uboot mt7620 RAM_VERSION
by Stefan Roese 25 Oct '22

25 Oct '22

Hi Kang-sen, On 24.10.22 19:58, Kang-sen Lu wrote: > I am wondering if you have read my reply on 10/18. It is very strange to > find that unless I had uboot to do a saveenv, the RAM_VERSION uboot.bin > would not run properly in DRAM. Frankly, I don't really understand this message. It's not clear to me, what you are doing and what is working and what is failing. I thought you were trying to boot the current mainline U-Boot RAM version u-boot.bin. If yes, which build target did you use? What does it show on the serial console? Thanks, Stefan > Thanks. > > Kang-sen > > On Tue, Oct 18, 2022 at 10:05 AM Kang-sen Lu <klu(a)waav.com > <mailto:klu@waav.com>> wrote: > > Hi, Stefan: > > Thanks for your reply. > > The uboot in the zbtlink mt7620 router has the signatures follows: > > U-Boot 1.1.3 (Nov 9 2016 - 15:34:50) > > SoC:MediaTek MT7620 > DRAM: Memory Testing..131072K OK. is 128 MB > relocate_code Pointer at: 87fb0000 > enable ephy clock...done. rf reg 29 = 5 > SSC disabled. > spi_wait_nsec: 29 > spi device id: ef 40 18 0 0 (40180000) > Flash: W25Q128BV > > I would like to share my strange experience about RAM version uboot > for mt7620. By pure luck, I found that when I tried to load a newly > built uboot with startup menu option 8, unless I change the > filename, say, from uboot.bin to uboot1.bin, the newly loaded uboot > would not startup properly in RAM. > > I don't have the knowledge to find out why this variable "modifies" > to be none-zero is so important to the execution of uboot in RAM. > Maybe some expert in this group can easily figure that out. > > Thanks. > > Kang-sen > > On Tue, Oct 18, 2022 at 7:53 AM Stefan Roese <sr(a)denx.de > <mailto:sr@denx.de>> wrote: > > Hi Kang-sen, > > (added Weijie Gao to Cc) > > On 17.10.22 14:11, Kang-sen Lu wrote: > > I am building uboot.bin for mt7620 router. > > > > I used start menu option 8, a hidden one choice, to load > uboot.bin through > > tftp. > > > > The tftp transfer is OK. But when the new uboot starts, it hang. > > So which mainline U-Boot build target did you use? Don't you see > any output on the serial console at all? > > > I am wondering if the RAM_VERSION for mt7620 still works. > > In mainline U-Boot this is usually handled this way. The SPL U-Boot > version is responsible for the low-level HW init, like DRAM/DDR init > etc. It's hard to impossible to chainload this SPL part from a > running U-Boot version. > > The "RAM_VERSION" is usually the main U-Boot proper image > "u-boot.bin". > So in general you are using the correct file here. Even though I > have > not idea, if the build target is correct for your "mt7620 router". > > Thanks, > Stefan > Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr(a)denx.de

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[PATCH] imx: spl: Add weak reset_cpu()
by Jun Nie 25 Oct '22

25 Oct '22

Add weak reset_cpu() to reduce redundant code. And it ease the new platforms that only need a empty function to pass build without below compiling failure. arch/arm/lib/reset.o: In function `do_reset': /git/u-boot/arch/arm/lib/reset.c:42: undefined reference to `reset_cpu' make[1]: *** [scripts/Makefile.spl:526: spl/u-boot-spl] Error 1 make: *** [Makefile:2087: spl/u-boot-spl] Error 2 Signed-off-by: Jun Nie <jun.nie(a)linaro.org> --- arch/arm/mach-imx/spl.c | 4 ++++ board/ronetix/imx7-cm/spl.c | 4 ---- board/technexion/pico-imx6ul/spl.c | 4 ---- board/technexion/pico-imx7d/spl.c | 4 ---- board/toradex/apalis_imx6/apalis_imx6.c | 4 ---- board/toradex/colibri_imx6/colibri_imx6.c | 4 ---- 6 files changed, 4 insertions(+), 20 deletions(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index ef00969a5e..6abbdb8909 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -388,3 +388,7 @@ void *spl_load_simple_fit_fix_load(const void *fit) return (void *)new; } + +__weak void reset_cpu(void) +{ +} diff --git a/board/ronetix/imx7-cm/spl.c b/board/ronetix/imx7-cm/spl.c index d36f734e49..864e95b187 100644 --- a/board/ronetix/imx7-cm/spl.c +++ b/board/ronetix/imx7-cm/spl.c @@ -115,10 +115,6 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } -void reset_cpu(void) -{ -} - #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ PAD_CTL_HYS | PAD_CTL_PUE | \ PAD_CTL_PUS_PU47KOHM) diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c index 251f5a1b7d..df01b5f8b5 100644 --- a/board/technexion/pico-imx6ul/spl.c +++ b/board/technexion/pico-imx6ul/spl.c @@ -147,10 +147,6 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } -void reset_cpu(void) -{ -} - #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index df5f058577..75d6aa8445 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -127,10 +127,6 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } -void reset_cpu(void) -{ -} - #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 8d2642f25d..b59d7cceea 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -1056,10 +1056,6 @@ int board_fit_config_name_match(const char *name) } #endif -void reset_cpu(void) -{ -} - #endif /* CONFIG_SPL_BUILD */ static struct mxc_serial_plat mxc_serial_plat = { diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index ab2ab587ff..261e46bc35 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -1116,10 +1116,6 @@ int board_fit_config_name_match(const char *name) } #endif -void reset_cpu(void) -{ -} - #endif /* CONFIG_SPL_BUILD */ static struct mxc_serial_plat mxc_serial_plat = { -- 2.25.1

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[PATCH v4 0/7] eficonfig: add UEFI Secure Boot key maintenance interface
by Masahisa Kojima 25 Oct '22

25 Oct '22

This series adds the UEFI Secure Boot key maintenance interface to the eficonfig command. User can enroll and delete the PK, KEK, db and dbx. Source code can be cloned with: $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git -b kojima/eficonfig_sbkey_v4 I'm aware of Simon's refactoring for common/menu.c, but this series is based on the current U-Boot/master. [Major Changes] - add menu entry accessor with '&' followed by title - add CONFIG_EFI_MM_COMM_TEE dependency Masahisa Kojima (7): eficonfig: refactor eficonfig_select_file_handler() eficonfig: expose append entry function eficonfig: add direct menu entry access mode eficonfig: add direct menu entry access in change boot order eficonfig: add UEFI Secure Boot Key enrollment interface eficonfig: add "Show/Delete Signature Database" menu entry test/py: eficonfig: use direct menu entry access mode cmd/Makefile | 5 + cmd/eficonfig.c | 331 ++++++-- cmd/eficonfig_sbkey.c | 751 ++++++++++++++++++ common/menu.c | 3 + include/efi_config.h | 13 + include/menu.h | 1 + .../py/tests/test_eficonfig/test_eficonfig.py | 178 ++--- 7 files changed, 1089 insertions(+), 193 deletions(-) create mode 100644 cmd/eficonfig_sbkey.c -- 2.17.1

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