August 2021 - U-Boot

[PATCH] xilinx: zynqmp: Enable stack relocation to DDR
by Michal Simek 27 Aug '21

27 Aug '21

There is no space in OCM for SPL stack because the space in OCM is occupied by TF-A. That's why move relocate stack to DDR to 0x18000000 address and also enable SPL_SIZE_LIMIT not to be more then 0xfffea000 which is default address for TFA. It is good to summarize current DDR usage in SPL flow. 0-0x80000 is used for BSS (CONFIG_SPL_BSS_START_ADDR, CONFIG_SPL_BSS_MAX_SIZE) 0x100000 is used for DTB passing address (CONFIG_XILINX_OF_BOARD_DTB_ADDR) 0x17fffe70 - CONFIG_SPL_STACK_R_ADDR - is used for GD 0x18000000 is used for SPL stack (CONFIG_SPL_STACK_R_ADDR) 0x20000000-0x21000000 is used for SPL malloc area (CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE) Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- configs/xilinx_zynqmp_virt_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 8d82fe918a60..00f7133d775a 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -8,6 +8,9 @@ CONFIG_SYS_MEMTEST_END=0x00001000 CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu100-revC" +CONFIG_SPL_STACK_R_ADDR=0x18000000 +CONFIG_SPL_SIZE_LIMIT=0x2a000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x0 CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y @@ -28,6 +31,7 @@ CONFIG_USE_PREBOOT=y CONFIG_PREBOOT="run scsi_init;usb start" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_STACK_R=y CONFIG_SPL_FPGA=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y -- 2.33.0

2 1

[PATCH] xilinx: zynqmp: Update descriptions for u-boot.its
by Michal Simek 27 Aug '21

27 Aug '21

Use TF-A instead of ATF in description. And update generic description with removing ATF because also configurations without it are supported. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh index feb3a6260a34..72a8a3eb7714 100755 --- a/arch/arm/mach-zynqmp/mkimage_fit_atf.sh +++ b/arch/arm/mach-zynqmp/mkimage_fit_atf.sh @@ -57,7 +57,7 @@ cat << __HEADER_EOF /dts-v1/; / { - description = "Configuration to load ATF before U-Boot"; + description = "Configuration for Xilinx ZynqMP SoC"; images { uboot { @@ -78,7 +78,7 @@ __HEADER_EOF if [ -f $BL31 ]; then cat << __ATF atf { - description = "ARM Trusted Firmware"; + description = "Trusted Firmware-A"; data = /incbin/("$BL31"); type = "firmware"; os = "arm-trusted-firmware"; -- 2.33.0

2 1

[PATCH 00/10] xilinx: Add support for DTB reselection
by Michal Simek 27 Aug '21

27 Aug '21

Hi, this series add support for board or board+cc runtime DT selection. EEPROM memory is read and based on that decoded if this is legacy/fru based format and proper DTB is used. There is a need to have all DTBs 64bit aligned. If you don't have it you will end up in exception. But one patch in this series is trying to detect it and panic before you reach it to let you know what's wrong. Enforcing mkimage/dtb alignment is done based on CONFIG_PHYS_64BIT and affects all 64bit systems but it is also not wrong for them to be properly aligned. Thanks, Michal Changes in v2: - Update subject and commit message - Enable 64bit alignment for all - reported by Andre - Update subject and commit message - Enable it for all (not just 64bit systems) - Update if condition for MULTI_DTB - call fru_capture in non DEBUG mode - Show detected name as standard message to see what has been chosen Michal Simek (10): xilinx: fru: Replace spaces with \0 in detected name xilinx: Use variable for passing board_name xilinx: common: Change board_info[] handling xilinx: common: Free allocated structure xilinx: Add support for generic board detection xilinx: zynqmp: Check that DT is 64bit aligned Makefile: Align fit-dtb.blob and u-boot.itb by 64bits arm64: dts: Make sure that all DTBs are 64bit aligned xilinx: zynqmp: Generate different u-boot.itb for MULTI_DTB_FIT xilinx: common: Enabling generic function for DT reselection Makefile | 3 + arch/arm/dts/Makefile | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 3 + arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 47 +++++++ board/xilinx/common/board.c | 158 +++++++++++++++++++----- board/xilinx/zynqmp/zynqmp.c | 3 + 6 files changed, 186 insertions(+), 30 deletions(-) -- 2.33.0

3 12

[PATCH v<4>] arm: add initial support for the Phytium Pomelo Board
by nicholas_zheng＠outlook.com 27 Aug '21

27 Aug '21

From: weichangzheng <nicholas_zheng(a)outlook.com> This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE. Signed-off-by: weichangzheng <nicholas_zheng(a)outlook.com> Changes since v1: updated to DT Changes since v2: Modify some explicit types and macro Changes since v3: Modify some SDRAM related macro definitions and distro_bootcmd --- arch/arm/Kconfig | 20 ++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 113 ++++++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 161 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 60 ++++++++++++ board/phytium/pomelo/pll.c | 73 ++++++++++++++ board/phytium/pomelo/pomelo.c | 122 +++++++++++++++++++++++ board/phytium/pomelo/sec.c | 37 +++++++ configs/pomelo_defconfig | 18 ++++ include/configs/pomelo.h | 34 +++++++ 14 files changed, 746 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0448787b8b..029af85fcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1818,6 +1818,25 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie. +config TARGET_POMELO + bool "Support Phytium Pomelo Platform" + select ARM64 + select DM + select AHCI + select SCSI_AHCI + select AHCI_PCI + select BLK + select PCI + select DM_PCI + select SCSI + select DM_SCSI + select DM_SERIAL + select DM_ETH if NET + imply CMD_PCI + help + Support for pomelo platform. + It has 8GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2038,6 +2057,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e6..45d0340bd3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1107,6 +1107,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..3869475902 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium Pomelo board + * Copyright (C) 2021, Phytium Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ +/dts-v1/; + +/ { + model = "Phytium Pomelo"; + compatible = "phytium,pomelo"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu2: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu3: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu4: cpu@8 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu5: cpu@9 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu6: cpu@12 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu7: cpu@13 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x301>; + enable-method = "psci"; + numa-node-id = <0>; + }; + }; + + pcie-controller@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + sysclk_48mhz: clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <48000000>; + clock-output-names = "sysclk_48mhz"; + }; + + uart0: uart@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clocks = <&sysclk_48mhz>; + }; +}; diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig new file mode 100644 index 0000000000..281aa8feff --- /dev/null +++ b/board/phytium/pomelo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POMELO + +config SYS_BOARD + default "pomelo" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pomelo" + +endif diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS new file mode 100644 index 0000000000..d76a4a026e --- /dev/null +++ b/board/phytium/pomelo/MAINTAINERS @@ -0,0 +1,8 @@ +POMELO BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pomelo/* +F: include/configs/pomelo.h +F: configs/pomelo_defconfig +F: arch/arm/dts/phytium-pomelo.dts diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile new file mode 100644 index 0000000000..b9cb3609bd --- /dev/null +++ b/board/phytium/pomelo/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pomelo.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o + + diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h new file mode 100644 index 0000000000..005ea5982b --- /dev/null +++ b/board/phytium/pomelo/cpu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 + * Phytium Technology Ltd <www.phytium.com> + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_POMELO_H +#define _FT_POMELO_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/*CPU RESET*/ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460010 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460011 +#define CFG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define RC_MODE 0x1 +#define X8X8 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460014 +#define PARAM_MCU_VERSION 0x1 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x3 +#define PARAM_ECC_ENABLE 0x3 +#define PARAM_FORCE_SPD_DISABLE 0x0 +#define PARAM_MCU_MISC_ENABLE 0x0 + +#define UDIMM_TYPE 0x2 +#define DIMM_X8 0x1 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_POMELO_H */ diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c new file mode 100644 index 0000000000..c6dbed9639 --- /dev/null +++ b/board/phytium/pomelo/ddr.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct ddr_spd { + /******************* read from spd *****************/ + u8 dimm_type; /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */ + u8 data_width; /* 0: x4; 1: x8; 2: x16 */ + u8 mirror_type;/* 0: stardard; 1: mirror */ + u8 ecc_type; /* 0: no-ecc; 1:ecc */ + u8 dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + u8 rank_num; + u8 row_num; + u8 col_num; + + u8 bg_num; /*only DDR4*/ + u8 bank_num; + u16 module_manufacturer_id; + u16 taamin; + u16 trcdmin; + + u16 trpmin; + u16 trasmin; + u16 trcmin; + u16 tfawmin; + + u16 trrd_smin; /*only DDR4*/ + u16 trrd_lmin; /*only DDR4*/ + u16 tccd_lmin; /*only DDR4*/ + u16 twrmin; + + u16 twtr_smin; /*only DDR4*/ + u16 twtr_lmin; /*only DDR4*/ + u16 twtrmin; /*only DDR3*/ + u16 trrdmin; /*only DDR3*/ + + /******************* RCD control words *****************/ + u8 f0rc03; /*bit[3:2]:CS bit[1:0]:CA */ + u8 f0rc04; /*bit[3:2]:ODT bit[1:0]:CKE */ + u8 f0rc05; /*bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + u8 bc00; + u8 bc01; + u8 bc02; + u8 bc03; + u8 bc04; + + u8 bc05; + u8 f5bc5x; + u8 f5bc6x; + /******************* LRDIMM special *****************/ + u8 vrefdq_pr0; + u8 vrefdq_mdram; + u8 rtt_mdram_1866; + u8 rtt_mdram_2400; + u8 rtt_mdram_3200; + + u8 drive_dram; + u8 odt_dram_1866; + u8 odt_dram_2400; + u8 odt_dram_3200; + u8 park_dram_1866; + u8 park_dram_2400; + u8 park_dram_3200; + u8 rcd_num; +} __attribute((aligned(4))); + +struct mcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + + u8 ch_enable; + u8 misc1_enable; + u8 misc2_enable; + u8 force_spd_enable; + u8 misc3_enable; + u8 train_debug; + u8 train_recover; + u8 rev2[9]; + + struct ddr_spd ddr_spd_info[2]; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; + pm->misc1_enable = PARAM_ECC_ENABLE; + pm->force_spd_enable = PARAM_FORCE_SPD_DISABLE; + pm->misc3_enable = PARAM_MCU_MISC_ENABLE; + pm->train_recover = 0x0; +} + +static u8 init_dimm_param(u8 ch, struct mcu_config *pm) +{ + debug("manual config dimm info...\n"); + pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE; + pm->ddr_spd_info[ch].data_width = DIMM_X8; + pm->ddr_spd_info[ch].mirror_type = NO_MIRROR; + pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info[ch].dram_type = DDR4_TYPE; + pm->ddr_spd_info[ch].rank_num = 1; + pm->ddr_spd_info[ch].row_num = 16; + pm->ddr_spd_info[ch].col_num = 10; + pm->ddr_spd_info[ch].bg_num = 4; + pm->ddr_spd_info[ch].bank_num = 4; + pm->ddr_spd_info[ch].taamin = 13750; + pm->ddr_spd_info[ch].trcdmin = 13750; + + pm->ddr_spd_info[ch].trpmin = 13750; + pm->ddr_spd_info[ch].trasmin = 32000; + pm->ddr_spd_info[ch].trcmin = 45750; + pm->ddr_spd_info[ch].tfawmin = 21000; + + pm->ddr_spd_info[ch].trrd_smin = 3000; + pm->ddr_spd_info[ch].trrd_lmin = 4900; + pm->ddr_spd_info[ch].tccd_lmin = 5000; + pm->ddr_spd_info[ch].twrmin = 15000; + + pm->ddr_spd_info[ch].twtr_smin = 2500; + pm->ddr_spd_info[ch].twtr_lmin = 7500; + + return 0; +} + +void get_default_mcu_info(u8 *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(u8 *data) +{ + struct mcu_config *mcu_info = (struct mcu_config *)data; + + for (int ch = 0; ch < 2; ch++) + init_dimm_param(ch, mcu_info); +} + +void ddr_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("DRAM init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c new file mode 100644 index 0000000000..698d82fd8d --- /dev/null +++ b/board/phytium/pomelo/pcie.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pcu_ctr { + u32 base_config[3]; + u32 equalization[3]; + u8 rev[80]; +} __attribute((aligned(4))); + +struct pcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 independent_tree; + u32 base_cfg; + u8 rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x2, + .size = 0x100, + .independent_tree = CFG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))), + .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PCIE init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c new file mode 100644 index 0000000000..a66ffddf09 --- /dev/null +++ b/board/phytium/pomelo/pll.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pll_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 core_pll; + u32 res1; + u32 lmu_pll; + u32 res2; + u32 res3; + u32 res4; + u32 res5; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x1, + .size = 0x30, + .core_pll = 2300, /*MHz*/ + .lmu_pll = 667, /*MHz*/ +}; + +u32 get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +void pll_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PLL init failed :0x%lx\n", res.a0); +} + +void check_reset(void) +{ + u32 rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + panic("other reset source\n"); + } +} diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c new file mode 100644 index 0000000000..6be30e8c93 --- /dev/null +++ b/board/phytium/pomelo/pomelo.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include <init.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->mem_clk = 0; + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000); + + debug("Phytium ddr init\n"); + + ddr_init(); + sec_init(); + debug("PBF relocate done\n"); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + debug("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("reset cpu error, %lx\n", res.a0); +} + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +int board_early_init_r(void) +{ + return 0; +} + +static struct mm_region pomelo_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x7b000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NS | + PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pomelo_mem_map; + +int __asm_flush_l3_dcache(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); + for (i = 0; i < HNF_COUNT; i++) { + do { + pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); + + return 0; +} + +int last_stage_init(void) +{ + int ret; + + /* pci e */ + pci_init(); + /* scsi scan */ + ret = scsi_scan(true); + if (ret) { + printf("scsi scan failed\n"); + return CMD_RET_FAILURE; + } + return ret; +} diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c new file mode 100644 index 0000000000..aeb3983f01 --- /dev/null +++ b/board/phytium/pomelo/sec.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct common_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u64 core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("SEC init failed :0x%lx\n", res.a0); +} diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig new file mode 100644 index 0000000000..a963d85fbb --- /dev/null +++ b/configs/pomelo_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_POMELO=y +CONFIG_SYS_TEXT_BASE=0x180000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pomelo#" +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_PHYTIUM=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h new file mode 100644 index 0000000000..6dcde9b475 --- /dev/null +++ b/include/configs/pomelo.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __POMELO_CONFIG_H__ +#define __POMELO_CONFIG_H__ + +/* SDRAM Bank #1 start address */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR (0x80000000 + 0x10000000) + +/* SIZE of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (0x100000 + 0x1000) +#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) + +/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1 + +/*BOOT*/ +#define CONFIG_SYS_BOOTM_LEN 0x3c00000 + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "load_kernel=ext4load scsi 0:1 0x90100000 uImage\0" \ + "load_fdt=ext4load scsi 0:1 0x95000000 ft-d2000.dtb\0"\ + "run load_kernel\0"\ + "run load_fdt\0"\ + "bootm 0x90100000 -:- 0x95000000" + +#endif -- 2.17.1

2 1

U-Boot ECDSA Software Implementation Status
by Pabis, Ryan 26 Aug '21

26 Aug '21

I see that Tim was working to add a non-platform specific implementation of the ECDSA algorithm to u-boot back in February. I would like to use this feature as well and was wondering if this work has been completed and where I can find the patch. Thanks, Ryan

2 1

[PATCH 00/28] Initial implementation of bootmethod/bootflow
by Simon Glass 26 Aug '21

26 Aug '21

Bootmethod and bootflow provide a built-in way for U-Boot to automatically boot an Operating System without custom scripting and other customisation: - bootmethod - a method to scan a device to find bootflows (owned by U-Boot) - bootflow - a description of how to boot (owned by the distro) This series provides an initial implementation of these, enable to scan for bootflows from MMC and Ethernet. The only bootflow supported is distro boot, i.e. an extlinux.conf file included on a filesystem or tftp server. It works similiarly to the existing script-based approach, but is native to U-Boot. With this we can boot on a Raspberry Pi 3 with just one command: bootflow scan -lb which means to scan, listing (-l) each bootflow and trying to boot each one (-b). The final patch shows this. It is intended that this approach be expanded to support mechanisms other than distro boot, including EFI-related ones. With a standard way to identify boot devices, these features become easier. It also should support U-Boot scripts, for backwards compatibility only. The first patch of this series moves boot-related code out of common/ and into a new boot/ directory. This helps to collect these related files in one place, as common/ is quite large. Like sysboot, this feature makes use of the existing PXE implementation. Much of this series consists of cleaning up that code and refactoring it into something closer to a module that can be called, teasing apart its reliance on the command-line interpreter to access filesystems and the like. Also it now uses function arguments and its own context struct internally rather than environment variables, which is very hard to follow. No core functional change is included in the included PXE patches. For documentation, see the 'doc' patch. There is quite a long list of future work included in the documentation. One question is the choice of naming. Since this is a bootloader, should we just call this a 'method' and a 'flow' ? The 'boot' prefix is already shared by other commands like bootm, booti, etc. The design is described here: https://drive.google.com/file/d/1ggW0KJpUOR__vBkj3l61L2dav4ZkNC12/view?usp=… The series is available at u-boot-dm/bmea-working Simon Glass (28): Create a new boot/ directory pxe: Move API comments to the header files pxe: Use a context pointer pxe: Move do_getfile() into the context pxe: Add a userdata field to the context pxe: Tidy up the is_pxe global pxe: Move pxe_utils files pxe: Tidy up some comments in pxe_utils pxe: Tidy up code style a little in pxe_utils pxe: Move common parsing coding into pxe_util pxe: Clean up the use of bootfile pxe: Drop get_bootfile_path() lib: Add tests for simple_itoa() lib: Add a function to convert a string to a hex value pxe: Return the file size from the getfile() function pxe: Refactor sysboot to have one helper doc: Move distro boot doc to rST pxe: Allow calling the pxe_get logic directly bootmethod: Add the uclass and core implementation bootmethod: Add an implementation of distro boot bootmethod: Add a command bootflow: Add a command bootmethod: Add tests for bootmethod and bootflow bootmethod: doc: Add documentation mmc: Allow for children other than the block device mmc: Add a bootmethod ethernet: Add a bootmethod RFC: rpi: Switch over to use bootflow Kconfig | 2 + MAINTAINERS | 16 + Makefile | 3 +- README | 1 + common/Kconfig.boot => boot/Kconfig | 22 +- boot/Makefile | 39 ++ {common => boot}/android_ab.c | 0 {common => boot}/boot_fit.c | 0 {common => boot}/bootm.c | 0 {common => boot}/bootm_os.c | 0 boot/bootmethod.c | 485 ++++++++++++++++++++ {common => boot}/bootretry.c | 0 {common => boot}/common_fit.c | 0 boot/distro.c | 194 ++++++++ {common => boot}/fdt_region.c | 0 {common => boot}/image-android-dt.c | 0 {common => boot}/image-android.c | 0 {common => boot}/image-cipher.c | 0 {common => boot}/image-fdt.c | 0 {common => boot}/image-fit-sig.c | 0 {common => boot}/image-fit.c | 0 {common => boot}/image-sig.c | 0 {common => boot}/image.c | 0 {cmd => boot}/pxe_utils.c | 512 +++++++++++----------- cmd/Kconfig | 8 + cmd/Makefile | 5 +- cmd/bootflow.c | 399 +++++++++++++++++ cmd/bootmethod.c | 130 ++++++ cmd/pxe.c | 136 +++--- cmd/pxe_utils.h | 91 ---- cmd/sysboot.c | 114 +++-- common/Kconfig | 2 - common/Makefile | 22 - configs/sandbox_defconfig | 3 +- doc/android/boot-image.rst | 2 +- doc/develop/bootflow.rst | 323 ++++++++++++++ doc/{README.distro => develop/distro.rst} | 180 ++++---- doc/develop/index.rst | 2 + doc/device-tree-bindings/bootmethod.txt | 14 + doc/usage/bootflow.rst | 419 ++++++++++++++++++ doc/usage/bootmethod.rst | 138 ++++++ doc/usage/index.rst | 2 + drivers/mmc/Makefile | 5 + drivers/mmc/mmc-uclass.c | 23 +- drivers/mmc/mmc_bootmethod.c | 46 ++ include/bootmethod.h | 357 +++++++++++++++ include/configs/rpi.h | 37 +- include/distro.h | 62 +++ include/dm/uclass-id.h | 1 + include/mmc.h | 12 +- include/pxe_utils.h | 253 +++++++++++ include/test/suites.h | 2 + include/vsprintf.h | 25 +- lib/vsprintf.c | 20 +- net/Kconfig | 9 + net/Makefile | 1 + net/eth-uclass.c | 8 + net/eth_bootmethod.c | 76 ++++ scripts/Makefile.spl | 4 +- test/Makefile | 1 + test/boot/Makefile | 5 + test/boot/bootmethod.c | 271 ++++++++++++ test/cmd_ut.c | 4 + test/print_ut.c | 33 ++ tools/Makefile | 16 +- try.sh | 131 ++++++ 66 files changed, 4035 insertions(+), 631 deletions(-) rename common/Kconfig.boot => boot/Kconfig (98%) create mode 100644 boot/Makefile rename {common => boot}/android_ab.c (100%) rename {common => boot}/boot_fit.c (100%) rename {common => boot}/bootm.c (100%) rename {common => boot}/bootm_os.c (100%) create mode 100644 boot/bootmethod.c rename {common => boot}/bootretry.c (100%) rename {common => boot}/common_fit.c (100%) create mode 100644 boot/distro.c rename {common => boot}/fdt_region.c (100%) rename {common => boot}/image-android-dt.c (100%) rename {common => boot}/image-android.c (100%) rename {common => boot}/image-cipher.c (100%) rename {common => boot}/image-fdt.c (100%) rename {common => boot}/image-fit-sig.c (100%) rename {common => boot}/image-fit.c (100%) rename {common => boot}/image-sig.c (100%) rename {common => boot}/image.c (100%) rename {cmd => boot}/pxe_utils.c (74%) create mode 100644 cmd/bootflow.c create mode 100644 cmd/bootmethod.c delete mode 100644 cmd/pxe_utils.h create mode 100644 doc/develop/bootflow.rst rename doc/{README.distro => develop/distro.rst} (76%) create mode 100644 doc/device-tree-bindings/bootmethod.txt create mode 100644 doc/usage/bootflow.rst create mode 100644 doc/usage/bootmethod.rst create mode 100644 drivers/mmc/mmc_bootmethod.c create mode 100644 include/bootmethod.h create mode 100644 include/distro.h create mode 100644 include/pxe_utils.h create mode 100644 net/eth_bootmethod.c create mode 100644 test/boot/Makefile create mode 100644 test/boot/bootmethod.c create mode 100755 try.sh -- 2.33.0.rc1.237.g0d66db33f3-goog

7 59

[PATCH 0/6] efi_loader: fix secure boot mode transitions
by Heinrich Schuchardt 26 Aug '21

26 Aug '21

The UEFI specification 2.9 defines the different modes that secure boot may be in. The patch series adds support for the "Deployed Mode" and the "Setup Mode". Furthermore the secure boot signature database must only be loaded from tamper-resistant storage. So we must not load it from ubootefi.var on the EFI system partition but only from the preseed variables store or via the OP-TEE driver for the eMMC replay protected memory partition. Heinrich Schuchardt (6): efi_loader: stop recursion in efi_init_secure_state efi_loader: correct determination of secure boot state efi_loader: don't load signature database from file efi_loader: correct secure boot state transition efi_loader: writing AuditMode, DeployedMode efi_loader: always initialize the secure boot state include/efi_variable.h | 6 ++- lib/efi_loader/efi_var_common.c | 66 +++++++++++++++++++++++-------- lib/efi_loader/efi_var_file.c | 41 +++++++++++-------- lib/efi_loader/efi_variable.c | 20 ++++++---- lib/efi_loader/efi_variable_tee.c | 4 +- 5 files changed, 95 insertions(+), 42 deletions(-) -- 2.30.2

1 6

[PATCH] lx2162a : Rename emmc boot command variable
by meenakshi.aggarwal＠nxp.com 26 Aug '21

26 Aug '21

From: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> Rename emmc_bootcmd environment variable to sd2_bootcmd to fix emmc boot on lx2162aqds board. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> --- include/configs/lx2162aqds.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h index 847534c550..d2145db6f1 100644 --- a/include/configs/lx2162aqds.h +++ b/include/configs/lx2162aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ #ifndef __LX2162_QDS_H @@ -65,7 +65,7 @@ u8 qixis_esdhc_detect_quirk(void); "$kernelhdr_addr_sd $kernelhdr_size_sd " \ " && esbc_validate ${kernelheader_addr_r};" \ "bootm $load_addr#$BOARD\0" \ - "emmc_bootcmd=echo Trying load from emmc card..;" \ + "sd2_bootcmd=echo Trying load from emmc card..;" \ "mmc dev 1; mmcinfo; mmc read $load_addr " \ "$kernel_addr_sd $kernel_size_sd ;" \ "env exists secureboot && mmc read $kernelheader_addr_r "\ -- 2.25.1

1 0

[PATCH] arm: dts: imx8mp: Generate single bootable binary
by Teresa Remmet 26 Aug '21

26 Aug '21

binman conversion made flashing flash.bin and u-boot.itb necessary. Update binman config to create a single flash.bin image again. This updates imx8mp_evk and phyCORE-i.MX8MP as they share the same binman config. Updated also imx8mp_evk documentation. Tested on phyCORE-i.MX8MP. Signed-off-by: Teresa Remmet <t.remmet(a)phytec.de> --- arch/arm/dts/imx8mp-u-boot.dtsi | 17 ++++++++++++++++- .../imx8mp_evk/imximage-8mp-lpddr4.cfg | 2 +- board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 2 +- doc/board/nxp/imx8mp_evk.rst | 1 - 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index a6ede2ed6e30..ace7b2051e7f 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -82,7 +82,7 @@ }; }; - flash { + spl { mkimage { args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000"; @@ -149,4 +149,19 @@ }; }; }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + filename = "spl.bin"; + offset = <0x0>; + }; + + uboot: blob-ext@2 { + filename = "u-boot.itb"; + offset = <0x58000>; + }; + }; }; diff --git a/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg b/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg index b2920b4908ed..2be18de674ba 100644 --- a/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg +++ b/board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg @@ -7,4 +7,4 @@ ROM_VERSION v2 BOOT_FROM sd -LOADER mkimage.flash.mkimage 0x920000 +LOADER mkimage.spl.mkimage 0x920000 diff --git a/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg b/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg index b2920b4908ed..2be18de674ba 100644 --- a/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg +++ b/board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg @@ -7,4 +7,4 @@ ROM_VERSION v2 BOOT_FROM sd -LOADER mkimage.flash.mkimage 0x920000 +LOADER mkimage.spl.mkimage 0x920000 diff --git a/doc/board/nxp/imx8mp_evk.rst b/doc/board/nxp/imx8mp_evk.rst index 609a29f3ebc3..b996ae055e69 100644 --- a/doc/board/nxp/imx8mp_evk.rst +++ b/doc/board/nxp/imx8mp_evk.rst @@ -52,7 +52,6 @@ Burn the flash.bin to the MicroSD card at offset 32KB: .. code-block:: bash $sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync - $sudo dd if=build/u-boot.itb of=/dev/sd[x] bs=1K seek=384 conv=notrunc; sync Boot ---- -- 2.25.1

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[PATCH 0/3] J7200/J721E: Fix USB DFU Boot mode
by Aswath Govindraju 26 Aug '21

26 Aug '21

The following series of patches fix USB DFU Boot mode in J7200 and J721E SoC's. Aswath Govindraju (3): arm: dts: k3-j721e-r5-*.dts: Fix clock-names property in the usb0 instance environment: ti: k3_dfu: Increase the size allocated for bootloader images in dfu_alt_info_ram configs: j72*_evm: Define the buffer sizes for dfu arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 2 +- configs/j7200_evm_a72_defconfig | 2 ++ configs/j7200_evm_r5_defconfig | 1 + configs/j721e_evm_a72_defconfig | 2 ++ configs/j721e_evm_r5_defconfig | 1 + include/configs/j721e_evm.h | 2 -- include/environment/ti/k3_dfu.h | 4 ++-- 7 files changed, 9 insertions(+), 5 deletions(-) -- 2.17.1

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