August 2021 - U-Boot

[PATCH] powerpc: Remove unused FCC ethernet code
by Tom Rini 30 Aug '21

30 Aug '21

This code is no longer used, remove it. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/powerpc/cpu/mpc85xx/Makefile | 1 - arch/powerpc/cpu/mpc85xx/ether_fcc.c | 460 --------------------------- arch/powerpc/cpu/mpc8xxx/cpu.c | 4 - include/configs/MPC8560ADS.h | 47 +-- 4 files changed, 1 insertion(+), 511 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc85xx/ether_fcc.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 15248a40824b..6f4ad1f9b762 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -29,7 +29,6 @@ obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o endif obj-$(CONFIG_CPM2) += commproc.o -obj-$(CONFIG_CPM2) += ether_fcc.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_FSL_CORENET) += liodn.o obj-$(CONFIG_MP) += mp.o diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c deleted file mode 100644 index 3c4eb1a7eba9..000000000000 --- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c +++ /dev/null @@ -1,460 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * MPC8560 FCC Fast Ethernet - * Copyright (c) 2003 Motorola,Inc. - * Xianghua Xiao, (X.Xiao(a)motorola.com) - * - * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek(a)jlc.net) - * - * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger(a)sysgo.de> - */ - -/* - * MPC8560 FCC Fast Ethernet - * Basic ET HW initialization and packet RX/TX routines - * - * This code will not perform the IO port configuration. This should be - * done in the iop_conf_t structure specific for the board. - * - * TODO: - * add a PHY driver to do the negotiation - * reflect negotiation results in FPSMR - * look for ways to configure the board specific stuff elsewhere, eg. - * config_xxx.h or the board directory - */ - -#include <common.h> -#include <malloc.h> -#include <asm/cpm_85xx.h> -#include <command.h> -#include <config.h> -#include <net.h> - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -#include <miiphy.h> -#endif - -#if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) - -static struct ether_fcc_info_s -{ - int ether_index; - int proff_enet; - ulong cpm_cr_enet_sblock; - ulong cpm_cr_enet_page; - ulong cmxfcr_mask; - ulong cmxfcr_value; -} - ether_fcc_info[] = -{ -#ifdef CONFIG_ETHER_ON_FCC1 -{ - 0, - PROFF_FCC1, - CPM_CR_FCC1_SBLOCK, - CPM_CR_FCC1_PAGE, - CONFIG_SYS_CMXFCR_MASK1, - CONFIG_SYS_CMXFCR_VALUE1 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC2 -{ - 1, - PROFF_FCC2, - CPM_CR_FCC2_SBLOCK, - CPM_CR_FCC2_PAGE, - CONFIG_SYS_CMXFCR_MASK2, - CONFIG_SYS_CMXFCR_VALUE2 -}, -#endif - -#ifdef CONFIG_ETHER_ON_FCC3 -{ - 2, - PROFF_FCC3, - CPM_CR_FCC3_SBLOCK, - CPM_CR_FCC3_PAGE, - CONFIG_SYS_CMXFCR_MASK3, - CONFIG_SYS_CMXFCR_VALUE3 -}, -#endif -}; - -/*---------------------------------------------------------------------*/ - -/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */ -#define PKT_MAXDMA_SIZE 1520 - -/* The FCC stores dest/src/type, data, and checksum for receive packets. */ -#define PKT_MAXBUF_SIZE 1518 -#define PKT_MINBUF_SIZE 64 - -/* Maximum input buffer size. Must be a multiple of 32. */ -#define PKT_MAXBLR_SIZE 1536 - -#define TOUT_LOOP 1000000 - -#define TX_BUF_CNT 2 - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * FCC Ethernet Tx and Rx buffer descriptors. - * Provide for Double Buffering - * Note: PKTBUFSRX is defined in net.h - */ - -typedef volatile struct rtxbd { - cbd_t rxbd[PKTBUFSRX]; - cbd_t txbd[TX_BUF_CNT]; -} RTXBD; - -/* Good news: the FCC supports external BDs! */ -#ifdef __GNUC__ -static RTXBD rtx __attribute__ ((aligned(8))); -#else -#error "rtx must be 64-bit aligned" -#endif - -#undef ET_DEBUG - -static int fec_send(struct eth_device *dev, void *packet, int length) -{ - int i = 0; - int result = 0; - - if (length <= 0) { - printf("fec: bad packet size: %d\n", length); - goto out; - } - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - printf("fec: tx buffer not ready\n"); - goto out; - } - } - - rtx.txbd[txIdx].cbd_bufaddr = (uint)packet; - rtx.txbd[txIdx].cbd_datlen = length; - rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \ - BD_ENET_TX_TC | BD_ENET_TX_PAD); - - for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) { - if (i >= TOUT_LOOP) { - printf("fec: tx error\n"); - goto out; - } - } - -#ifdef ET_DEBUG - printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc); - printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length); - for(i=0;i<(length/16 + 1);i++) { - printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\ - *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \ - *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3)); - } -#endif - - /* return only status bits */ - result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS; - txIdx = (txIdx + 1) % TX_BUF_CNT; - -out: - return result; -} - -static int fec_recv(struct eth_device* dev) -{ - int length; - - for (;;) - { - if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - length = -1; - break; /* nothing received - leave for() loop */ - } - length = rtx.rxbd[rxIdx].cbd_datlen; - - if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) { - printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc); - } - else { - /* Pass the packet up to the protocol layers. */ - net_process_received_packet(net_rx_packets[rxIdx], length - 4); - } - - - /* Give the buffer back to the FCC. */ - rtx.rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } - else { - rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - } - return length; -} - - -static int fec_init(struct eth_device* dev, struct bd_info *bis) -{ - struct ether_fcc_info_s * info = dev->priv; - int i; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - volatile ccsr_cpm_cp_t *cp = &(cpm->im_cpm_cp); - fcc_enet_t *pram_ptr; - unsigned long mem_addr; - -#if 0 - mii_discover_phy(); -#endif - - /* 28.9 - (1-2): ioports have been set up already */ - - /* 28.9 - (3): connect FCC's tx and rx clocks */ - cpm->im_cpm_mux.cmxuar = 0; /* ATM */ - cpm->im_cpm_mux.cmxfcr = (cpm->im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) | - info->cmxfcr_value; - - /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32; - } - - /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; - } else if (info->ether_index == 1){ - cpm->im_cpm_fcc2.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; - } else if (info->ether_index == 2){ - cpm->im_cpm_fcc3.fpsmr = CONFIG_SYS_FCC_PSMR | FCC_PSMR_ENCRC; - } - - /* 28.9 - (6): FDSR: Ethernet Syn */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fdsr = 0xD555; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.fdsr = 0xD555; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.fdsr = 0xD555; - } - - /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */ - rxIdx = 0; - txIdx = 0; - - /* Setup Receiver Buffer Descriptors */ - for (i = 0; i < PKTBUFSRX; i++) - { - rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx.rxbd[i].cbd_datlen = 0; - rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; - } - rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* Setup Ethernet Transmitter Buffer Descriptors */ - for (i = 0; i < TX_BUF_CNT; i++) - { - rtx.txbd[i].cbd_sc = 0; - rtx.txbd[i].cbd_datlen = 0; - rtx.txbd[i].cbd_bufaddr = 0; - } - rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* 28.9 - (7): initialize parameter ram */ - pram_ptr = (fcc_enet_t *)&(cpm->im_dprambase[info->proff_enet]); - - /* clear whole structure to make sure all reserved fields are zero */ - memset((void*)pram_ptr, 0, sizeof(fcc_enet_t)); - - /* - * common Parameter RAM area - * - * Allocate space in the reserved FCC area of DPRAM for the - * internal buffers. No one uses this space (yet), so we - * can do this. Later, we will add resource management for - * this area. - * CPM_FCC_SPECIAL_BASE: 0xB000 for MPC8540, MPC8560 - * 0x9000 for MPC8541, MPC8555 - */ - mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64); - pram_ptr->fen_genfcc.fcc_riptr = mem_addr; - pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32; - /* - * Set maximum bytes per receive buffer. - * It must be a multiple of 32. - */ - pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */ - /* localbus SDRAM should be preferred */ - pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB | - CONFIG_SYS_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]); - pram_ptr->fen_genfcc.fcc_rbdstat = 0; - pram_ptr->fen_genfcc.fcc_rbdlen = 0; - pram_ptr->fen_genfcc.fcc_rdptr = 0; - /* localbus SDRAM should be preferred */ - pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB | - CONFIG_SYS_CPMFCR_RAMTYPE) << 24; - pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]); - pram_ptr->fen_genfcc.fcc_tbdstat = 0; - pram_ptr->fen_genfcc.fcc_tbdlen = 0; - pram_ptr->fen_genfcc.fcc_tdptr = 0; - - /* protocol-specific area */ - pram_ptr->fen_statbuf = 0x0; - pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */ - pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */ - pram_ptr->fen_crcec = 0; - pram_ptr->fen_alec = 0; - pram_ptr->fen_disfc = 0; - pram_ptr->fen_retlim = 15; /* Retry limit threshold */ - pram_ptr->fen_retcnt = 0; - pram_ptr->fen_pper = 0; - pram_ptr->fen_boffcnt = 0; - pram_ptr->fen_gaddrh = 0; - pram_ptr->fen_gaddrl = 0; - pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */ - /* - * Set Ethernet station address. - * - * This is supplied in the board information structure, so we - * copy that into the controller. - * So far we have only been given one Ethernet address. We make - * it unique by setting a few bits in the upper byte of the - * non-static part of the address. - */ -#define ea eth_get_ethaddr() - pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - pram_ptr->fen_ibdcount = 0; - pram_ptr->fen_ibdstart = 0; - pram_ptr->fen_ibdend = 0; - pram_ptr->fen_txlen = 0; - pram_ptr->fen_iaddrh = 0; /* disable hash */ - pram_ptr->fen_iaddrl = 0; - pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */ - /* pad pointer. use tiptr since we don't need a specific padding char */ - pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr; - pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */ - pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */ - -#if defined(ET_DEBUG) - printf("parm_ptr(0xff788500) = %p\n",pram_ptr); - printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n", - pram_ptr->fen_genfcc.fcc_rbase); - printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n", - pram_ptr->fen_genfcc.fcc_tbase); -#endif - - /* 28.9 - (8)(9): clear out events in FCCE */ - /* 28.9 - (9): FCCM: mask all events */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.fcce = ~0x0; - cpm->im_cpm_fcc1.fccm = 0; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.fcce = ~0x0; - cpm->im_cpm_fcc2.fccm = 0; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.fcce = ~0x0; - cpm->im_cpm_fcc3.fccm = 0; - } - - /* 28.9 - (10-12): we don't use ethernet interrupts */ - - /* 28.9 - (13) - * - * Let's re-initialize the channel now. We have to do it later - * than the manual describes because we have just now finished - * the BD initialization. - */ - cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page, - info->cpm_cr_enet_sblock, - 0x0c, - CPM_CR_INIT_TRX) | CPM_CR_FLG; - do { - __asm__ __volatile__ ("eieio"); - } while (cp->cpcr & CPM_CR_FLG); - - /* 28.9 - (14): enable tx/rx in gfmr */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } else if (info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } else if (info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR; - } - - return 1; -} - -static void fec_halt(struct eth_device* dev) -{ - struct ether_fcc_info_s * info = dev->priv; - volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR; - - /* write GFMR: disable tx/rx */ - if(info->ether_index == 0) { - cpm->im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } else if(info->ether_index == 1) { - cpm->im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } else if(info->ether_index == 2) { - cpm->im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR); - } -} - -int fec_initialize(struct bd_info *bis) -{ - struct eth_device* dev; - int i; - - for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) - { - dev = (struct eth_device*) malloc(sizeof *dev); - memset(dev, 0, sizeof *dev); - - sprintf(dev->name, "FCC%d", - ether_fcc_info[i].ether_index + 1); - dev->priv = &ether_fcc_info[i]; - dev->init = fec_init; - dev->halt = fec_halt; - dev->send = fec_send; - dev->recv = fec_recv; - - eth_register(dev); - -#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ - && defined(CONFIG_BITBANGMII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = bb_miiphy_read; - mdiodev->write = bb_miiphy_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - } - - return 1; -} - -#endif diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index eda64861ee6f..0985fb2d0577 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -351,10 +351,6 @@ int fixup_cpu(void) */ int cpu_eth_init(struct bd_info *bis) { -#if defined(CONFIG_ETHER_ON_FCC) - fec_initialize(bis); -#endif - #if defined(CONFIG_UEC_ETH) uec_standard_init(bis); #endif diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 02aeb6f3d536..10cd44c18d66 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -29,7 +29,6 @@ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* @@ -259,50 +258,6 @@ #endif /* CONFIG_TSEC_ENET */ -#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ - -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#endif - /* * Environment */ @@ -339,7 +294,7 @@ /* * Environment Configuration */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) +#if defined(CONFIG_TSEC_ENET) #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 -- 2.17.1

1 1

[PATCH 1/3] aristainetos2: Rename CONFIG_EXTRA_ENV_BOARD_SETTINGS
by Tom Rini 30 Aug '21

30 Aug '21

Rename CONFIG_EXTRA_ENV_BOARD_SETTINGS to EXTRA_ENV_BOARD_SETTINGS in order to not further add to the CONFIG namespace. Cc: Heiko Schocher <hs(a)denx.de> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- include/configs/aristainetos2.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 78fa1a969e7f..69398787d9e7 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -93,13 +93,13 @@ #endif #if (CONFIG_SYS_BOARD_VERSION == 5) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ +#define EXTRA_ENV_BOARD_SETTINGS \ "dead=while true; do; " \ "led led_red on; sleep 1;" \ "led led_red off; sleep 1;" \ "done\0" #elif (CONFIG_SYS_BOARD_VERSION == 6) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ +#define EXTRA_ENV_BOARD_SETTINGS \ "dead=while true; do; " \ "led led_red on; led led_red2 on; sleep 1;" \ "led led_red off; led led_red2 off;; sleep 1;" \ @@ -414,7 +414,7 @@ "run main_rescue_boot;" \ "fi; \0"\ HAB_EXTRA_SETTINGS \ - CONFIG_EXTRA_ENV_BOARD_SETTINGS + EXTRA_ENV_BOARD_SETTINGS #define CONFIG_ARP_TIMEOUT 200UL -- 2.17.1

3 7

[PATCH] usb: dwc2: Rename CONFIG_DWC2 namespace to DWC2
by Tom Rini 30 Aug '21

30 Aug '21

There are a number of DWC2 configuration options that are set in dwc2.h and referenced in dwc2.c only. Move these out of the CONFIG_DWC2 namespace and in to the DWC2 namespace. Note that hikey was defining an option that was already always enabled, so we can remove that hunk. Cc: Marek Vasut <marex(a)denx.de> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- drivers/usb/host/dwc2.c | 52 ++++++++++++++++++------------------ drivers/usb/host/dwc2.h | 42 ++++++++++++++--------------- include/configs/hikey.h | 4 --- scripts/config_whitelist.txt | 20 -------------- 4 files changed, 47 insertions(+), 71 deletions(-) diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 43cc2e04339c..23060fc369c0 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -86,14 +86,14 @@ static void init_fslspclksel(struct dwc2_core_regs *regs) { uint32_t phyclk; -#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) +#if (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ #else /* High speed PHY running at full speed or high speed */ phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; #endif -#ifdef CONFIG_DWC2_ULPI_FS_LS +#ifdef DWC2_ULPI_FS_LS uint32_t hwcfg2 = readl(&regs->ghwcfg2); uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; @@ -257,28 +257,28 @@ static void dwc_otg_core_host_init(struct udevice *dev, /* Initialize Host Configuration Register */ init_fslspclksel(regs); -#ifdef CONFIG_DWC2_DFLT_SPEED_FULL +#ifdef DWC2_DFLT_SPEED_FULL setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); #endif /* Configure data FIFO sizes */ -#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO +#ifdef DWC2_ENABLE_DYNAMIC_FIFO if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { /* Rx FIFO */ - writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz); + writel(DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz); /* Non-periodic Tx FIFO */ - nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << + nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE << DWC2_FIFOSIZE_DEPTH_OFFSET; - nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << + nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE << DWC2_FIFOSIZE_STARTADDR_OFFSET; writel(nptxfifosize, &regs->gnptxfsiz); /* Periodic Tx FIFO */ - ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << + ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE << DWC2_FIFOSIZE_DEPTH_OFFSET; - ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + - CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << + ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE + + DWC2_HOST_NPERIO_TX_FIFO_SIZE) << DWC2_FIFOSIZE_STARTADDR_OFFSET; writel(ptxfifosize, &regs->hptxfsiz); } @@ -340,7 +340,7 @@ static void dwc_otg_core_init(struct udevice *dev) struct dwc2_core_regs *regs = priv->regs; uint32_t ahbcfg = 0; uint32_t usbcfg = 0; - uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; + uint8_t brst_sz = DWC2_DMA_BURST_SIZE; /* Common Initialization */ usbcfg = readl(&regs->gusbcfg); @@ -357,7 +357,7 @@ static void dwc_otg_core_init(struct udevice *dev) } /* Set external TS Dline pulsing */ -#ifdef CONFIG_DWC2_TS_DLINE +#ifdef DWC2_TS_DLINE usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; #else usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; @@ -371,8 +371,8 @@ static void dwc_otg_core_init(struct udevice *dev) * This programming sequence needs to happen in FS mode before * any other programming occurs */ -#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ - (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) +#if defined(DWC2_DFLT_SPEED_FULL) && \ + (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) /* If FS mode with FS PHY */ setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL); @@ -387,7 +387,7 @@ static void dwc_otg_core_init(struct udevice *dev) if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) init_fslspclksel(regs); -#ifdef CONFIG_DWC2_I2C_ENABLE +#ifdef DWC2_I2C_ENABLE /* Program GUSBCFG.OtgUtmifsSel to I2C */ setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); @@ -407,16 +407,16 @@ static void dwc_otg_core_init(struct udevice *dev) * immediately after setting phyif. */ usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); - usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; + usbcfg |= DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ -#ifdef CONFIG_DWC2_PHY_ULPI_DDR +#ifdef DWC2_PHY_ULPI_DDR usbcfg |= DWC2_GUSBCFG_DDRSEL; #else usbcfg &= ~DWC2_GUSBCFG_DDRSEL; #endif } else { /* UTMI+ interface */ -#if (CONFIG_DWC2_UTMI_WIDTH == 16) +#if (DWC2_UTMI_WIDTH == 16) usbcfg |= DWC2_GUSBCFG_PHYIF; #endif } @@ -429,7 +429,7 @@ static void dwc_otg_core_init(struct udevice *dev) usbcfg = readl(&regs->gusbcfg); usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); -#ifdef CONFIG_DWC2_ULPI_FS_LS +#ifdef DWC2_ULPI_FS_LS uint32_t hwcfg2 = readl(&regs->ghwcfg2); uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; @@ -456,14 +456,14 @@ static void dwc_otg_core_init(struct udevice *dev) brst_sz >>= 1; } -#ifdef CONFIG_DWC2_DMA_ENABLE +#ifdef DWC2_DMA_ENABLE ahbcfg |= DWC2_GAHBCFG_DMAENABLE; #endif break; case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; -#ifdef CONFIG_DWC2_DMA_ENABLE +#ifdef DWC2_DMA_ENABLE ahbcfg |= DWC2_GAHBCFG_DMAENABLE; #endif break; @@ -476,7 +476,7 @@ static void dwc_otg_core_init(struct udevice *dev) if (!priv->hnp_srp_disable) usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP; -#ifdef CONFIG_DWC2_IC_USB_CAP +#ifdef DWC2_IC_USB_CAP usbcfg |= DWC2_GUSBCFG_IC_USB_CAP; #endif @@ -939,9 +939,9 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, in, len); - max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; - if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) - max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; + max_xfer_len = DWC2_MAX_PACKET_COUNT * max; + if (max_xfer_len > DWC2_MAX_TRANSFER_SIZE) + max_xfer_len = DWC2_MAX_TRANSFER_SIZE; if (max_xfer_len > DWC2_DATA_BUF_SIZE) max_xfer_len = DWC2_DATA_BUF_SIZE; @@ -1198,7 +1198,7 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) return -ENODEV; } -#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS +#ifdef DWC2_PHY_ULPI_EXT_VBUS priv->ext_vbus = 1; #else priv->ext_vbus = 0; diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h index 97a06c48f216..a6f562fe60e2 100644 --- a/drivers/usb/host/dwc2.h +++ b/drivers/usb/host/dwc2.h @@ -759,32 +759,32 @@ struct dwc2_core_regs { #define RH_B_PPCM 0xffff0000 /* port power control mask */ /* Default driver configuration */ -#define CONFIG_DWC2_DMA_ENABLE -#define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ -#undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ -#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ -#define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */ -#define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS) -#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ -#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ -#define CONFIG_DWC2_MAX_TRANSFER_SIZE 65535 -#define CONFIG_DWC2_MAX_PACKET_COUNT 511 +#define DWC2_DMA_ENABLE +#define DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ +#undef DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ +#define DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ +#define DWC2_MAX_CHANNELS 16 /* Max # of EPs */ +#define DWC2_HOST_RX_FIFO_SIZE (516 + DWC2_MAX_CHANNELS) +#define DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ +#define DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ +#define DWC2_MAX_TRANSFER_SIZE 65535 +#define DWC2_MAX_PACKET_COUNT 511 #define DWC2_PHY_TYPE_FS 0 #define DWC2_PHY_TYPE_UTMI 1 #define DWC2_PHY_TYPE_ULPI 2 -#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ -#ifndef CONFIG_DWC2_UTMI_WIDTH -#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ +#define DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ +#ifndef DWC2_UTMI_WIDTH +#define DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ #endif -#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ -#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ -#undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */ -#undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */ -#undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */ -#undef CONFIG_DWC2_THR_CTL /* Threshold control */ -#define CONFIG_DWC2_TX_THR_LENGTH 64 -#undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */ +#undef DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ +#define DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ +#undef DWC2_I2C_ENABLE /* Enable I2C */ +#undef DWC2_ULPI_FS_LS /* ULPI is FS/LS */ +#undef DWC2_TS_DLINE /* External DLine pulsing */ +#undef DWC2_THR_CTL /* Threshold control */ +#define DWC2_TX_THR_LENGTH 64 +#undef DWC2_IC_USB_CAP /* IC Cap */ #endif /* __DWC2_H__ */ diff --git a/include/configs/hikey.h b/include/configs/hikey.h index 659fbee052d5..45b01463acb1 100644 --- a/include/configs/hikey.h +++ b/include/configs/hikey.h @@ -47,10 +47,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) -#ifdef CONFIG_USB_DWC2 -#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO -#endif - #define CONFIG_HIKEY_GPIO /* BOOTP options */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2d70bf5da7c5..9384aa8e4e0b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -282,26 +282,6 @@ CONFIG_DRIVER_AT91EMAC_PHYADDR CONFIG_DRIVER_AT91EMAC_QUIET CONFIG_DRIVER_DM9000 CONFIG_DSP_CLUSTER_START -CONFIG_DWC2_DFLT_SPEED_FULL -CONFIG_DWC2_DMA_BURST_SIZE -CONFIG_DWC2_DMA_ENABLE -CONFIG_DWC2_ENABLE_DYNAMIC_FIFO -CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE -CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE -CONFIG_DWC2_HOST_RX_FIFO_SIZE -CONFIG_DWC2_I2C_ENABLE -CONFIG_DWC2_IC_USB_CAP -CONFIG_DWC2_MAX_CHANNELS -CONFIG_DWC2_MAX_PACKET_COUNT -CONFIG_DWC2_MAX_TRANSFER_SIZE -CONFIG_DWC2_PHY_TYPE -CONFIG_DWC2_PHY_ULPI_DDR -CONFIG_DWC2_PHY_ULPI_EXT_VBUS -CONFIG_DWC2_THR_CTL -CONFIG_DWC2_TS_DLINE -CONFIG_DWC2_TX_THR_LENGTH -CONFIG_DWC2_ULPI_FS_LS -CONFIG_DWC2_UTMI_WIDTH CONFIG_DWCDDR21MCTL CONFIG_DWCDDR21MCTL_BASE CONFIG_DWC_AHSATA_BASE_ADDR -- 2.17.1

1 1

[PATCH 1/2] arm: mach-rmobile: Move cpu_reset to rzg2-reset.c
by Adam Ford 30 Aug '21

30 Aug '21

Various RZ/G2[MNH] boards have copies of cpu_reset which creates duplicate code, so move this to a common file shared among all users of the RZG2 and declare it weak so it can be overwritten if necessary. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile index 195bbeb5c8..2bd173ec3a 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-rmobile/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o -obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o +obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o rzg2-reset.o ifneq ($(CONFIG_R8A779A0),) obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o diff --git a/arch/arm/mach-rmobile/rzg2-reset.c b/arch/arm/mach-rmobile/rzg2-reset.c new file mode 100644 index 0000000000..8c3608f34a --- /dev/null +++ b/arch/arm/mach-rmobile/rzg2-reset.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Renesas Electronics Corporation + */ + +#include <asm/io.h> + +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_CA57_CODE 0xA5A5000F +#define RST_CA53_CODE 0x5A5A000F + +__weak void reset_cpu(void) +{ + unsigned long midr, cputype; + + asm volatile("mrs %0, midr_el1" : "=r" (midr)); + cputype = (midr >> 4) & 0xfff; + + if (cputype == 0xd03) + writel(RST_CA53_CODE, RST_CA53RESCNT); + else + writel(RST_CA57_CODE, RST_CA57RESCNT); +} + -- 2.25.1

2 4

[ANN] U-Boot v2021.10-rc3 released
by Tom Rini 30 Aug '21

30 Aug '21

Hey all, It's release day again and here's v2021.10-rc3. At this point in the cycle, I'm opening up the -next branch, which is now in sync with master. I'll be re-syncing each -rc in to -next. As you might have noticed, I've pushed out a large number of CONFIG migrations to Kconfig of late. I'll be merging most of those to -next shortly. I want to note that how I've been doing these is a combination of moveconfig.py, which works great for most things, and https://patchwork.ozlabs.org/project/uboot/patch/1500407318-7977-1-git-send… updated for whatever symbol I'm using, when complex math is involved. This also lets me do a before/after so I can be sure that say SYS_MALLOC_LEN is the same. In terms of a changelog, git log --merges v2021.10-rc2..v2021.10-rc3 contains what I've pulled but as always, better PR messages and tags will provide better results here. We'll continue with every other week -rc's from here out, and that shouldn't impact the October 4th, 2021 release date. Thanks all! -- Tom

1 0

[PATCH 0/5] Fix FIT hash algos in SPL (Fixes v2021.10-rc2)
by Alexandru Gagniuc 30 Aug '21

30 Aug '21

Simon and I recently worked on killing a bunch extra definitions. One of the side-effects is that certain hash algorithms won't work in SPL when used in the context of FIT verification. For example, in FIT verification, CONFIG_IS_ENABLED(SHA256) is used (good), but there is no corresponding CONFIG_SPL_SHA256 (bad). This will always be false for SPL, hence certain "hash" algos are broken. This series resolves the selection by replacing the broken selection with hash_lookup_algo(), which does not have the aforementioned problem. This at the very least allows 'algo = "sha256"' FIT nodes to work in SPL. This series does not attempt to add individual SHA/CRC/MD5 configs for SPL. Hash algo selection for SPL has been problematic even before. This series is meant as an emergency fix, so it does not attempt to tackle general refactoring issues. Alexandru Gagniuc (5): common: Remove unused CONFIG_FIT_SHAxxx selectors lib: Drop SHA512_ALGO in lieu of SHA512 common/spl: Drop SPL_HASH_SUPPORT in favor of SPL_HASH image: Drop if/elseif hash selection in calculate_hash() image: Drop IMAGE_ENABLE_{MD5, CRC32} #defines arch/arm/mach-socfpga/Kconfig | 2 +- common/Kconfig.boot | 32 ++--------- common/Makefile | 3 +- common/image-fit.c | 45 +++++++--------- common/spl/Kconfig | 54 +------------------ ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 +- configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 2 +- .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 2 +- .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 2 +- ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 2 +- configs/mt8516_pumpkin_defconfig | 2 +- include/configs/xilinx_zynqmp.h | 2 +- include/image.h | 23 -------- lib/Kconfig | 12 ++--- lib/Makefile | 2 +- lib/crypt/Kconfig | 2 +- lib/efi_loader/Kconfig | 2 +- lib/sha512.c | 2 - 18 files changed, 39 insertions(+), 154 deletions(-) -- 2.31.1

2 9

[PATCH V2 1/2] ARM: dts: rmobile: beacon-renesom: Enable USB and ethernet ref clocks
by Adam Ford 30 Aug '21

30 Aug '21

There are two versaclock programmable clock chips used to provide reference clocks for both USB and Ethernet. Enable the driver in the configs to run these clocks. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- V2: Move from defconfig to kconfig diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index a6dcce180b..c90ea06692 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -76,18 +76,24 @@ config TARGET_BEACON_RZG2H select R8A774E1 select RZ_G2 select PINCTRL_PFC_R8A774E1 + select CLK_CCF + select CLK_VERSACLOCK config TARGET_BEACON_RZG2M bool "Beacon EmbeddedWorks RZ/G2M Dev Kit" select R8A774A1 select RZ_G2 select PINCTRL_PFC_R8A774A1 + select CLK_CCF + select CLK_VERSACLOCK config TARGET_BEACON_RZG2N bool "Beacon EmbeddedWorks RZ/G2N Dev Kit" select R8A774B1 select RZ_G2 select PINCTRL_PFC_R8A774B1 + select CLK_CCF + select CLK_VERSACLOCK config TARGET_CONDOR bool "Condor board" -- 2.25.1

1 2

incompatible device trees between u-boot and linux
by François Ozog 30 Aug '21

30 Aug '21

Hi, Trying to respond to a U-Boot digest manually, please accept apologies as I don't know how to do it properly... >On Wed, Aug 25, 2021 at 06:43:23PM +0300, Vladimir Oltean wrote: >> On Wed, Aug 25, 2021 at 11:24:08AM -0400, Tom Rini wrote: >> > On Wed, Aug 25, 2021 at 06:12:20PM +0300, Vladimir Oltean wrote: >> > > On Wed, Aug 25, 2021 at 10:26:10AM -0400, Tom Rini wrote: >> > > > On Wed, Aug 25, 2021 at 05:18:16PM +0300, Vladimir Oltean wrote: >> > > > > On Wed, Aug 25, 2021 at 10:00:45AM -0400, Tom Rini wrote: >> > > > > > On Wed, Aug 25, 2021 at 03:58:10PM +0200, Michael Walle wrote: >> > > > > > >> > > > > > > Hi, >> > > > > > > >> > > > > > > I noticed that there is a fallback to the u-boot device tree for linux >> > > > > > > (esp. EFI boot) if no other device tree was found, see [1]. It seems this >> > > > > > > is working fine for imx devices, for example, where you can just boot a >> > > > > > > stock installer iso via EFI. It will just work and it is quite a nice >> > > > > > > feature as a fallback. >> > > > > > > >> > > > > > > Now for the layerscape architecture, the ls1028a in my case, things are >> > > > > > > more difficult because the bindings differ between u-boot and linux - one >> > > > > > > which comes to mind is DSA and ethernet. >> > > > > > > >> > > > > > > Which begs the general question, is it encouraged to have both bindings >> > > > > > > diverge? To me it seems, that most bindings in u-boot are ad-hoc and there >> > > > > > > is no real review or alignment but just added as needed, which is ok if >> > > > > > > they are local to u-boot. But since they are nowadays passed to linux >> > > > > > > (by default!) I'm not so sure anymore. >> > > > > > > >> > > > > > > OTOH The whole structure around a .dts{,i} and -u-boot.dtsi looks like >> > > > > > > they should (could?) be shared between linux and u-boot. >> > > > > > > >> > > > > > > -michael >> > > > > > > >> > > > > > > [1] >> > > > > > > https://elixir.bootlin.com/u-boot/v2021.10-rc2/source/common/board_r.c#L471 >> > > > > > >> > > > > > The U-Boot device tree is supposed to be able to be passed on to Linux >> > > > > > and Just Work. The bindings are not supposed to be different between >> > > > > > the two (except for when we take the binding while it's being hashed out >> > > > > > upstream BUT THEN RESYNCED). >> > > > > >> > > > > You might need to spell that out a bit clearer. >> > > > > >> > > > > You are saying that both U-Boot and Linux are allowed to have their own >> > > > > custom properties (like 'u-boot,dm-spl' for U-Boot, and 'managed = "in-band-status"' >> > > > > for Linux), as long as the device tree files themselves are in sync, and >> > > > > the subset of the device tree blob understood by Linux (i.e. the U-Boot >> > > > > blob sans the U-Boot specifics) is compatible with the Linux DT blob? >> > > > >> > > > I don't know what about the Linux example makes it Linux specific. But >> > > > yes, 'u-boot,dm-spl' is clearly in our namespace and should be ignored >> > > > by Linux. The whole reason we have the -u-boot.dtsi automatic drop-in >> > > > logic (as much as it can be used is that device trees are device trees >> > > ^ >> > > I don't think this parenthesis ever closes... >> > >> > Ah, whoops. Should have been "(as much as it can be used)" because it >> > does get #included instead in some cases, for reasons. >> > >> > > >> > > > and describe the hardware and developers don't need to write a device >> > > > tree for Linux and a device tree for U-Boot and a device tree for >> > > > FreeBSD and ... So yes, you're supposed to use the device tree for a >> > > ^ >> > > so I never get the answer to "the whole reason is...". >> > > >> > > > platform and it works here and there and every where. >> > > >> > > The fact that only Linux uses it makes it Linux specific. >> > > >> > > > > To expand even further on that, it means we should put 'managed = "in-band-status"' >> > > > > in U-Boot, which is a Linux phylink device tree property, even if U-Boot >> > > > > does not use phylink? >> > > > >> > > > We should be able to drop in the device trees from Linux and use them. >> > > > Custodians should be re-syncing them periodically. Some are, even. >> > > >> > > Are you ready to take up device tree bindings for PTP timers, PCIe root >> > > complex event collectors, cascaded interrupt controllers, things which >> > > U-Boot will never ever need to support? >> > > >> > > At least in Linux there is a policy to not add device tree nodes that do >> > > not have drivers. Is the same policy not true for U-Boot? At least your >> > > ./scripts/checkpatch.pl does have the same "check for DT compatible >> > > documentation" section as Linux. You might consider removing it if you >> > > want people to not strip the DTs they submit to U-Boot. >> > > >> > > And why do we even maintain the device tree bindings in Linux at all? >> > > It seems rather counter-productive for both ends to do that, if it is >> > > expected that the kernel works with DT blobs provided by third parties too, >> > > and if all third parties need to resync with it (there are other boot >> > > loaders too beyond U-Boot, and other kernels beyond Linux). Somehow it >> > > doesn't feel right for the reference to be the Linux kernel. Maybe this >> > > is something that needs to be brought up with higher-level Linux maintainers. >> > > >> > > I have no problem at all with structuring the device tree in the same >> > > way in U-Boot as in Linux, as long as that proves to not be a foolish >> > > endeavor. >> > >> > DT is ABI is hardware description and OS-agnostic has been the rule for >> > 10+ years. If that's no longer the case, can someone please tell me? >> >> So if Michael's board with DT provided by U-Boot doesn't work for some >> stupid reason like "Linux expects the pcie node to be under /soc", or >> "Linux wants all PCIe BARs of a RCIEP ECAM to be spelled out in the >> 'ranges' property, because it's too dumb to detect them itself", or >> something like that, I've got no argument against that, let's go ahead >> and resync U-Boot with Linux. >> >> But "DT is ABI is hardware description" is a pretty vague truism that >> does not actually help here. > >I'm saying that because it's what's been said for what feels like 10+ >years. I don't want to think how many countless hours have been spent >on that point at conferences over the years. It's not even a Linux >thing. I would swear you can (or could, unless it got broken) take the >same DTB for some platforms and boot Linux or FreeBSD or some other BSD >or maybe even VxWorks and it works. > > I cannot agree more. For historical reasons in the embedded market, the product maker was the board maker, the distro producer and the firmware producer. That led to a situation where the Linux kernel developper was stating the hardware description and that led to...problems. The best analogy I have to describe how wrong this is: As a French driver, my Device Tree description about the car is that the steering wheel is on the left hand side of the car; when entering an English car, I just complain that the wheel is not where it should be. Now the value chain is going more "mature" and your may end up booting a Fedora IoT edition on a bunch of platforms that have been designed to boot any distro; and the Trusted Applications may come from the OEM and not the board maker. Organizing the software value chain along side of the hardware value chain (Silicon provider, SoM provider, Carrier provider, Integrator, Car manufacturer for instance) need DT technology and lifecycle re-boot. (softwsystem up firmware such as Trusted Firmware, boot firmware such as U-Boot and operating systems) Some elements of discussion can be found here: https://linaro.atlassian.net/wiki/spaces/DTE/overview https://docs.google.com/document/d/1CLkhLRaz_zcCq44DLGmPZQFPbYHOC6nzPowaL0X… If we take the https://www.solid-run.com/arm-servers-networking-platforms/honeycomb-workst… board as an example to stay on NXP SoCs: what is the ideal way to deal with device tree should we start from a blank sheet? A key element are SerDes pins: from a SoC perspective they can be made PCI lanes or Ethernet lanes. This is chosen by the board vendor. An operating system should never manage the SerDes, it will see either the PCI lanes or the Ethernet port (not exactly true yet because of DPAA2 - but let's keep it high level). It is the responsibility of the firmware to actually match the SoC configuration with board layout (PCI slot, PCI device, Ethernet port). In my mind, the ideal situation is: The board vendor takes the SoC DT as input and applies fixups (at design time or runtime) to produce the board DT. The board DT should be independent from the firmware stack (Coreboot, TF-A+U-Boot, TF-A + LinuxBoot) and the booted OS: it is just describing the hardware!!! Firmware elements can still apply fixes at runtime: TF-A role is to pass detected DRAM, U-Boot may have a parameter (saved as U-Boot variable) to define active cores and ensures the DT is fixed up to match that desire, OP-TEE can expose the amount of Secure DRAM it has carved out through FF-A API. >> Will you accept device trees with devices for which a driver will never >> probe in U-Boot, > >Yes, I will absolutely take device trees that have devices we don't need >in U-Boot since the point is, and many SoC vendors are doing (and the >ones that aren't are, I am not happy about / with) right now. > >> and will you remove the checkpatch warnings about those, >> to not discourage people from submitting them prior to the actual public >> review? > >With respect to checkpatch.pl, maybe I'm just missing the line in >question? Or maybe it's a kernel-related warning we need to disable in >our .checkpatch.conf. But I don't want to side-track over this part. > >> If a U-Boot driver will be written for a device that does not have a >> driver yet in Linux, then the Linux driver will be written but with >> DT bindings incompatible with what was established in U-Boot, will you >> wake up the U-Boot developer from the grave and ask them to resync the >> driver to follow Linux? Or will you accept drivers at all for hardware >> that is not supported by Linux? > >What I've said for years (but yes, I've missed changes, maybe the yaml >dt binding stuff would help so I could make CI fail or at least require >manual override?) is that U-Boot will take immature bindings but it's on >the developer to re-sync once the bindings are fully reviewed. This is >to help with the chicken-and-egg problem. But old bindings are not >intended to be supported, once it's finalized. That is part of the >bargain. > >> I also think there are various degrees of what it means "to work" with a >> device tree provided directly by U-Boot. Distros like Arch Linux ARM >> have a package for device tree blobs, and it is expected that these are >> updated by the distro, and U-Boot just loads them. As Michael points out, >> the DT provided by U-Boot is just a fallback. The OS should boot to >> prompt and have a network connection to set itself up properly again. >> But we need to draw a harder line on what we _actually_ desire to work >> beyond that. > >Every distribution has a package for device tree binaries, because >that's how you get a device tree on the still vast majority of platforms >that don't ship one in-flash (RPis being the modern exception) and to my >knowledge none of them are happy about having to build and pass and make >sure the right one is used on a given board at boot. So yes, U-Boot >being able to pass a device tree on to the next stage is one of those >things to help everything Just Work and be boring. > >-- >Tom

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Do not stop bootloader loading using any key
by Fariya F 30 Aug '21

30 Aug '21

Hi, I am using uboot code 2016.03-gf92eba1 code base. I need to disable stopping of bootloader execution using any key(ctrl c or any key) I also need to set bootdelay to 0. How to do these 2 config changes so the bootloader boots without any user intervention Regards Fariya

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[PATCH] pwm: Add driver for cadence TTC
by Michal Simek 30 Aug '21

30 Aug '21

TTC has three modes of operations. Timer, PWM and input counters. There is already driver for timer under CADENCE_TTC_TIMER which is used for ZynqMP R5 configuration. This driver is targeting PWM which is for example configuration which can be used for fan control. The driver has been tested on Xilinx Kria SOM platform where fan is connected to one PL pin. When TTC output is connected via EMIO to PL pin TTC pwm can be configured and tested for example like this: pwm config 0 0 10000 1200 pwm enable 0 0 pwm config 0 0 10000 1400 pwm config 0 0 10000 1600 Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- MAINTAINERS | 1 + drivers/pwm/Kconfig | 7 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-cadence-ttc.c | 217 ++++++++++++++++++++++++++++++++++ 4 files changed, 226 insertions(+) create mode 100644 drivers/pwm/pwm-cadence-ttc.c diff --git a/MAINTAINERS b/MAINTAINERS index 4cf0c33c5d58..889813382249 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -600,6 +600,7 @@ F: drivers/mmc/zynq_sdhci.c F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c +F: drivers/pwm/pwm-cadence-ttc.c F: drivers/serial/serial_zynq.c F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index cf7f4c6840ce..176e703c8fbb 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -9,6 +9,13 @@ config DM_PWM frequency/period can be controlled along with the proportion of that time that the signal is high. +config PWM_CADENCE_TTC + bool "Enable support for the Cadence TTC PWM" + depends on DM_PWM && !CADENCE_TTC_TIMER + help + Cadence TTC can be configured as timer which is done via + CONFIG_CADENCE_TTC_TIMER or as PWM. This is covering only PWM now. + config PWM_CROS_EC bool "Enable support for the Chrome OS EC PWM" depends on DM_PWM diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 10d244bfb79d..abf5af41d2cc 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o +obj-$(CONFIG_PWM_CADENCE_TTC) += pwm-cadence-ttc.o obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o diff --git a/drivers/pwm/pwm-cadence-ttc.c b/drivers/pwm/pwm-cadence-ttc.c new file mode 100644 index 000000000000..1d007676bb3b --- /dev/null +++ b/drivers/pwm/pwm-cadence-ttc.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2021 Xilinx, Inc. Michal Simek + */ + +#include <clk.h> +#include <common.h> +#include <div64.h> +#include <dm.h> +#include <log.h> +#include <pwm.h> +#include <asm/io.h> +#include <log.h> +#include <div64.h> +#include <linux/math64.h> +#include <linux/log2.h> +#include <dm/device_compat.h> + +#define TTC_COUNTER_CONTROL_1 0xc +#define TTC_INTERVAL_COUNTER_1 0x24 +#define TTC_MATCH_1_COUNTER_1 0x30 + +#define CPWM_CLK_FALLING_EDGE 0x40 +#define CPWM_CLK_SRC_EXTERNAL 0x20 +#define CPWM_CLK_PRESCALE_SHIFT 1 +#define CPWM_CLK_PRESCALE_MASK (15 << 1) +#define CPWM_CLK_PRESCALE_ENABLE 1 + +#define CPWM_COUNTER_CTRL_WAVE_POL 0x40 +#define CPWM_COUNTER_CTRL_WAVE_DISABLE 0x20 +#define CPWM_COUNTER_CTRL_RESET 0x10 +#define CPWM_COUNTER_CTRL_MATCH_ENABLE 0x8 +#define CPWM_COUNTER_CTRL_DECREMENT_ENABLE 0x4 +#define CPWM_COUNTER_CTRL_INTERVAL_ENABLE 0x2 +#define CPWM_COUNTER_CTRL_COUNTING_DISABLE 0x1 + +struct cadence_ttc_pwm_priv { + uchar *regs; + unsigned long frequency; + bool invert[2]; +}; + +static int cadence_ttc_pwm_set_invert(struct udevice *dev, uint channel, + bool polarity) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + + if (channel > 2) { + dev_err(dev, "Unsupported channel number %d(max 2)\n", channel); + return -EINVAL; + } + + priv->invert[channel] = polarity; + + dev_dbg(dev, "polarity=%u. Please config PWM again\n", polarity); + + return 0; +} + +static int cadence_ttc_pwm_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + u32 counter_ctrl, x; + int period_clocks, duty_clocks, prescaler; + + dev_dbg(dev, "channel %d, duty %d/ period %d ns\n", channel, + duty_ns, period_ns); + + if (channel > 2) { + dev_err(dev, "Unsupported channel number %d(max 2)\n", channel); + return -EINVAL; + } + + /* Make sure counter is stopped */ + counter_ctrl = readl(priv->regs + TTC_COUNTER_CONTROL_1 + + (channel * 4)); + setbits_le32(priv->regs + TTC_COUNTER_CONTROL_1 + (channel * 4), + CPWM_COUNTER_CTRL_COUNTING_DISABLE); + + /* Calculate period, prescaler and set clock control register */ + period_clocks = div64_u64(((int64_t)period_ns * priv->frequency), + 1000000000LL); + + prescaler = ilog2(period_clocks) + 1 - 16; + if (prescaler < 0) + prescaler = 0; + + x = readl(priv->regs + (channel * 4)); + + if (!prescaler) { + x &= ~(CPWM_CLK_PRESCALE_ENABLE | CPWM_CLK_PRESCALE_MASK); + } else { + x &= ~CPWM_CLK_PRESCALE_MASK; + x |= CPWM_CLK_PRESCALE_ENABLE | + (((prescaler - 1) << CPWM_CLK_PRESCALE_SHIFT) & + CPWM_CLK_PRESCALE_MASK); + }; + + /* External source is not handled by this driver now */ + x &= ~CPWM_CLK_SRC_EXTERNAL; + + writel(x, priv->regs + (channel * 4)); + + /* Calculate interval and set counter control value */ + duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency), + 1000000000LL); + + writel((period_clocks >> prescaler) & 0xffff, + priv->regs + TTC_INTERVAL_COUNTER_1 + (channel * 4)); + writel((duty_clocks >> prescaler) & 0xffff, + priv->regs + TTC_MATCH_1_COUNTER_1 + (channel * 4)); + + /* Restore counter */ + counter_ctrl &= ~CPWM_COUNTER_CTRL_DECREMENT_ENABLE; + counter_ctrl |= CPWM_COUNTER_CTRL_INTERVAL_ENABLE | + CPWM_COUNTER_CTRL_RESET | + CPWM_COUNTER_CTRL_MATCH_ENABLE; + + if (priv->invert[channel]) + counter_ctrl |= CPWM_COUNTER_CTRL_WAVE_POL; + else + counter_ctrl &= ~CPWM_COUNTER_CTRL_WAVE_POL; + + writel(counter_ctrl, + priv->regs + TTC_COUNTER_CONTROL_1 + (channel * 4)); + + dev_dbg(dev, "%d/%d clocks, prescaler 2^%d\n", duty_clocks, + period_clocks, prescaler); + + return 0; +}; + +static int cadence_ttc_pwm_set_enable(struct udevice *dev, uint channel, + bool enable) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + + if (channel > 2) { + dev_err(dev, "Unsupported channel number %d(max 2)\n", channel); + return -EINVAL; + } + + dev_dbg(dev, "Enable: %d, channel %d\n", enable, channel); + + if (enable) { + clrbits_le32(priv->regs + TTC_COUNTER_CONTROL_1 + (channel * 4), + CPWM_COUNTER_CTRL_COUNTING_DISABLE | + CPWM_COUNTER_CTRL_WAVE_DISABLE); + setbits_le32(priv->regs + TTC_COUNTER_CONTROL_1 + (channel * 4), + CPWM_COUNTER_CTRL_RESET); + } else { + setbits_le32(priv->regs + TTC_COUNTER_CONTROL_1 + (channel * 4), + CPWM_COUNTER_CTRL_COUNTING_DISABLE | + CPWM_COUNTER_CTRL_WAVE_DISABLE); + } + + return 0; +}; + +static int cadence_ttc_pwm_of_to_plat(struct udevice *dev) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + + return 0; +} + +static int cadence_ttc_pwm_probe(struct udevice *dev) +{ + struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + priv->frequency = clk_get_rate(&clk); + if (IS_ERR_VALUE(priv->frequency)) { + dev_err(dev, "failed to get rate\n"); + return priv->frequency; + } + dev_dbg(dev, "Clk frequency: %ld\n", __func__, priv->frequency); + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + return 0; +} + +static const struct pwm_ops cadence_ttc_pwm_ops = { + .set_invert = cadence_ttc_pwm_set_invert, + .set_config = cadence_ttc_pwm_set_config, + .set_enable = cadence_ttc_pwm_set_enable, +}; + +static const struct udevice_id cadence_ttc_pwm_ids[] = { + { .compatible = "cdns,ttc" }, + { } +}; + +U_BOOT_DRIVER(cadence_ttc_pwm) = { + .name = "cadence_ttc_pwm", + .id = UCLASS_PWM, + .of_match = cadence_ttc_pwm_ids, + .ops = &cadence_ttc_pwm_ops, + .of_to_plat = cadence_ttc_pwm_of_to_plat, + .probe = cadence_ttc_pwm_probe, + .priv_auto = sizeof(struct cadence_ttc_pwm_priv), +}; -- 2.33.0

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