August 2021 - U-Boot

[PATCH v3 0/4] Support SiFive Composable cache driver
by Zong Li 31 Aug '21

31 Aug '21

This patch set contains the SiFive composable cache support, and indroduce an interface to do cache initialization, each platform can overwrite it by their own implementation. Changed in v3: - Combine some patches - Drop the subdirectories of vendor in lib/ - Rebase codebase Changed in v2: - Refine the ccache driver by Sean's suggestions - Introduce a common interface for cache initialization Zong Li (4): cache: add sifive composable cache driver riscv: lib: introduce a cache_init interface board: sifive: use ccache driver instead of helper function riscv: lib: modify the indent arch/riscv/Kconfig | 5 ++ arch/riscv/cpu/fu540/Kconfig | 2 + arch/riscv/cpu/fu540/Makefile | 1 - arch/riscv/cpu/fu540/cache.c | 55 ----------------- arch/riscv/cpu/fu740/Kconfig | 2 + arch/riscv/cpu/fu740/Makefile | 1 - arch/riscv/cpu/fu740/cache.c | 55 ----------------- arch/riscv/include/asm/arch-fu540/cache.h | 14 ----- arch/riscv/include/asm/arch-fu740/cache.h | 14 ----- arch/riscv/include/asm/cache.h | 3 +- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/cache.c | 5 ++ arch/riscv/lib/sifive_cache.c | 27 ++++++++ board/sifive/unleashed/unleashed.c | 12 +--- board/sifive/unmatched/unmatched.c | 11 +--- drivers/cache/Kconfig | 7 +++ drivers/cache/Makefile | 1 + drivers/cache/cache-sifive-ccache.c | 75 +++++++++++++++++++++++ 18 files changed, 131 insertions(+), 160 deletions(-) delete mode 100644 arch/riscv/cpu/fu540/cache.c delete mode 100644 arch/riscv/cpu/fu740/cache.c delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h create mode 100644 arch/riscv/lib/sifive_cache.c create mode 100644 drivers/cache/cache-sifive-ccache.c -- 2.32.0

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[PATCH v4 0/4] Support SiFive Composable cache driver
by Zong Li 31 Aug '21

31 Aug '21

This patch set contains the SiFive composable cache support, and uses this driver to enable the ways of ccache by overwriting the enable_caches. Changed in v4: - Use generic enable_caches(), rather than cache_init(). - Rebase code base to v2021.10-rc3 Changed in v3: - Combine some patches - Drop the subdirectories of vendor in lib/ - Rebase codebase Changed in v2: - Refine the ccache driver by Sean's suggestions - Introduce a common interface for cache initialization Zong Li (4): cache: add sifive composable cache driver riscv: lib: implement enable_caches for sifive cache board: sifive: use ccache driver instead of helper function riscv: lib: modify the indent arch/riscv/Kconfig | 5 ++ arch/riscv/cpu/fu540/Kconfig | 2 + arch/riscv/cpu/fu540/Makefile | 1 - arch/riscv/cpu/fu540/cache.c | 55 ----------------- arch/riscv/cpu/fu740/Kconfig | 2 + arch/riscv/cpu/fu740/Makefile | 1 - arch/riscv/cpu/fu740/cache.c | 55 ----------------- arch/riscv/include/asm/arch-fu540/cache.h | 14 ----- arch/riscv/include/asm/arch-fu740/cache.h | 14 ----- arch/riscv/include/asm/cache.h | 2 +- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/sifive_cache.c | 27 ++++++++ board/sifive/unleashed/unleashed.c | 10 +-- board/sifive/unmatched/unmatched.c | 11 +--- common/board_r.c | 4 +- drivers/cache/Kconfig | 7 +++ drivers/cache/Makefile | 1 + drivers/cache/cache-sifive-ccache.c | 75 +++++++++++++++++++++++ 18 files changed, 128 insertions(+), 159 deletions(-) delete mode 100644 arch/riscv/cpu/fu540/cache.c delete mode 100644 arch/riscv/cpu/fu740/cache.c delete mode 100644 arch/riscv/include/asm/arch-fu540/cache.h delete mode 100644 arch/riscv/include/asm/arch-fu740/cache.h create mode 100644 arch/riscv/lib/sifive_cache.c create mode 100644 drivers/cache/cache-sifive-ccache.c -- 2.32.0

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[PATCH v2 0/4] Add octal DTR support for Macronix flash
by JaimeLiao 31 Aug '21

31 Aug '21

This series add support for Macronix octal DTR flash, add second time Softreset with "INVERT" command extension type and follow linux kernel to enable 4byte opcode when possible. JaimeLiao (4): mtd: spi-nor: macronix: add support for Macronix Octal flash mtd: spi-nor-core: Adding different type of command extension in Soft Reset mtd: spi-nor-core: set 4byte opcode when possible mtd: spi-nor-core: Add support for Macronix Octal flash drivers/mtd/spi/spi-nor-core.c | 117 +++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi-nor-ids.c | 22 ++++++- include/linux/mtd/spi-nor.h | 13 +++- 3 files changed, 149 insertions(+), 3 deletions(-) -- 2.17.1

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efi_loader: Omit memory with "no-map" when returning memory
by Kristian Amlie 31 Aug '21

31 Aug '21

Since I'm not very experienced with EFI internals, this is part patch submission, part question. Does it seem correct? At least according to comments I could find in the code, it should work like this. See patch. -- Kristian

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[PATCH 1/2] arm: a37xx: pci: Disable returning CRS response
by Pali Rohár 31 Aug '21

31 Aug '21

There was mistake in commit 4cd61c43fd51 ("arm: a37xx: pci: Fix handling PIO config error responses"). U-Boot does not support handling of CRS return value for PCI_VENDOR_ID config read request and also does not set CRSSVE bit. Therefore disable returning CRS response for now. Signed-off-by: Pali Rohár <pali(a)kernel.org> Fixes: 4cd61c43fd51 ("arm: a37xx: pci: Fix handling PIO config error responses") --- drivers/pci/pci-aardvark.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 815b26162f15..d3ef8f203d97 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -358,7 +358,18 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } - allow_crs = (offset == PCI_VENDOR_ID) && (size == 4); + /* + * Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to + * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and + * only when CRSSVE bit in Root Port PCIe device is enabled. In all + * other error PCIe Root Complex must return all-ones. + * Aardvark HW does not have Root Port PCIe device and U-Boot does not + * implement emulation of this device. + * U-Boot currently does not support handling of CRS return value for + * PCI_VENDOR_ID config read request and also does not set CRSSVE bit. + * Therefore disable returning CRS response for now. + */ + allow_crs = false; if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev, -- 2.20.1

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Re: [PATCH] Convert CONFIG_SYS_MALLOC_LEN to Kconfig
by Rick Chen 31 Aug '21

31 Aug '21

> From: U-Boot <u-boot-bounces(a)lists.denx.de> On Behalf Of Tom Rini > Sent: Sunday, August 29, 2021 9:35 AM > To: u-boot(a)lists.denx.de > Subject: [PATCH] Convert CONFIG_SYS_MALLOC_LEN to Kconfig > > This converts the following to Kconfig: > CONFIG_SYS_MALLOC_LEN > > Signed-off-by: Tom Rini <trini(a)konsulko.com> > --- For riscv, Reviewed-by: Rick Chen <rick(a)andestech.com>

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[PATCH] board/imx6sabresd: add the option of imx6solo during FIT matching
by jiladahe1997＠gmail.com 31 Aug '21

31 Aug '21

From 934d43a647bfee33f32f710500c75ef2490f25f6 Mon Sep 17 00:00:00 2001 From: Mingrui Ren <jiladahe1997(a)gmail.com> Date: Mon, 30 Aug 2021 20:35:11 +0800 Subject: [PATCH] board/imx6sabresd: add imx6solo during FIT matching When using imx6solo cpu, the 'board_fit_config_name_match' function will return -1, then u-boot will choose wrong FIT, and causing further problems. imx6solo is similar to imx6dl, so I just add it into imx6dl. Signed-off-by: Mingrui Ren <jiladahe1997(a)gmail.com> --- board/freescale/mx6sabresd/mx6sabresd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 8c35230855..0bd968411e 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -928,7 +928,7 @@ int board_fit_config_name_match(const char *name) } else if (is_mx6dqp()) { if (!strcmp(name, "imx6qp-sabresd")) return 0; - } else if (is_mx6dl()) { + } else if (is_mx6dl() || is_mx6solo()) { if (!strcmp(name, "imx6dl-sabresd")) return 0; } -- 2.25.1

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am335x_spl_bch - SPL NAND loading hang on power on only
by Kevin Baker 31 Aug '21

31 Aug '21

Hi all, I am working on updating our version of u-boot, and came across something weird - the SPL hangs after "Trying to load NAND" on the first power-on boot, but after a watchdog reset or power-on reset, the NAND works fine. U-Boot SPL 2021.01-00010-g8c91cf967b-dirty (Aug 30 2021 - 19:03:45 -0500) Trying to boot from NAND <<<< hangs here until watchdog reset After checking more common issues - pinmux/config/timing/NAND connections, etc. and printf-tracing it, it is actually hanging after board_nand_init and at this call to select_chip before getting to NAND_CMD_RESET: drivers/mtd/nand/raw/am335x_spl_bch.c: nand_init() ... board_nand_init(&nand_chip); if (nand_chip.select_chip) nand_chip.select_chip(mtd, 0); <<<< stuck here ??? <<<< /* NAND chip may require reset after power-on */ nand_command(0, 0, 0, NAND_CMD_RESET); ... Somehow, the first power up, nand_chip.select_chip is set to 0xFFFFFFFF, so it hangs at that point. Whereas future power-on resets have the location cleared to 0, so it works fine... Explicitly setting select_chip to NULL in the call to board_nand_init for omap_gpmc makes everything work fine: drivers/mtd/nand/raw/omap_gpmc.c: board_nand_init() ... writel(gpmc_config, &gpmc_cfg->config) + nand->select_chip = NULL; + nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; ... But now I am worried about other things not being cleared out properly at reset... The am335x SPL NAND driver is pretty old and presumably well-tested code, so I was kinda surprised at this fix working. Would anyone know if a configuration setting, compiler setting or similar contributes to this? Or is it some artifact of the power-up state of the board? Is there a better way of 'clearing' the static nand_chip struct in am335x_spl_bch.c, or is there really a missing setup of this function pointer somewhere for am335x_spl_bch/omap_gpmc? This is against TI's u-boot @ d77252021a85c72d7ff9a4e151b81c4b4b9e1205 , with a Variscite VAR-SOM-AM33 module. Just wanted to check with the list to see if I am missing something... Thanks, Kevin

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[PATCH V3] ARM: rmobile: beacon-renesom: Enable QSPI NOR Flash
by Adam Ford 31 Aug '21

31 Aug '21

There is a QSPI NOR flash part on the board. Because this chip isn't yet supported in Linux, but it is supported in U-Boot, and the face that the RPC_SPI compatible names are different in U-Boot and Linux, the device tree updates are confined to -u-boot.dtsi files. In order to use the QSPI, TF-A must leave RPC unlocked by compiling TF-A with RZG_RPC_HYPERFLASH_LOCKED=0. Signed-off-by: Adam Ford <aford173(a)gmail.com> Reviewed-by: Biju Bas <biju.das.jz(a)bp.renesas.com> --- V3: Rebase, and combine into som.dsti file V2: Add note to commit message about TF-A No functional changes diff --git a/arch/arm/dts/beacon-renesom-som.dtsi b/arch/arm/dts/beacon-renesom-som.dtsi index 9565495b49..d30bab3c8b 100644 --- a/arch/arm/dts/beacon-renesom-som.dtsi +++ b/arch/arm/dts/beacon-renesom-som.dtsi @@ -7,6 +7,10 @@ #include <dt-bindings/clk/versaclock.h> / { + aliases { + spi0 = &rpc; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -275,6 +279,25 @@ }; }; +&rpc { + compatible = "renesas,rcar-gen3-rpc"; + num-cs = <1>; + spi-max-frequency = <40000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + &scif_clk { clock-frequency = <14745600>; }; diff --git a/configs/r8a774a1_beacon_defconfig b/configs/r8a774a1_beacon_defconfig index 23c423060d..7ba4ac05f5 100644 --- a/configs/r8a774a1_beacon_defconfig +++ b/configs/r8a774a1_beacon_defconfig @@ -18,7 +18,9 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -47,6 +49,10 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y @@ -56,6 +62,9 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/r8a774b1_beacon_defconfig b/configs/r8a774b1_beacon_defconfig index 034ed219e2..44528cd2e1 100644 --- a/configs/r8a774b1_beacon_defconfig +++ b/configs/r8a774b1_beacon_defconfig @@ -18,7 +18,9 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -48,6 +50,10 @@ CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_RENESAS_SDHI=y CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_BITBANGMII=y CONFIG_PHY_REALTEK=y @@ -61,6 +67,9 @@ CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_RENESAS_RPC_SPI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/r8a774e1_beacon_defconfig b/configs/r8a774e1_beacon_defconfig index a6e1ea0e16..9cde39f467 100644 --- a/configs/r8a774e1_beacon_defconfig +++ b/configs/r8a774e1_beacon_defconfig @@ -18,7 +18,9 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -47,6 +49,10 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y @@ -56,6 +62,9 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y -- 2.25.1

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[PATCH] Kconfig: Use spaces not tabs in Kconfig entires
by Tom Rini 30 Aug '21

30 Aug '21

While the Kconfig language seems to accept either form of whitespace, we use a space throughout the project, except in these spots. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- arch/arm/mach-exynos/Kconfig | 2 +- board/freescale/mx6memcal/Kconfig | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 0b4276c03628..7df0e176179d 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -141,7 +141,7 @@ if ARCH_EXYNOS7 choice prompt "EXYNOS7 board select" -config TARGET_ESPRESSO7420 +config TARGET_ESPRESSO7420 bool "ESPRESSO7420 board" select ARM64 select ARMV8_MULTIENTRY diff --git a/board/freescale/mx6memcal/Kconfig b/board/freescale/mx6memcal/Kconfig index 9987cba5dcb7..481403ae855d 100644 --- a/board/freescale/mx6memcal/Kconfig +++ b/board/freescale/mx6memcal/Kconfig @@ -87,12 +87,12 @@ choice help Select the type of DDR (DDR3 or LPDDR2) used on your design -config DDR3 +config DDR3 bool "DDR3" help Select this if your board design uses DDR3. -config LPDDR2 +config LPDDR2 bool "LPDDR2" help Select this if your board design uses LPDDR2. -- 2.17.1

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