July 2021 - U-Boot

[PATCH v2 0/3] Add MRMAC driver support
by Ashok Reddy Soma 02 Jul '21

02 Jul '21

This patch set adds Xilinx AXI Multirate MAC(MRMAC) driver support. This MRMAC is a high performance, low latency, adaptable Ethernet integrated hard IP. This can be configured up to four ports with MAC rates from 10GE to 100GE. Supported Configuration Combinations: 1 × 100GE 2 × 50GE 1 × 40GE 4 × 25GE 4 × 10GE Currently added support and tested below configurations in the driver: 4 × 25GE 4 × 10GE Changes in v2: - Changed all static allocations to dynamic and freed them. - Used setbits_le32 and clrbits_le32 wherever applicable - All return's are changed to proper error codes instead of 1 or -1 - Changed return type of isrxready() from int to bool - Changed all printf's to log_warning, and debug to log_debug - Added function headers with desciption - Changed all capital hex numbers to small hex numbers Ashok Reddy Soma (3): net: ethtool: Add ethernet speed macros for higher speeds net: xilinx: axi_mrmac: Add MRMAC driver xilinx: versal: Enable Xilinx AXI MRMAC MAINTAINERS | 1 + configs/xilinx_versal_virt_defconfig | 1 + drivers/net/Kconfig | 9 + drivers/net/Makefile | 1 + drivers/net/xilinx_axi_emac.c | 2 +- drivers/net/xilinx_axi_mrmac.c | 564 +++++++++++++++++++++++++++ drivers/net/xilinx_axi_mrmac.h | 203 ++++++++++ include/linux/ethtool.h | 8 + 8 files changed, 788 insertions(+), 1 deletion(-) create mode 100644 drivers/net/xilinx_axi_mrmac.c create mode 100644 drivers/net/xilinx_axi_mrmac.h -- 2.17.1

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[PATCH 0/9] phyCORE-i.MX8MP Update
by Teresa Remmet 02 Jul '21

02 Jul '21

Hello, this patchstack includes phyCORE-i.MX8MP updates and the switch to binman. But also resynced the imx8mp.dtsi from kernel add introduced a common imx8mp-u-boot.dtsi Teresa Teresa Remmet (9): arm: dts: imx8mp: Resync imx8mp device tree include arm: dts: imx8mp: Add common u-boot dtsi arm: dts: imx8mp-phyboard-pollux: Sync dts files with kernel board: phytec: phycore_imx8mp: Change debug UART board: phytec: phycore_imx8mp: Add fec support board: phytec: phycore_imx8mp: Set VDD_ARM to 0,95V board: phytec: phycore-imx8mp: Enable DVS1 control arm: dts: imx8mp-phyboard-pollux-rdk-u-boot: Add wdog pinctrl entry board: phytec: imx8mp-phycore: Switch to binman arch/arm/dts/imx8mp-evk-u-boot.dtsi | 39 +---- .../imx8mp-phyboard-pollux-rdk-u-boot.dtsi | 152 +++++++++++++----- arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts | 58 ++++++- arch/arm/dts/imx8mp-phycore-som.dtsi | 2 +- arch/arm/dts/imx8mp-u-boot.dtsi | 42 +++++ arch/arm/dts/imx8mp.dtsi | 146 ++++++++++++++++- arch/arm/mach-imx/imx8m/Kconfig | 1 + .../phytec/phycore_imx8mp/imximage-8mp-sd.cfg | 10 ++ board/phytec/phycore_imx8mp/phycore-imx8mp.c | 14 ++ board/phytec/phycore_imx8mp/spl.c | 23 ++- configs/phycore-imx8mp_defconfig | 12 +- include/configs/phycore_imx8mp.h | 29 +++- 12 files changed, 430 insertions(+), 98 deletions(-) create mode 100644 arch/arm/dts/imx8mp-u-boot.dtsi create mode 100644 board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg -- 2.25.1

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[PATCH v2] board: sl28: add DSA support for variant 2
by Michael Walle 02 Jul '21

02 Jul '21

Now that u-boot gained DSA support, and it is already enabled for the kontron_sl28 board, add the last missing piece and enable the corresponding devices it in the device tree. Signed-off-by: Michael Walle <michael(a)walle.cc> --- changes since v1: - renamed ethernet alias stem, because it was changed in commit 82a3c9ef20d43d97416589854b4bbcb4c2450c24 ("net: use the same alias stem for ethernet as linux") Now that the mentioned commit made it finally into u-boot. We can move forward here. It would be nice if this would still make it into 2021.07, given that this is only a device tree change for a this particular board. .../fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi | 7 ++++ .../arm/dts/fsl-ls1028a-kontron-sl28-var2.dts | 40 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi index 79b771e074..4e0ce3f77d 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi @@ -1,2 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ #include "fsl-ls1028a-kontron-sl28-u-boot.dtsi" + +/ { + aliases { + ethernet0 = &mscc_felix_port0; + ethernet1 = &mscc_felix_port1; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts index 1ea1265bcf..7a3aa21408 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts @@ -22,4 +22,44 @@ /delete-property/ phy-handle; }; +&enetc2 { + status = "okay"; +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + label = "gbe0"; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + status = "okay"; +}; + +&mscc_felix_port1 { + label = "gbe1"; + phy-handle = <&phy1>; + phy-mode = "sgmii"; + status = "okay"; +}; + +&mscc_felix_port4 { + ethernet = <&enetc2>; + status = "okay"; +}; + /delete-node/ &phy0; +&mdio0 { + phy0: ethernet-phy@5 { + reg = <0x5>; + eee-broken-1000t; + eee-broken-100tx; + }; + + phy1: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + }; +}; -- 2.20.1

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[PATCH 1/3 v3] efi: Fix to use null handle to create new handle for efi_fmp_raw
by Ilias Apalodimas 02 Jul '21

02 Jul '21

From: Masami Hiramatsu <masami.hiramatsu(a)linaro.org> When running the efidebug capsule disk-update command, the efi_fmp_raw protocol installation fails with 2 (EFI_INVALID_PARAMETER) as below. This is because the code passes efi_root instead of the handle local var. => efidebug capsule disk-update EFI: Call: efi_install_multiple_protocol_interfaces( &handle, &efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL) EFI: Entry efi_install_multiple_protocol_interfaces(00000000fbaf5988) EFI: Call: efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface) EFI: Entry efi_install_protocol_interface(00000000fbaf5988, 86c77a67-0b97-4633-a187-49104d0685c7, 0, 00000000fbfa6ee8) EFI: new handle 00000000fbb37520 EFI: Exit: efi_install_protocol_interface: 0 EFI: 0 returned by efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface) EFI: Exit: efi_install_multiple_protocol_interfaces: 0 EFI: 0 returned by efi_install_multiple_protocol_interfaces( &handle, &efi_guid_firmware_management_protocol, &efi_fmp_fit, NULL) EFI: Call: efi_install_multiple_protocol_interfaces( &efi_root, &efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL) EFI: Entry efi_install_multiple_protocol_interfaces(00000000fbfec648) EFI: Call: efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface) EFI: Entry efi_install_protocol_interface(00000000fbfec648, 86c77a67-0b97-4633-a187-49104d0685c7, 0, 00000000fbfa6f18) EFI: handle 00000000fbaf8520 EFI: Exit: efi_install_protocol_interface: 2 EFI: 2 returned by efi_install_protocol_interface( handle, protocol, EFI_NATIVE_INTERFACE, protocol_interface) EFI: Exit: efi_install_multiple_protocol_interfaces: 2 EFI: 2 returned by efi_install_multiple_protocol_interfaces( &efi_root, &efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL) Command failed, result=1 To fix this issue, pass the handle local var which is set NULL right before installing efi_fmp_raw as same as the installing efi_fmp_fit. (In both cases, the local reference to the handle will be just discarded) Signed-off-by: Masami Hiramatsu <masami.hiramatsu(a)linaro.org> Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> --- Changes since v2: - Updated commit description Changes since v1: - lib/efi_loader/efi_capsule.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 60309d4a07d0..cc6ed453ed21 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -940,7 +940,7 @@ efi_status_t __weak arch_efi_load_capsule_drivers(void) if (IS_ENABLED(CONFIG_EFI_CAPSULE_FIRMWARE_RAW)) { handle = NULL; ret = EFI_CALL(efi_install_multiple_protocol_interfaces( - &efi_root, + &handle, &efi_guid_firmware_management_protocol, &efi_fmp_raw, NULL)); } -- 2.32.0.rc0

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32bit GRUB on RISC-V
by Heinrich Schuchardt 02 Jul '21

02 Jul '21

Hello Tom, the RISC-V platform specification has a profile OS-A for running rich operating systems like Linux and BSD. This profile requires 64bit and UEFI conforming to the EBBR. Only the 'embedded' profile may use 32bit. This obsoletes 32bit GRUB on RISC-V. Best regards Heinrich

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[PATCH 1/3] usb: ehci-mx6: move mode set/detect to probe
by Tim Harvey 02 Jul '21

02 Jul '21

There is no need to set and/or detect mode in of_to_plat and accessing phy registers at that point before device power domain and clock are enabled will cause hangs on platforms such as IMX8M Mini. Move the mode set/detect from of_to_plat into the probe and remove the unnecessary of_to_plat. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- drivers/usb/host/ehci-mx6.c | 42 ++++++++++++++----------------------- 1 file changed, 16 insertions(+), 26 deletions(-) diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 06be9deaaa..c2dfe49012 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -539,28 +539,6 @@ static int ehci_usb_phy_mode(struct udevice *dev) return 0; } -static int ehci_usb_of_to_plat(struct udevice *dev) -{ - struct usb_plat *plat = dev_get_plat(dev); - enum usb_dr_mode dr_mode; - - dr_mode = usb_get_dr_mode(dev_ofnode(dev)); - - switch (dr_mode) { - case USB_DR_MODE_HOST: - plat->init_type = USB_INIT_HOST; - break; - case USB_DR_MODE_PERIPHERAL: - plat->init_type = USB_INIT_DEVICE; - break; - case USB_DR_MODE_OTG: - case USB_DR_MODE_UNKNOWN: - return ehci_usb_phy_mode(dev); - }; - - return 0; -} - static int mx6_parse_dt_addrs(struct udevice *dev) { #if !defined(CONFIG_PHY) @@ -623,7 +601,6 @@ static int ehci_usb_probe(struct udevice *dev) struct usb_plat *plat = dev_get_plat(dev); struct usb_ehci *ehci = dev_read_addr_ptr(dev); struct ehci_mx6_priv_data *priv = dev_get_priv(dev); - enum usb_init_type type = plat->init_type; struct ehci_hccr *hccr; struct ehci_hcor *hcor; int ret; @@ -641,7 +618,6 @@ static int ehci_usb_probe(struct udevice *dev) return ret; priv->ehci = ehci; - priv->init_type = type; #if CONFIG_IS_ENABLED(CLK) ret = clk_get_by_index(dev, 0, &priv->clk); @@ -657,6 +633,21 @@ static int ehci_usb_probe(struct udevice *dev) mdelay(1); #endif + switch (usb_get_dr_mode(dev_ofnode(dev))) { + case USB_DR_MODE_HOST: + plat->init_type = USB_INIT_HOST; + break; + case USB_DR_MODE_PERIPHERAL: + plat->init_type = USB_INIT_DEVICE; + break; + case USB_DR_MODE_OTG: + case USB_DR_MODE_UNKNOWN: + ret = ehci_usb_phy_mode(dev); + if (ret) + return ret; + }; + priv->init_type = plat->init_type; + #if CONFIG_IS_ENABLED(DM_REGULATOR) ret = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_supply); @@ -680,7 +671,7 @@ static int ehci_usb_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->vbus_supply) { ret = regulator_set_enable(priv->vbus_supply, - (type == USB_INIT_DEVICE) ? + (priv->init_type == USB_INIT_DEVICE) ? false : true); if (ret && ret != -ENOSYS) { printf("Error enabling VBUS supply (ret=%i)\n", ret); @@ -764,7 +755,6 @@ U_BOOT_DRIVER(usb_mx6) = { .name = "ehci_mx6", .id = UCLASS_USB, .of_match = mx6_usb_ids, - .of_to_plat = ehci_usb_of_to_plat, .probe = ehci_usb_probe, .remove = ehci_usb_remove, .ops = &ehci_usb_ops, -- 2.17.1

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[PATCH] powerpc: fix regression in arch_initr_trap()
by Matt Merhar 01 Jul '21

01 Jul '21

The assembly output of the arch_initr_trap() function differed by a single byte after common.h was removed from traps.c: fff49a18 <arch_initr_trap>: fff49a18: 94 21 ff f0 stwu r1,-16(r1) fff49a1c: 7c 08 02 a6 mflr r0 fff49a20: 90 01 00 14 stw r0,20(r1) -fff49a24: 80 62 00 44 lwz r3,68(r2) +fff49a24: 80 62 00 38 lwz r3,56(r2) fff49a28: 4b ff 76 19 bl fff41040 <trap_init> fff49a2c: 80 01 00 14 lwz r0,20(r1) fff49a30: 38 60 00 00 li r3,0 fff49a34: 38 21 00 10 addi r1,r1,16 fff49a38: 7c 08 03 a6 mtlr r0 This was causing a consistent hard lockup during the MMC read / loading of the QoriQ FMan firmware on a P2041RDB board. Re-adding the header causes identical assembly to be emitted and allows the firmware loading and subsequent boot to succeed. Fixes: 401d1c4f5d ("common: Drop asm/global_data.h from common header") Signed-off-by: Matt Merhar <mattmerhar(a)protonmail.com> --- arch/powerpc/lib/traps.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/lib/traps.c b/arch/powerpc/lib/traps.c index c7bce82a44..ab8ca269a5 100644 --- a/arch/powerpc/lib/traps.c +++ b/arch/powerpc/lib/traps.c @@ -4,6 +4,7 @@ * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. */ +#include <common.h> #include <init.h> #include <asm/global_data.h> -- 2.25.1

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[GIT PULL] xilinx patches for v2021.10
by Michal Simek 01 Jul '21

01 Jul '21

Hi, please pull these patches to your tree (next). There are a lot of DT syncup changes which are also going to Linux kernel. CI loop doesn't show any problem. BTW: Isn't there any option in CI not to run builds against the same sha1? Because I see build for the branch itself and then for the tag which is kind of wasting of resources. Thanks, Michal The following changes since commit 1ce892cb1ce970d8ee6ffcecc22351c84e67fca4: azure: Use msys2 20210604 installer for Windows build (2021-06-22 09:06:03 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2021.10 for you to fetch changes up to 45576273e9209309238f332c85a6fef955c49b59: xilinx: zynqmp: Add support for 67dr silicon (2021-07-01 09:25:06 +0200) ---------------------------------------------------------------- Xilinx changes for v2021.10 clk: - Add driver for Xilinx Clocking Wizard IP fdt: - Also record architecture in /fit-images net: - Fix plat/priv data handling in axi emac - Add support for 10G/25G speeds pca953x: - Add missing dependency on i2c serial: - Fix dependencies for DEBUG uart for pl010/pl011 - Add setconfig option for cadence serial driver watchdog: - Add cadence wdt expire now function zynq: - Update DT bindings to reflect the latest state and descriptions zynqmp: - Update DT bindings to reflect the latest state and descriptions - SPL: Add support for ECC DRAM initialization - Fix R5 core 1 handling logic - Enable firmware driver for mini configurations - Enable secure boot, regulators, wdt - Add support xck devices and 67dr - Add psu init for sm/smk-k26 SOMs - Add handling for MMC seq number via mmc_get_env_dev() - Handle reserved memory locations - Add support for u-boot.itb generation for secure OS - Handle BL32 handoffs for secure OS - Add support for 64bit addresses for u-boot.its generation - Change eeprom handling via nvmem aliases ---------------------------------------------------------------- Ashok Reddy Soma (3): arm64: zynqmp: Fix application loading on R5 core1 net: xilinx: axi_emac: Cleanup of of_to_plat() net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet Jorge Ramirez-Ortiz (1): zynqmp: spl: support DRAM ECC initialization Kunihiko Hayashi (1): serial: zynq: Add support for serial parameters Michal Simek (44): gpio: pca953x: Add missing i2c dependency ARM: zynq: Convert at25 binding to new description on zc770-xm013 ARM: zynq: Fix OCM mapping to be aligned with binding on zc702 arm64: zynqmp: Enable EFI secure boot arm64: zynqmp: Add support for SVD devices arm64: zynqmp: Enable gpio driver for zcu1275/zcu1285 ARM: zynq: Rename bus to be align with simple-bus yaml arm64: zynqmp: Add psu_init_gpl for k26 boards arm64: zynqmp: Handle MMC seq number based on boot device arm64: zynqmp: Update psgtr clocks index for boards arm64: zynqmp: Disable CCI by default arm64: zynqmp: Add reset description for sata arm64: zynqmp: Move DP nodes to the end of file (zcu106) arm64: zynqmp: Add label for zynqmp_ipi arm64: zynqmp: Update Copyright years to 2021 zynqmp: Enable regulators zynqmp: Do not place u-boot to reserved memory location zynqmp: Generate u-boot.its also with TEE dynamically zynqmp: Pass bl32 entry to TF-A via xilinx handoff structure zynqmp: Remove u-boot,dm-pre-reloc for uart instances arm64: zynqmp: Remove additional header from zc1232 DT arm64: zynqmp: Add maximum-speed property for dwc3 nodes arm64: zynqmp: Remove addition newline from zc1751 dc1 arm64: zynqmp: Remove unused dp_aclk clock arm64: zynqmp: Sync dp port location on zc1751 dc4 arm64: zynqmp: Sync psgtr location on zcu100/zcu106 xilinx: Convert xlnx,eeprom property to nvmem alias arm64: zynqmp: Remove si5328 and si5382 nodes arm64: zynqmp: Remove can aliases from zc1751 arm64: zynqmp: Remove unused property from SD/USB arm64: zynqmp: Remove information about dma clock on zcu106 arm64: zynqmp: Sync psgtr location on zcu104/zcu111/zc1751-dc1 arm64: zynqmp: Add support for 64bit addresses in its arm64: zynqmp: Remove revA compatibility string from kv260 revB/1 arm64: zynqmp: Use overlay sugar syntax for Kria SOM arm64: zynqmp: Update usb dwc3 DT description arm64: zynqmp: Enable USB3.0 for dc2/dc3 arm64: zynqmp: Remove gpio from aliases list arm64: zynqmp: Add psgtr description to zc1751 dc1 board arm64: zynqmp: Add missing year in Kria dts files spl: fit: Also record architecture in /fit-images serial: Add additional depencies for PL010 and PL011 drivers arm64: zynqmp: Enable WDT command watchdog: cadence: Add expire_now method Piyush Mehta (1): arm64: dts: zynqmp: Add psgtr and phy entry for USB and SATA node Srinivas Neeli (1): arm64: zynqmp: rtc: Update rtc calibration value Stefano Stabellini (1): arm64: zynqmp: Add missing SMID for pcie to zynqmp.dtsi T Karthik Reddy (2): arm64: xilinx: Set CONFIG_ZYNQMP_FIRMWARE config for mini emmc xilinx: zynqmp: Add support for 67dr silicon Zhengxun (1): clk: zynq: Add clock wizard driver arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts | 2 +- arch/arm/dts/zynq-7000.dtsi | 2 +- arch/arm/dts/zynq-syzygy-hub.dts | 2 +- arch/arm/dts/zynq-zc702.dts | 6 + arch/arm/dts/zynq-zc770-xm013.dts | 7 +- arch/arm/dts/zynqmp-a2197-revA.dts | 4 +- arch/arm/dts/zynqmp-clk-ccf.dtsi | 9 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 4 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 4 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 5 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 5 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 5 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 6 +- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 594 +++++++++++++++++++++++++++++++++++++++++----------------------------------------------- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 575 ++++++++++++++++++++++++++++++++++++++++--------------------------------------------- arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 7 +- arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi | 2 +- arch/arm/dts/zynqmp-smk-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 1 - arch/arm/dts/zynqmp-zc1232-revA.dts | 3 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 22 ++-- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 7 +- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 41 ++++++- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 21 ++-- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 3 +- arch/arm/dts/zynqmp-zcu100-revC.dts | 11 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 15 +-- arch/arm/dts/zynqmp-zcu104-revA.dts | 23 ++-- arch/arm/dts/zynqmp-zcu104-revC.dts | 24 ++-- arch/arm/dts/zynqmp-zcu106-revA.dts | 49 +++----- arch/arm/dts/zynqmp-zcu111-revA.dts | 15 +-- arch/arm/dts/zynqmp-zcu1275-revA.dts | 6 +- arch/arm/dts/zynqmp-zcu1275-revB.dts | 6 +- arch/arm/dts/zynqmp-zcu1285-revA.dts | 6 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 12 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 12 +- arch/arm/dts/zynqmp.dtsi | 38 ++++-- arch/arm/mach-zynqmp/Kconfig | 35 ++++++ arch/arm/mach-zynqmp/Makefile | 1 + arch/arm/mach-zynqmp/ecc_spl_init.c | 163 ++++++++++++++++++++++++ arch/arm/mach-zynqmp/handoff.c | 19 ++- arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h | 13 ++ arch/arm/mach-zynqmp/include/mach/hardware.h | 2 + arch/arm/mach-zynqmp/mkimage_fit_atf.sh | 59 ++++++++- arch/arm/mach-zynqmp/mp.c | 70 ++++++----- arch/arm/mach-zynqmp/spl.c | 4 + board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c | 673 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/xilinx/zynqmp/zynqmp-smk-k26-revA | 1 + board/xilinx/zynqmp/zynqmp.c | 89 +++++++++++++- common/fdt_support.c | 4 +- common/spl/spl_fit.c | 3 +- configs/xilinx_versal_mini_emmc0_defconfig | 1 + configs/xilinx_versal_mini_emmc1_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 6 + drivers/clk/Kconfig | 11 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-xlnx-clock-wizard.c | 186 ++++++++++++++++++++++++++++ drivers/gpio/Kconfig | 2 +- drivers/net/xilinx_axi_emac.c | 193 +++++++++++++++++++++-------- drivers/serial/Kconfig | 4 +- drivers/serial/serial_zynq.c | 68 +++++++++++ drivers/watchdog/cdns_wdt.c | 41 ++++++- include/fdt_support.h | 3 +- 66 files changed, 2295 insertions(+), 918 deletions(-) create mode 100644 arch/arm/mach-zynqmp/ecc_spl_init.c create mode 100644 arch/arm/mach-zynqmp/include/mach/ecc_spl_init.h create mode 100644 board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c create mode 120000 board/xilinx/zynqmp/zynqmp-smk-k26-revA create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

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[PATCH 5/7] stm32mp: cmd_stm32key: add get_misc_dev function
by Hexagon Email Recovery 01 Jul '21

01 Jul '21

This message could not be delivered immediately due to an internal mail routing issue. The mail routing error has been resolved in the meantime. We apologize for the delay in delivery and any inconvenience this may have caused. In case of any questions please contact us via it(a)hexagon.com. Original sender: patrick.delaunay(a)foss.st.com Original delivery time: 28-Jun-2021 01:34 PM (UTC) ----------------------------------------------------------------------------------------------------------------------- This email is not from Hexagon’s Office 365 instance. Please be careful while clicking links, opening attachments, or replying to this email. Add a helper function to access to BSEC misc driver. Signed-off-by: Patrick Delaunay --- arch/arm/mach-stm32mp/cmd_stm32key.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index c4cb6342fa..886c52794f 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -14,6 +14,17 @@ #define STM32_OTP_HASH_KEY_START 24 #define STM32_OTP_HASH_KEY_SIZE 8 +static int get_misc_dev(struct udevice **dev) +{ + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), dev); + if (ret) + log_err("Can't find stm32mp_bsec driver\n"); + + return ret; +} + static void read_hash_value(u32 addr) { int i; @@ -31,13 +42,9 @@ static int fuse_hash_value(u32 addr, bool print) u32 word, val; int i, ret; - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(stm32mp_bsec), - &dev); - if (ret) { - log_err("Can't find stm32mp_bsec driver\n"); + ret = get_misc_dev(&dev); + if (ret) return ret; - } for (i = 0, word = STM32_OTP_HASH_KEY_START; i < STM32_OTP_HASH_KEY_SIZE; -- 2.25.1

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[PATCH 0/7] stm32mp: cmd_stm32key: updates
by Hexagon Email Recovery 01 Jul '21

01 Jul '21

This message could not be delivered immediately due to an internal mail routing issue. The mail routing error has been resolved in the meantime. We apologize for the delay in delivery and any inconvenience this may have caused. In case of any questions please contact us via it(a)hexagon.com. Original sender: patrick.delaunay(a)foss.st.com Original delivery time: 28-Jun-2021 01:28 PM (UTC) ----------------------------------------------------------------------------------------------------------------------- This email is not from Hexagon’s Office 365 instance. Please be careful while clicking links, opening attachments, or replying to this email. Several improvements and protection on the command stm32key. This command is used to experiment the secure boot on STM32MP15x; the expected sequence to manually activate it with this U-Boot command is: - Key generation with STM32 KeyGen tool - Key registration: update and lock PKH in OTP (stm32key fuse) - Perform image authentication of an image signed with STM32 Signing tool and check that the ROM code accepted them - Close the device, only signed binary will be accepted (stm32key close) Warning: Make sure that a device with Secure boot enabled is used, check the security field of the chip part number. Otherwise the chip will be bricked and could not be used anymore. This command is activated by default on STMicroelectronics evaluation boards but these OTP can also be updated directly by customer application or with Secure Secret Provisioning (SSP). Patrick Delaunay (7): stm32mp: configs: activate the command stm32key only for ST boards stm32mp: cmd_stm32key: use sub command stm32mp: cmd_stm32key: handle error in fuse_hash_value stm32mp: cmd_stm32key: lock of PKH OTP after fuse stm32mp: cmd_stm32key: add get_misc_dev function stm32mp: cmd_stm32key: add read OTP subcommand stm32mp: cmd_stm32key: add subcommand close arch/arm/mach-stm32mp/Kconfig | 4 +- arch/arm/mach-stm32mp/cmd_stm32key.c | 239 +++++++++++++++++++++++---- configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + 4 files changed, 208 insertions(+), 37 deletions(-) -- 2.25.1

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