July 2021 - U-Boot

[PATCH] remove struct uclass_driver::ops
by Rasmus Villemoes 04 Jul '21

04 Jul '21

Each _device_ belonging to a given uclass of course has its own ->ops, of a type determined by and known to the uclass. However, no instance of a uclass_driver seems to populate ->ops, and the only reference to it in code is this relocation. Moreover, it's not really clear what could sensibly be assigned; it would have to be some "struct uclass_ops *" providing a set of methods for the core to call on that particular uclass, but should the need for that ever arise, it would be better to have a member of that particular type instead of void*. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- drivers/core/root.c | 3 --- include/dm/uclass.h | 3 --- 2 files changed, 6 deletions(-) diff --git a/drivers/core/root.c b/drivers/core/root.c index fe0562cd6f..a03661bf06 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -111,9 +111,6 @@ void fix_uclass(void) entry->init += gd->reloc_off; if (entry->destroy) entry->destroy += gd->reloc_off; - /* FIXME maybe also need to fix these ops */ - if (entry->ops) - entry->ops += gd->reloc_off; } } diff --git a/include/dm/uclass.h b/include/dm/uclass.h index 6752d8ee0b..2778818b52 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -84,8 +84,6 @@ struct udevice; * its children. If non-zero this is the size of this data, to be allocated * in the child device's parent_plat pointer. This value is only used as * a fallback if this member is 0 in the driver. - * @ops: Uclass operations, providing the consistent interface to devices - * within the uclass. * @flags: Flags for this uclass (DM_UC_...) */ struct uclass_driver { @@ -106,7 +104,6 @@ struct uclass_driver { int per_device_plat_auto; int per_child_auto; int per_child_plat_auto; - const void *ops; uint32_t flags; }; -- 2.29.2

2 2

[PATCH v3] sandbox: cros-ec: Add tests for the Chromium OS EC PWM driver
by Alper Nebi Yasak 04 Jul '21

04 Jul '21

This patch adds a limited pulse-width modulator to sandbox's Chromium OS Embedded Controller emulation. The emulated PWM device supports multiple channels but can only set a duty cycle for each, as the actual EC doesn't expose any functionality or information other than that. Though the EC supports specifying the PWM channel by its type (e.g. display backlight, keyboard backlight), this is not implemented in the emulation as nothing in U-Boot uses this type specification. This emulated PWM device is then used to test the Chromium OS PWM driver in sandbox. Adding the required device node to the sandbox test device-tree unfortunately makes it the first PWM device, so this also touches some other tests to make sure they still use the sandbox PWM. Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- This depends on a small fix [1] for cros-ec-pwm which otherwise fails to build. [1] https://patchwork.ozlabs.org/project/uboot/patch/20210514134840.19380-1-alp… Changes in v3: - Add tag: "Reviewed-by: Simon Glass <sjg(a)chromium.org>" - Replace instances of "Chrome OS" with "Chromium OS" in commit message - Add missing "EC" in the subject line v2: https://patchwork.ozlabs.org/project/uboot/patch/20210519153017.12544-1-alp… Changes in v2: - Try to clarify commit message v1: https://patchwork.ozlabs.org/project/uboot/patch/20210516154144.141945-1-al… arch/sandbox/dts/test.dts | 6 +++ arch/sandbox/include/asm/test.h | 10 +++++ configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_noinst_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/misc/cros_ec_sandbox.c | 47 +++++++++++++++++++++++ test/cmd/pwm.c | 32 +++++++++++++++- test/dm/Makefile | 1 + test/dm/cros_ec_pwm.c | 60 ++++++++++++++++++++++++++++++ test/dm/panel.c | 2 +- test/dm/pwm.c | 6 ++- 13 files changed, 164 insertions(+), 5 deletions(-) create mode 100644 test/dm/cros_ec_pwm.c diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 5ca3bc502a43..c684ff0b6db8 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -139,6 +139,12 @@ size = <0x10000>; }; }; + + cros_ec_pwm: cros-ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + }; dsi_host: dsi_host { diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 1cb960ac240d..dab1a4ea01b3 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -275,4 +275,14 @@ void sandbox_set_enable_memio(bool enable); */ void sandbox_cros_ec_set_test_flags(struct udevice *dev, uint flags); +/** + * sandbox_cros_ec_get_pwm_duty() - Get EC PWM config for testing purposes + * + * @dev: Device to check + * @index: PWM channel index + * @duty: Current duty cycle in 0..EC_PWM_MAX_DUTY range. + * @return 0 if OK, -ENOSPC if the PWM number is invalid + */ +int sandbox_cros_ec_get_pwm_duty(struct udevice *dev, uint index, uint *duty); + #endif diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index 9a373bab6fe3..188ce05cfbf1 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -186,6 +186,7 @@ CONFIG_REGULATOR_S5M8767=y CONFIG_DM_REGULATOR_SANDBOX=y CONFIG_REGULATOR_TPS65090=y CONFIG_DM_PWM=y +CONFIG_PWM_CROS_EC=y CONFIG_PWM_SANDBOX=y CONFIG_RAM=y CONFIG_REMOTEPROC_SANDBOX=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index bdbf714e2bd9..6c7a2f02718b 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -223,6 +223,7 @@ CONFIG_DM_REGULATOR_SANDBOX=y CONFIG_REGULATOR_TPS65090=y CONFIG_DM_REGULATOR_SCMI=y CONFIG_DM_PWM=y +CONFIG_PWM_CROS_EC=y CONFIG_PWM_SANDBOX=y CONFIG_RAM=y CONFIG_REMOTEPROC_SANDBOX=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 853c9440ea02..0844d6ec23eb 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -163,6 +163,7 @@ CONFIG_REGULATOR_S5M8767=y CONFIG_DM_REGULATOR_SANDBOX=y CONFIG_REGULATOR_TPS65090=y CONFIG_DM_PWM=y +CONFIG_PWM_CROS_EC=y CONFIG_PWM_SANDBOX=y CONFIG_RAM=y CONFIG_REMOTEPROC_SANDBOX=y diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig index c7fc98b5569a..629bde1f7ed6 100644 --- a/configs/sandbox_noinst_defconfig +++ b/configs/sandbox_noinst_defconfig @@ -181,6 +181,7 @@ CONFIG_REGULATOR_S5M8767=y CONFIG_DM_REGULATOR_SANDBOX=y CONFIG_REGULATOR_TPS65090=y CONFIG_DM_PWM=y +CONFIG_PWM_CROS_EC=y CONFIG_PWM_SANDBOX=y CONFIG_RAM=y CONFIG_REMOTEPROC_SANDBOX=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index 87223a54d873..aa629e231753 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -183,6 +183,7 @@ CONFIG_REGULATOR_S5M8767=y CONFIG_DM_REGULATOR_SANDBOX=y CONFIG_REGULATOR_TPS65090=y CONFIG_DM_PWM=y +CONFIG_PWM_CROS_EC=y CONFIG_PWM_SANDBOX=y CONFIG_RAM=y CONFIG_REMOTEPROC_SANDBOX=y diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index bc01df0904eb..db5e3b0f51a2 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -64,6 +64,7 @@ struct ec_keymatrix_entry { enum { VSTORE_SLOT_COUNT = 4, + PWM_CHANNEL_COUNT = 4, }; struct vstore_slot { @@ -71,6 +72,10 @@ struct vstore_slot { u8 data[EC_VSTORE_SLOT_SIZE]; }; +struct ec_pwm_channel { + uint duty; /* not ns, EC_PWM_MAX_DUTY = 100% */ +}; + /** * struct ec_state - Information about the EC state * @@ -85,6 +90,7 @@ struct vstore_slot { * @recovery_req: Keyboard recovery requested * @test_flags: Flags that control behaviour for tests * @slot_locked: Locked vstore slots (mask) + * @pwm: Information per PWM channel */ struct ec_state { u8 vbnv_context[EC_VBNV_BLOCK_SIZE_V2]; @@ -98,6 +104,7 @@ struct ec_state { bool recovery_req; uint test_flags; struct vstore_slot slot[VSTORE_SLOT_COUNT]; + struct ec_pwm_channel pwm[PWM_CHANNEL_COUNT]; } s_state, *g_state; /** @@ -554,6 +561,33 @@ static int process_cmd(struct ec_state *ec, len = sizeof(*resp); break; } + case EC_CMD_PWM_GET_DUTY: { + const struct ec_params_pwm_get_duty *req = req_data; + struct ec_response_pwm_get_duty *resp = resp_data; + struct ec_pwm_channel *pwm; + + if (req->pwm_type != EC_PWM_TYPE_GENERIC) + return -EINVAL; + if (req->index >= PWM_CHANNEL_COUNT) + return -EINVAL; + pwm = &ec->pwm[req->index]; + resp->duty = pwm->duty; + len = sizeof(*resp); + break; + } + case EC_CMD_PWM_SET_DUTY: { + const struct ec_params_pwm_set_duty *req = req_data; + struct ec_pwm_channel *pwm; + + if (req->pwm_type != EC_PWM_TYPE_GENERIC) + return -EINVAL; + if (req->index >= PWM_CHANNEL_COUNT) + return -EINVAL; + pwm = &ec->pwm[req->index]; + pwm->duty = req->duty; + len = 0; + break; + } default: printf(" ** Unknown EC command %#02x\n", req_hdr->command); return -1; @@ -619,6 +653,19 @@ void sandbox_cros_ec_set_test_flags(struct udevice *dev, uint flags) ec->test_flags = flags; } +int sandbox_cros_ec_get_pwm_duty(struct udevice *dev, uint index, uint *duty) +{ + struct ec_state *ec = dev_get_priv(dev); + struct ec_pwm_channel *pwm; + + if (index >= PWM_CHANNEL_COUNT) + return -ENOSPC; + pwm = &ec->pwm[index]; + *duty = pwm->duty; + + return 0; +} + int cros_ec_probe(struct udevice *dev) { struct ec_state *ec = dev_get_priv(dev); diff --git a/test/cmd/pwm.c b/test/cmd/pwm.c index 5343af83fa34..2fc0b5e40704 100644 --- a/test/cmd/pwm.c +++ b/test/cmd/pwm.c @@ -18,16 +18,20 @@ static int dm_test_pwm_cmd(struct unit_test_state *uts) { struct udevice *dev; + /* cros-ec-pwm */ ut_assertok(uclass_get_device(UCLASS_PWM, 0, &dev)); ut_assertnonnull(dev); ut_assertok(console_record_reset_enable()); /* pwm <invert> <pwm_dev_num> <channel> <polarity> */ - ut_assertok(run_command("pwm invert 0 0 1", 0)); + /* cros-ec-pwm doesn't support invert */ + ut_asserteq(1, run_command("pwm invert 0 0 1", 0)); + ut_assert_nextline("error(-38)") ut_assert_console_end(); - ut_assertok(run_command("pwm invert 0 0 0", 0)); + ut_asserteq(1, run_command("pwm invert 0 0 0", 0)); + ut_assert_nextline("error(-38)") ut_assert_console_end(); /* pwm <config> <pwm_dev_num> <channel> <period_ns> <duty_ns> */ @@ -41,6 +45,30 @@ static int dm_test_pwm_cmd(struct unit_test_state *uts) ut_assertok(run_command("pwm disable 0 0", 0)); ut_assert_console_end(); + /* sandbox-pwm */ + ut_assertok(uclass_get_device(UCLASS_PWM, 1, &dev)); + ut_assertnonnull(dev); + + ut_assertok(console_record_reset_enable()); + + /* pwm <invert> <pwm_dev_num> <channel> <polarity> */ + ut_assertok(run_command("pwm invert 1 0 1", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("pwm invert 1 0 0", 0)); + ut_assert_console_end(); + + /* pwm <config> <pwm_dev_num> <channel> <period_ns> <duty_ns> */ + ut_assertok(run_command("pwm config 1 0 10 50", 0)); + ut_assert_console_end(); + + /* pwm <enable/disable> <pwm_dev_num> <channel> */ + ut_assertok(run_command("pwm enable 1 0", 0)); + ut_assert_console_end(); + + ut_assertok(run_command("pwm disable 1 0", 0)); + ut_assert_console_end(); + return 0; } diff --git a/test/dm/Makefile b/test/dm/Makefile index c9644617a1fe..9ef9171a1cbc 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_DM_BOOTCOUNT) += bootcount.o obj-$(CONFIG_CLK) += clk.o clk_ccf.o obj-$(CONFIG_CPU) += cpu.o obj-$(CONFIG_CROS_EC) += cros_ec.o +obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o obj-$(CONFIG_DEVRES) += devres.o obj-$(CONFIG_DMA) += dma.o obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi_host.o diff --git a/test/dm/cros_ec_pwm.c b/test/dm/cros_ec_pwm.c new file mode 100644 index 000000000000..f8d6e1e6c40f --- /dev/null +++ b/test/dm/cros_ec_pwm.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <cros_ec.h> +#include <dm.h> +#include <pwm.h> +#include <asm/test.h> +#include <dm/test.h> +#include <test/test.h> +#include <test/ut.h> + +static int dm_test_cros_ec_pwm(struct unit_test_state *uts) +{ + struct udevice *pwm; + struct udevice *ec; + uint duty; + + ut_assertok(uclass_get_device_by_name(UCLASS_PWM, "cros-ec-pwm", &pwm)); + ut_assertnonnull(pwm); + ec = dev_get_parent(pwm); + ut_assertnonnull(ec); + + ut_assertok(pwm_set_config(pwm, 0, 100, 50)); + ut_assertok(pwm_set_enable(pwm, 0, true)); + ut_assertok(sandbox_cros_ec_get_pwm_duty(ec, 0, &duty)); + ut_asserteq(50 * EC_PWM_MAX_DUTY / 100, duty); + + ut_assertok(pwm_set_config(pwm, 0, 15721, 2719)); + ut_assertok(pwm_set_enable(pwm, 0, true)); + ut_assertok(sandbox_cros_ec_get_pwm_duty(ec, 0, &duty)); + ut_asserteq(2719 * EC_PWM_MAX_DUTY / 15721, duty); + + ut_assertok(pwm_set_enable(pwm, 0, false)); + ut_assertok(sandbox_cros_ec_get_pwm_duty(ec, 0, &duty)); + ut_asserteq(0, duty); + + ut_assertok(pwm_set_enable(pwm, 0, true)); + ut_assertok(sandbox_cros_ec_get_pwm_duty(ec, 0, &duty)); + ut_asserteq(2719 * EC_PWM_MAX_DUTY / 15721, duty); + + ut_assertok(pwm_set_config(pwm, 1, 1000, 0)); + ut_assertok(pwm_set_enable(pwm, 1, true)); + ut_assertok(sandbox_cros_ec_get_pwm_duty(ec, 1, &duty)); + ut_asserteq(0, duty); + + ut_assertok(pwm_set_config(pwm, 2, 1000, 1024)); + ut_assertok(pwm_set_enable(pwm, 2, true)); + ut_assertok(sandbox_cros_ec_get_pwm_duty(ec, 2, &duty)); + ut_asserteq(EC_PWM_MAX_DUTY, duty); + + ut_assertok(pwm_set_config(pwm, 3, EC_PWM_MAX_DUTY, 0xABCD)); + ut_assertok(pwm_set_enable(pwm, 3, true)); + ut_assertok(sandbox_cros_ec_get_pwm_duty(ec, 3, &duty)); + ut_asserteq(0xABCD, duty); + + ut_asserteq(-EINVAL, pwm_set_enable(pwm, 4, true)); + + return 0; +} +DM_TEST(dm_test_cros_ec_pwm, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); diff --git a/test/dm/panel.c b/test/dm/panel.c index 49f5ac7169d3..4d435a0d255c 100644 --- a/test/dm/panel.c +++ b/test/dm/panel.c @@ -28,7 +28,7 @@ static int dm_test_panel(struct unit_test_state *uts) bool polarity; ut_assertok(uclass_first_device_err(UCLASS_PANEL, &dev)); - ut_assertok(uclass_first_device_err(UCLASS_PWM, &pwm)); + ut_assertok(uclass_get_device_by_name(UCLASS_PWM, "pwm", &pwm)); ut_assertok(uclass_get_device(UCLASS_GPIO, 1, &gpio)); ut_assertok(regulator_get_by_platname("VDD_EMMC_1.8V", &reg)); ut_assertok(sandbox_pwm_get_config(pwm, 0, &period_ns, &duty_ns, diff --git a/test/dm/pwm.c b/test/dm/pwm.c index b624cf3d6558..dff626c771ac 100644 --- a/test/dm/pwm.c +++ b/test/dm/pwm.c @@ -20,7 +20,7 @@ static int dm_test_pwm_base(struct unit_test_state *uts) bool enable; bool polarity; - ut_assertok(uclass_get_device(UCLASS_PWM, 0, &dev)); + ut_assertok(uclass_get_device_by_name(UCLASS_PWM, "pwm", &dev)); ut_assertnonnull(dev); ut_assertok(pwm_set_config(dev, 0, 100, 50)); ut_assertok(pwm_set_enable(dev, 0, true)); @@ -35,8 +35,10 @@ static int dm_test_pwm_base(struct unit_test_state *uts) ut_asserteq(period_ns, 4096); ut_asserteq(duty_ns, 50 * 4096 / 100); + ut_assertok(uclass_get_device(UCLASS_PWM, 0, &dev)); ut_assertok(uclass_get_device(UCLASS_PWM, 1, &dev)); - ut_asserteq(-ENODEV, uclass_get_device(UCLASS_PWM, 2, &dev)); + ut_assertok(uclass_get_device(UCLASS_PWM, 2, &dev)); + ut_asserteq(-ENODEV, uclass_get_device(UCLASS_PWM, 3, &dev)); return 0; } -- 2.31.1

2 1

[PATCH] tools: Fix default target compile tools in Python tools
by Alper Nebi Yasak 04 Jul '21

04 Jul '21

In commit 1e4687aa47ed ("binman: Use target-specific tools when cross-compiling"), a utility function was implemented to get preferred compilation tools using environment variables like CC and CROSS_COMPILE. Although it intended to provide custom default tools (same as those in the global Makefile) when no relevant variables were set (for example using "gcc" for "cc"), it is only doing so when CROSS_COMPILE is set and returning the literal name of the tool otherwise. Remove the check for an empty CROSS_COMPILE, which makes the function use it as an empty prefix to the custom defaults and return the intended executables. Fixes: 1e4687aa47ed ("binman: Use target-specific tools when cross-compiling") Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- tools/patman/tools.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/tools/patman/tools.py b/tools/patman/tools.py index e5f391b7aa9a..ec95a543bd92 100644 --- a/tools/patman/tools.py +++ b/tools/patman/tools.py @@ -292,8 +292,6 @@ def GetTargetCompileTool(name, cross_compile=None): if cross_compile is None: cross_compile = env.get('CROSS_COMPILE', '') - if not cross_compile: - return name, [] if name in ('as', 'ar', 'nm', 'ldr', 'strip', 'objcopy', 'objdump'): target_name = cross_compile + name -- 2.32.0.rc2

2 1

[PATCH 0/8] sunxi: mmc: Fixes and speed increase
by Andre Przywara 04 Jul '21

04 Jul '21

While debugging some eMMC problem on the H616 SoC, I stumbled upon some weird code in the Allwinner MMC driver. Some closer inspection and some help from Ondrej later this series of fixes emerged: Some patches remove part of the #ifdef hell we needlessly had in the driver. A big chunk is around the "new timing mode", which all "newer" SoCs (since around 2015) have, and which requires some extra bit to be set. We didn't enable this mode for all SoCs, this is now fixed in patches 3-6. Patch 7 fixes a big performance problem we had due to using MMIO accesses for the actual data transfer, as opposed to DMA transfers used in Linux. Short from adding a lot of code to use DMA as well, we can actually halve the number of MMIO accesses on reads, effectively doubling the bus transfer performance. This helps the H6 a lot, but also improves the eMMC read performance. The final patch makes use of some generic MMC DT code, to parse generic DT properties. This allows us to remove sunxi specific code, but also adds support for "broken-cd" and more advanced MMC speed modes. Please have a look and test this code on as many boards as possible. While a performance increase is nice, we don't want to risk data integrity over this, so please try to verify that it still works for you. Cheers, Andre. P.S. Patches 5 and 6 use different approaches to differentiate between SoCs specific quirks: Patch 5/8 selects an explicit symbol from the SoC specific sections in our Kconfig file, while patch 6/8 compares the selected SoC type in the C code. Please let me know which approach is better, I can then use this for both patches (and in the future). Andre Przywara (8): mmc: sunxi: Avoid #ifdefs in delay and width setup mmc: sunxi: Fix warnings with CONFIG_PHYS_64BIT mmc: sunxi: Fix MMC clock parent selection mmc: sunxi: Cleanup "new timing mode" selection mmc: sunxi: Enable "new timing mode" on all new SoCs mmc: sunxi: Cleanup and fix self-calibration code mmc: sunxi: Increase MMIO FIFO read performance mmc: sunxi: Use mmc_of_parse() .../include/asm/arch-sunxi/clock_sun50i_h6.h | 2 +- arch/arm/include/asm/arch-sunxi/mmc.h | 1 + arch/arm/mach-sunxi/Kconfig | 3 + drivers/mmc/sunxi_mmc.c | 160 +++++++++++------- 4 files changed, 102 insertions(+), 64 deletions(-) -- 2.17.5

3 14

[RFC PATCH] mtd: mxs_nand: Add support for edo mode for imx6ul(lz) architecture
by Michael Trimarchi 04 Jul '21

04 Jul '21

Add a proof of concept to support nand speed mode. This reduce load time about 4 times for large binary Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- arch/arm/include/asm/mach-imx/regs-gpmi.h | 9 + drivers/mtd/nand/raw/mxs_nand.c | 238 ++++++++++++++++++++-- drivers/mtd/nand/raw/mxs_nand_dt.c | 9 +- include/mxs_nand.h | 1 + 4 files changed, 242 insertions(+), 15 deletions(-) diff --git a/arch/arm/include/asm/mach-imx/regs-gpmi.h b/arch/arm/include/asm/mach-imx/regs-gpmi.h index 33daa53c45..7a15778631 100644 --- a/arch/arm/include/asm/mach-imx/regs-gpmi.h +++ b/arch/arm/include/asm/mach-imx/regs-gpmi.h @@ -93,6 +93,11 @@ struct mxs_gpmi_regs { #define GPMI_CTRL1_DECOUPLE_CS (1 << 24) #define GPMI_CTRL1_WRN_DLY_SEL_MASK (0x3 << 22) #define GPMI_CTRL1_WRN_DLY_SEL_OFFSET 22 +#define GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS 0x0 +#define GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS 0x1 +#define GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS 0x2 +#define GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY 0x3 + #define GPMI_CTRL1_TIMEOUT_IRQ_EN (1 << 20) #define GPMI_CTRL1_GANGED_RDYBUSY (1 << 19) #define GPMI_CTRL1_BCH_MODE (1 << 18) @@ -111,6 +116,10 @@ struct mxs_gpmi_regs { #define GPMI_CTRL1_ATA_IRQRDY_POLARITY (1 << 2) #define GPMI_CTRL1_CAMERA_MODE (1 << 1) #define GPMI_CTRL1_GPMI_MODE (1 << 0) +#define GPMI_CTRL1_CLEAR_MASK (GPMI_CTRL1_WRN_DLY_SEL_MASK | \ + GPMI_CTRL1_DLL_ENABLE | \ + GPMI_CTRL1_RDN_DELAY_MASK | \ + GPMI_CTRL1_HALF_PERIOD) #define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) #define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index e56ebcfddc..ba1ce9cf4c 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -26,8 +26,11 @@ #include <asm/arch/imx-regs.h> #include <asm/mach-imx/regs-bch.h> #include <asm/mach-imx/regs-gpmi.h> +#include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <mxs_nand.h> +#include <linux/math64.h> +#include <clk.h> #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4 @@ -46,6 +49,10 @@ #endif #define MXS_NAND_BCH_TIMEOUT 10000 +#define USEC_PER_SEC 1000000 +#define NSEC_PER_SEC 1000000000L + +#define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period) struct nand_ecclayout fake_ecc_layout; @@ -1310,6 +1317,206 @@ err1: return ret; } +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +/* + * <1> Firstly, we should know what's the GPMI-clock means. + * The GPMI-clock is the internal clock in the gpmi nand controller. + * If you set 100MHz to gpmi nand controller, the GPMI-clock's period + * is 10ns. Mark the GPMI-clock's period as GPMI-clock-period. + * + * <2> Secondly, we should know what's the frequency on the nand chip pins. + * The frequency on the nand chip pins is derived from the GPMI-clock. + * We can get it from the following equation: + * + * F = G / (DS + DH) + * + * F : the frequency on the nand chip pins. + * G : the GPMI clock, such as 100MHz. + * DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP + * DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD + * + * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz, + * the nand EDO(extended Data Out) timing could be applied. + * The GPMI implements a feedback read strobe to sample the read data. + * The feedback read strobe can be delayed to support the nand EDO timing + * where the read strobe may deasserts before the read data is valid, and + * read data is valid for some time after read strobe. + * + * The following figure illustrates some aspects of a NAND Flash read: + * + * |<---tREA---->| + * | | + * | | | + * |<--tRP-->| | + * | | | + * __ ___|__________________________________ + * RDN \________/ | + * | + * /---------\ + * Read Data --------------< >--------- + * \---------/ + * | | + * |<-D->| + * FeedbackRDN ________ ____________ + * \___________/ + * + * D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY. + * + * + * <4> Now, we begin to describe how to compute the right RDN_DELAY. + * + * 4.1) From the aspect of the nand chip pins: + * Delay = (tREA + C - tRP) {1} + * + * tREA : the maximum read access time. + * C : a constant to adjust the delay. default is 4000ps. + * tRP : the read pulse width, which is exactly: + * tRP = (GPMI-clock-period) * DATA_SETUP + * + * 4.2) From the aspect of the GPMI nand controller: + * Delay = RDN_DELAY * 0.125 * RP {2} + * + * RP : the DLL reference period. + * if (GPMI-clock-period > DLL_THRETHOLD) + * RP = GPMI-clock-period / 2; + * else + * RP = GPMI-clock-period; + * + * Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period + * is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD + * is 16000ps, but in mx6q, we use 12000ps. + * + * 4.3) since {1} equals {2}, we get: + * + * (tREA + 4000 - tRP) * 8 + * RDN_DELAY = ----------------------- {3} + * RP + */ +static void mxs_compute_timings(struct nand_chip *chip, + const struct nand_sdr_timings *sdr) +{ + struct mxs_nand_info *nand_info = nand_get_controller_data(chip); + unsigned long int clk_rate; + unsigned int dll_wait_time_us; + unsigned int dll_threshold_ps = nand_info->max_chain_delay; + unsigned int period_ps, reference_period_ps; + unsigned int data_setup_cycles, data_hold_cycles, addr_setup_cycles; + unsigned int tRP_ps; + bool use_half_period; + int sample_delay_ps, sample_delay_factor; + u16 busy_timeout_cycles; + u8 wrn_dly_sel; + u32 timing0; + u32 timing1; + u32 ctrl1n; + u32 clkcfg; + + if (sdr->tRC_min >= 30000) { + /* ONFI non-EDO modes [0-3] */ + clk_rate = 22000000; + wrn_dly_sel = GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS; + clkcfg = (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | \ + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET); + } else if (sdr->tRC_min >= 25000) { + /* ONFI EDO mode 4 */ + clk_rate = 80000000; + wrn_dly_sel = GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; + clkcfg = (1 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | \ + (1 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET); + } else { + /* ONFI EDO mode 5 */ + clk_rate = 100000000; + wrn_dly_sel = GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY; + clkcfg = (1 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | \ + (1 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET); + } + + /* SDR core timings are given in picoseconds */ + period_ps = div_u64((u64)NSEC_PER_SEC * 1000, clk_rate); + + addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps); + data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps); + data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps); + busy_timeout_cycles = TO_CYCLES(sdr->tWB_max + sdr->tR_max, period_ps); + + timing0 = (addr_setup_cycles << GPMI_TIMING0_ADDRESS_SETUP_OFFSET) | + (data_hold_cycles << GPMI_TIMING0_DATA_HOLD_OFFSET) | + (data_setup_cycles << GPMI_TIMING0_DATA_SETUP_OFFSET); + timing1 = (busy_timeout_cycles * 4096) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET; + + /* + * Derive NFC ideal delay from {3}: + * + * (tREA + 4000 - tRP) * 8 + * RDN_DELAY = ----------------------- + * RP + */ + if (period_ps > dll_threshold_ps) { + use_half_period = true; + reference_period_ps = period_ps / 2; + } else { + use_half_period = false; + reference_period_ps = period_ps; + } + + tRP_ps = data_setup_cycles * period_ps; + sample_delay_ps = (sdr->tREA_max + 4000 - tRP_ps) * 8; + if (sample_delay_ps > 0) + sample_delay_factor = sample_delay_ps / reference_period_ps; + else + sample_delay_factor = 0; + + ctrl1n = (wrn_dly_sel << GPMI_CTRL1_WRN_DLY_SEL_OFFSET); + if (sample_delay_factor) + ctrl1n |= (sample_delay_factor << GPMI_CTRL1_RDN_DELAY_OFFSET) | + GPMI_CTRL1_DLL_ENABLE | + (use_half_period ? GPMI_CTRL1_HALF_PERIOD : 0); + + + writel(timing0, &nand_info->gpmi_regs->hw_gpmi_timing0); + writel(timing1, &nand_info->gpmi_regs->hw_gpmi_timing1); + + /* + * Clear several CTRL1 fields, DLL must be disabled when setting + * RDN_DELAY or HALF_PERIOD. + */ + writel(GPMI_CTRL1_CLEAR_MASK, &nand_info->gpmi_regs->hw_gpmi_ctrl1_clr); + writel(ctrl1n, &nand_info->gpmi_regs->hw_gpmi_ctrl1_set); + + setup_gpmi_io_clk(clkcfg); + + /* Wait 64 clock cycles before using the GPMI after enabling the DLL */ + dll_wait_time_us = USEC_PER_SEC / clk_rate * 64; + if (!dll_wait_time_us) + dll_wait_time_us = 1; + + /* Wait for the DLL to settle. */ + udelay(dll_wait_time_us); +} + +static int mxs_nand_setup_interface(struct mtd_info *mtd, int chipnr, + const struct nand_data_interface *conf) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + const struct nand_sdr_timings *sdr; + + + sdr = nand_get_sdr_timings(conf); + if (IS_ERR(sdr)) + return PTR_ERR(sdr); + + /* Stop here if this call was just a check */ + if (chipnr < 0) + return 0; + + /* Do the actual derivation of the controller timings */ + mxs_compute_timings(chip, sdr); + + return 0; +} + +#endif + int mxs_nand_init_spl(struct nand_chip *nand) { struct mxs_nand_info *nand_info; @@ -1342,16 +1549,16 @@ int mxs_nand_init_spl(struct nand_chip *nand) nand->options |= NAND_NO_SUBPAGE_WRITE; - nand->cmd_ctrl = mxs_nand_cmd_ctrl; - nand->dev_ready = mxs_nand_device_ready; - nand->select_chip = mxs_nand_select_chip; + nand->cmd_ctrl = mxs_nand_cmd_ctrl; + nand->dev_ready = mxs_nand_device_ready; + nand->select_chip = mxs_nand_select_chip; - nand->read_byte = mxs_nand_read_byte; - nand->read_buf = mxs_nand_read_buf; + nand->read_byte = mxs_nand_read_byte; + nand->read_buf = mxs_nand_read_buf; - nand->ecc.read_page = mxs_nand_ecc_read_page; + nand->ecc.read_page = mxs_nand_ecc_read_page; - nand->ecc.mode = NAND_ECC_HW; + nand->ecc.mode = NAND_ECC_HW; return 0; } @@ -1384,16 +1591,19 @@ int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info) if (nand_info->dev) nand->flash_node = dev_of_offset(nand_info->dev); - nand->cmd_ctrl = mxs_nand_cmd_ctrl; + nand->cmd_ctrl = mxs_nand_cmd_ctrl; - nand->dev_ready = mxs_nand_device_ready; - nand->select_chip = mxs_nand_select_chip; - nand->block_bad = mxs_nand_block_bad; + nand->dev_ready = mxs_nand_device_ready; + nand->select_chip = mxs_nand_select_chip; + nand->block_bad = mxs_nand_block_bad; - nand->read_byte = mxs_nand_read_byte; +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) + nand->setup_data_interface = mxs_nand_setup_interface; +#endif + nand->read_byte = mxs_nand_read_byte; - nand->read_buf = mxs_nand_read_buf; - nand->write_buf = mxs_nand_write_buf; + nand->read_buf = mxs_nand_read_buf; + nand->write_buf = mxs_nand_write_buf; /* first scan to find the device and get the page size */ if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index 18c042c7bb..872e5fe684 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -22,22 +22,27 @@ struct mxs_nand_dt_data { unsigned int max_ecc_strength_supported; + int max_chain_delay; /* See the async EDO mode */ }; static const struct mxs_nand_dt_data mxs_nand_imx6q_data = { .max_ecc_strength_supported = 40, + .max_chain_delay = 12000, }; static const struct mxs_nand_dt_data mxs_nand_imx6sx_data = { .max_ecc_strength_supported = 62, + .max_chain_delay = 12000, }; static const struct mxs_nand_dt_data mxs_nand_imx7d_data = { .max_ecc_strength_supported = 62, + .max_chain_delay = 12000, }; static const struct mxs_nand_dt_data mxs_nand_imx8qxp_data = { .max_ecc_strength_supported = 62, + .max_chain_delay = 12000, }; static const struct udevice_id mxs_nand_dt_ids[] = { @@ -72,8 +77,10 @@ static int mxs_nand_dt_probe(struct udevice *dev) int ret; data = (void *)dev_get_driver_data(dev); - if (data) + if (data) { info->max_ecc_strength_supported = data->max_ecc_strength_supported; + info->max_chain_delay = data->max_chain_delay; + } info->dev = dev; diff --git a/include/mxs_nand.h b/include/mxs_nand.h index c0cefaca90..c7c6870ed9 100644 --- a/include/mxs_nand.h +++ b/include/mxs_nand.h @@ -42,6 +42,7 @@ struct mxs_nand_info { struct nand_chip chip; struct udevice *dev; unsigned int max_ecc_strength_supported; + int max_chain_delay; bool use_minimum_ecc; /* legacy bch geometry flag */ bool legacy_bch_geometry; -- 2.25.1

1 0

[PATCH] arm: imx: Fix spl imx romapi for imx8mn
by Michael Trimarchi 04 Jul '21

04 Jul '21

We experimenting problems with imx8mn family cpu. We try to support boot0 and boot1 fallback. The condition to decide what function the bootrom should choose come from is_boot_from_stream_device This is a boot from mmcblk0boot0 with some debug U-Boot SPL 2020.04-5.4.70-2.3.2+gf3bcbdfc62 (Jul 03 2021 - 17:00:27 +0000) power_bd71837_init DDRINFO: start DRAM init DDRINFO: DRAM rate 1600MTS DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done Normal Boot Trying to boot from BOOTROM ROM API interface 2 from boot 131073 Interface is 2 MMC and boot is 131073 and according to this static int is_boot_from_stream_device(u32 boot) +{ + u32 interface; + + interface = boot >> 16; + if (interface >= BT_DEV_TYPE_USB) + return 1; + + if (interface == BT_DEV_TYPE_MMC && (boot & 1)) + return 1; + + return 0; +} the return is 1, that does not allow us to boot. Boot from boot1 give 131072 that is boot1 this let device boot because is_boot_from_stream_device is 0 and romapi use spl_romapi_load_image_seekable Adjust the bootcondition let us boot from mmcblk0boot0 and mmcblk0boot1 without any problem mmc partconf 0 EXT_CSD[179], PARTITION_CONFIG: BOOT_ACK: 0x0 BOOT_PARTITION_ENABLE: 0x1 PARTITION_ACCESS: 0x0 and the board was fused already. Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- arch/arm/mach-imx/spl_imx_romapi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 7e6a05a6f3..36f8848d45 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -18,10 +18,11 @@ static int is_boot_from_stream_device(u32 boot) u32 interface; interface = boot >> 16; + if (interface >= BT_DEV_TYPE_USB) return 1; - if (interface == BT_DEV_TYPE_MMC && (boot & 1)) + if (!is_imx8mn() && interface == BT_DEV_TYPE_MMC && (boot & 1)) return 1; return 0; -- 2.25.1

1 0

[PATCH] ARM: renesas: Set CONFIG_SYS_TEXT_BASE=0x0 on R-Car Gen3
by Marek Vasut 04 Jul '21

04 Jul '21

Since R-Car Gen3 already enables position independent build, also set CONFIG_SYS_TEXT_BASE=0x0 to finalize the switch. This is possible since 534f0fbd65 ("arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=y") fixed current env_get_char() crash with CONFIG_SYS_TEXT_BASE=0x0 . This change permits us to start U-Boot from any location in DRAM instead of specific TEXT_BASE. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> --- configs/rcar3_salvator-x_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index bb0bcfefe2..709e6435ae 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0x50000000 +CONFIG_SYS_TEXT_BASE=0x0 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 CONFIG_DM_GPIO=y -- 2.30.2

1 0

[PATCH] ARM: rmobile: Remove default bootargs
by Marek Vasut 04 Jul '21

04 Jul '21

The bootargs in all those boards are a copy of initial example bootargs, just remove those as they make little sense in most configurations. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> --- configs/hihope_rzg2_defconfig | 1 - configs/r8a77970_eagle_defconfig | 1 - configs/r8a77980_condor_defconfig | 1 - configs/r8a77990_ebisu_defconfig | 1 - configs/r8a77995_draak_defconfig | 1 - configs/rcar3_salvator-x_defconfig | 1 - configs/rcar3_ulcb_defconfig | 1 - 7 files changed, 7 deletions(-) diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index be71ebb6a2..800481326d 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -12,7 +12,6 @@ CONFIG_TARGET_HIHOPE_RZG2=y CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb" # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_HUSH_PARSER=y diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 2e5fb60f1a..2532154978 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -14,7 +14,6 @@ CONFIG_TARGET_EAGLE=y CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb" CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 1b9948bcbb..02f008ad35 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -14,7 +14,6 @@ CONFIG_TARGET_CONDOR=y CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_DEFAULT_FDT_FILE="r8a77980-condor.dtb" # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_HUSH_PARSER=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 69297fef66..e5cab47f9f 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -13,7 +13,6 @@ CONFIG_TARGET_EBISU=y CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb" # CONFIG_BOARD_EARLY_INIT_F is not set CONFIG_UPDATE_TFTP=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 562b80b996..acae38a6c0 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -13,7 +13,6 @@ CONFIG_TARGET_DRAAK=y CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb" CONFIG_UPDATE_TFTP=y CONFIG_HUSH_PARSER=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 150db3bff5..bb0bcfefe2 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -12,7 +12,6 @@ CONFIG_TARGET_SALVATOR_X=y CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_DEFAULT_FDT_FILE="r8a77950-salvator-x.dtb" CONFIG_UPDATE_TFTP=y CONFIG_HUSH_PARSER=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index a6f806c3c3..e0d72d940d 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -13,7 +13,6 @@ CONFIG_TARGET_ULCB=y CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" CONFIG_DEFAULT_FDT_FILE="r8a77950-ulcb.dtb" CONFIG_UPDATE_TFTP=y CONFIG_HUSH_PARSER=y -- 2.30.2

1 0

[PATCH] ARM: rmobile: Align CPU: print with other prints
by Marek Vasut 04 Jul '21

04 Jul '21

The CPU: print only has one space after it, while the other prints from U-Boot align the value to offset 7. Align the CPU: print too. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> --- arch/arm/mach-rmobile/cpu_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 9ec622bdb5..83bbc4e72a 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -118,7 +118,7 @@ int print_cpuinfo(void) { int i = rmobile_cpuinfo_idx(); - printf("CPU: Renesas Electronics %s rev %d.%d\n", + printf("CPU: Renesas Electronics %s rev %d.%d\n", get_cpu_name(i), rmobile_get_cpu_rev_integer(), rmobile_get_cpu_rev_fraction()); -- 2.30.2

1 0

[PATCH 1/3] ARM: dts: rmobile: Add sysinfo extras on R-Car Gen3
by Marek Vasut 04 Jul '21

04 Jul '21

Add sysinfo node and phandle to the board ID EEPROM on all boards where this functionality is described in DT, which is Salvator-X(S), ULCB and Ebisu. The u-boot,dm-pre-reloc is necessary here, since the sysinfo must be available early during boot. The V3M and V3H boards currently do not describe this board ID EEPROM in upstream DT, but that could be easily added later, once the DTs contain the necessary nodes. ULCB and Ebisu needs the full EEPROM node in the u-boot extras DT, since the EEPROM node is still missing in the upstream DTs. Ebisu also needs extra compatible string override for the i2c_dvfs. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> --- arch/arm/dts/r8a77950-salvator-x-u-boot.dts | 17 +++++++++++++++ arch/arm/dts/r8a77950-ulcb-u-boot.dts | 18 ++++++++++++++++ arch/arm/dts/r8a77960-salvator-x-u-boot.dts | 17 +++++++++++++++ arch/arm/dts/r8a77960-ulcb-u-boot.dts | 18 ++++++++++++++++ arch/arm/dts/r8a77965-salvator-x-u-boot.dts | 17 +++++++++++++++ arch/arm/dts/r8a77965-ulcb-u-boot.dts | 18 ++++++++++++++++ arch/arm/dts/r8a77990-ebisu-u-boot.dts | 23 +++++++++++++++++++++ 7 files changed, 128 insertions(+) diff --git a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts index 36c8a44a90..bb83bc1d7b 100644 --- a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts @@ -8,6 +8,23 @@ #include "r8a77950-salvator-x.dts" #include "r8a77950-u-boot.dtsi" +/ { + sysinfo { + compatible = "renesas,rcar-sysinfo"; + i2c-eeprom = <&sysinfo_eeprom>; + u-boot,dm-pre-reloc; + }; +}; + +&i2c_dvfs { + u-boot,dm-pre-reloc; + + sysinfo_eeprom: eeprom@50 { + u-boot,dm-pre-reloc; + status = "okay"; + }; +}; + &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; status = "okay"; diff --git a/arch/arm/dts/r8a77950-ulcb-u-boot.dts b/arch/arm/dts/r8a77950-ulcb-u-boot.dts index d3191c55d5..16d9e38b70 100644 --- a/arch/arm/dts/r8a77950-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77950-ulcb-u-boot.dts @@ -17,6 +17,24 @@ gpio-miso = <&gpio6 10 0>; gpio-sstbz = <&gpio2 3 0>; }; + + sysinfo { + compatible = "renesas,rcar-sysinfo"; + i2c-eeprom = <&sysinfo_eeprom>; + u-boot,dm-pre-reloc; + }; +}; + +&i2c_dvfs { + u-boot,dm-pre-reloc; + + sysinfo_eeprom: eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + u-boot,dm-pre-reloc; + status = "okay"; + }; }; &rpc { diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts index 439fd6c3ad..dda3567e9e 100644 --- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts @@ -8,6 +8,23 @@ #include "r8a77960-salvator-x.dts" #include "r8a77960-u-boot.dtsi" +/ { + sysinfo { + compatible = "renesas,rcar-sysinfo"; + i2c-eeprom = <&sysinfo_eeprom>; + u-boot,dm-pre-reloc; + }; +}; + +&i2c_dvfs { + u-boot,dm-pre-reloc; + + sysinfo_eeprom: eeprom@50 { + u-boot,dm-pre-reloc; + status = "okay"; + }; +}; + &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; status = "okay"; diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dts b/arch/arm/dts/r8a77960-ulcb-u-boot.dts index aab9c95931..e4f77ae262 100644 --- a/arch/arm/dts/r8a77960-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dts @@ -17,6 +17,24 @@ gpio-miso = <&gpio6 10 0>; gpio-sstbz = <&gpio2 3 0>; }; + + sysinfo { + compatible = "renesas,rcar-sysinfo"; + i2c-eeprom = <&sysinfo_eeprom>; + u-boot,dm-pre-reloc; + }; +}; + +&i2c_dvfs { + u-boot,dm-pre-reloc; + + sysinfo_eeprom: eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + u-boot,dm-pre-reloc; + status = "okay"; + }; }; &rpc { diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts index 8cbef83b9c..e651e889bc 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts @@ -8,6 +8,23 @@ #include "r8a77965-salvator-x.dts" #include "r8a77965-u-boot.dtsi" +/ { + sysinfo { + compatible = "renesas,rcar-sysinfo"; + i2c-eeprom = <&sysinfo_eeprom>; + u-boot,dm-pre-reloc; + }; +}; + +&i2c_dvfs { + u-boot,dm-pre-reloc; + + sysinfo_eeprom: eeprom@50 { + u-boot,dm-pre-reloc; + status = "okay"; + }; +}; + &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; status = "okay"; diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dts b/arch/arm/dts/r8a77965-ulcb-u-boot.dts index 38966bf644..3574d6da6f 100644 --- a/arch/arm/dts/r8a77965-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dts @@ -17,6 +17,24 @@ gpio-miso = <&gpio6 10 0>; gpio-sstbz = <&gpio2 3 0>; }; + + sysinfo { + compatible = "renesas,rcar-sysinfo"; + i2c-eeprom = <&sysinfo_eeprom>; + u-boot,dm-pre-reloc; + }; +}; + +&i2c_dvfs { + u-boot,dm-pre-reloc; + + sysinfo_eeprom: eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + u-boot,dm-pre-reloc; + status = "okay"; + }; }; &rpc { diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts index 6afc0be66e..7022a2ba84 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts @@ -8,6 +8,29 @@ #include "r8a77990-ebisu.dts" #include "r8a77990-u-boot.dtsi" +/ { + sysinfo { + compatible = "renesas,rcar-sysinfo"; + i2c-eeprom = <&sysinfo_eeprom>; + u-boot,dm-pre-reloc; + }; +}; + +&i2c_dvfs { + compatible = "renesas,iic-r8a77990", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + u-boot,dm-pre-reloc; + + sysinfo_eeprom: eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + u-boot,dm-pre-reloc; + status = "okay"; + }; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; -- 2.30.2

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