July 2021 - U-Boot

Re: [PATCH v2 1/2] usb: ehci-mx6: move mode set/detect to probe
by Tim Harvey 03 Jul '21

03 Jul '21

On Fri, Jul 2, 2021 at 12:17 PM Marek Vasut <marex(a)denx.de> wrote: > > On 7/2/21 2:15 AM, Tim Harvey wrote: > > There is no need to set and/or detect mode in of_to_plat > > Are you absolutely sure of that ? > > It used to be necessary to know the core mode early to determine which > driver (the gadget or host) to probe, that's why this code was in > of_to_plat. > Marek, I can't find a reason for the core mode to be known early and have tested it both with host and gadget mode on IMX6 and IMX8MM. Fabio has tested this change also (from another thread) with SPL SDP on IMX8MM (granted the SPL is not using DM_USB for that). It appears I accidentally forgot to cc the uboot list so I'll need to resend this at any rate. Best regards, Tim

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[PULL u-boot] Please pull u-boot-amlogic-20210703
by Neil Armstrong 03 Jul '21

03 Jul '21

Hi Tom, Please find a very late fix for a SPI NOR Flash probe fail on the Amlogic based libretech boards. The CI job is at https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/8015 Thanks, Neil The following changes since commit b7ad721c83fdbeeb71189d5f259c109cb1c38895: Revert "TEST: USB_HOST not USB" (2021-06-30 13:10:02 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-amlogic.git tags/u-boot-amlogic-20210703 for you to fetch changes up to 8c6d8c32192049f8dafaaafae68eb9124b21c1e0: configs: libretech: set SPI mode to 0 (2021-07-02 23:59:27 +0200) ---------------------------------------------------------------- - configs: libretech: set SPI mode to 0 to fix SPI NOR Flash probe ---------------------------------------------------------------- Da Xue (1): configs: libretech: set SPI mode to 0 configs/libretech-ac_defconfig | 1 + configs/libretech-cc_v2_defconfig | 1 + configs/libretech-s905d-pc_defconfig | 1 + configs/libretech-s912-pc_defconfig | 1 + 4 files changed, 4 insertions(+)

2 1

Pull request for efi-2021-07-rc6
by Heinrich Schuchardt 03 Jul '21

03 Jul '21

Dear Tom, The following changes since commit b7ad721c83fdbeeb71189d5f259c109cb1c38895: Revert "TEST: USB_HOST not USB" (2021-06-30 13:10:02 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2021-07-rc6 for you to fetch changes up to 0fa5020c024e49222ca97ead3502b332d35dea76: efi_loader: Allow capsule update on-disk without checking OsIndications (2021-07-02 18:29:06 +0200) Gitlab CI showed no problems: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/8004 ---------------------------------------------------------------- Pull request for efi-2021-07-rc6 Bug fixes: * improve specification compliance of UEFI capsule updates * allow capsule update on-disk without checking OsIndications * provide parameter checks for QueryVariableInfo() ---------------------------------------------------------------- Heinrich Schuchardt (2): efi_loader: missing parentheses in query_console_size efi_loader: clear OsIndications Ilias Apalodimas (3): efi_loader: Force a single FMP instance per hardware store efi_loader: Always install FMPs efi_loader: Allow capsule update on-disk without checking OsIndications Masami Hiramatsu (2): efi: Fix to use null handle to create new handle for efi_fmp_raw efi_loader: Improve the parameter check for QueryVariableInfo() configs/xilinx_zynqmp_virt_defconfig | 1 - include/efi_loader.h | 1 + lib/efi_loader/Kconfig | 55 +++++++++++++++++++++--------------- lib/efi_loader/efi_capsule.c | 49 +++++++++++++++++++++----------- lib/efi_loader/efi_console.c | 2 +- lib/efi_loader/efi_setup.c | 46 +++++++++++++++++++++++++++++- lib/efi_loader/efi_var_common.c | 13 +++++++++ 7 files changed, 124 insertions(+), 43 deletions(-)

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[PATCH] autoboot: fix MENUKEY
by Da Xue 03 Jul '21

03 Jul '21

replace CONFIG_AUTOBOOT_USE_MENUKEY with CONFIG_AUTOBOOT_MENUKEY Signed-off-by: Da Xue <da(a)libre.computer> --- common/autoboot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/autoboot.c b/common/autoboot.c index c834db7323..26bfd64acc 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -45,7 +45,7 @@ static int menukey; #endif #ifdef CONFIG_AUTOBOOT_USE_MENUKEY -#define AUTOBOOT_MENUKEY CONFIG_AUTOBOOT_USE_MENUKEY +#define AUTOBOOT_MENUKEY CONFIG_AUTOBOOT_MENUKEY #else #define AUTOBOOT_MENUKEY 0 #endif -- 2.20.1

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[PATCH] autoboot: fix typos of CONFIG_AUTOBOOT_USE_MENUKEY
by Da Xue 03 Jul '21

03 Jul '21

replace typo CONFIG_USE_AUTOBOOT_MENUKEY with CONFIG_AUTOBOOT_USE_MENUKEY Signed-off-by: Da Xue <da(a)libre.computer> --- common/autoboot.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/common/autoboot.c b/common/autoboot.c index 0bb08e7a4c..e201c01ece 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -44,8 +44,8 @@ static int menukey; #define AUTOBOOT_STOP_STR_SHA256 "" #endif -#ifdef CONFIG_USE_AUTOBOOT_MENUKEY -#define AUTOBOOT_MENUKEY CONFIG_USE_AUTOBOOT_MENUKEY +#if defined(CONFIG_AUTOBOOT_USE_MENUKEY) && defined(CONFIG_AUTOBOOT_MENUKEY) +#define AUTOBOOT_MENUKEY CONFIG_AUTOBOOT_MENUKEY #else #define AUTOBOOT_MENUKEY 0 #endif @@ -282,7 +282,7 @@ static int abortboot_single_key(int bootdelay) abort = 1; /* don't auto boot */ bootdelay = 0; /* no more delay */ key = getchar();/* consume input */ - if (IS_ENABLED(CONFIG_USE_AUTOBOOT_MENUKEY)) + if (IS_ENABLED(CONFIG_AUTOBOOT_USE_MENUKEY)) menukey = key; break; } @@ -388,7 +388,7 @@ void autoboot_command(const char *s) disable_ctrlc(prev); /* restore Ctrl-C checking */ } - if (IS_ENABLED(CONFIG_USE_AUTOBOOT_MENUKEY) && + if (IS_ENABLED(CONFIG_AUTOBOOT_USE_MENUKEY) && menukey == AUTOBOOT_MENUKEY) { s = env_get("menucmd"); if (s) -- 2.20.1

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[PATCH] configs: libretech: set SPI mode to 0
by Da Xue 03 Jul '21

03 Jul '21

Kconfig defaults to mode 3 if CONFIG_SF_DEFAULT_MODE is not set. It becomes an issue since meson_spifc does not support SPI_CPHA. Needed after commit e2e95e5e25421fbef499e21bf94a5339701f9a99. Signed-off-by:Da Xue <da(a)libre.computer> --- configs/libretech-ac_defconfig | 1 + configs/libretech-cc_v2_defconfig | 1 + configs/libretech-s905d-pc_defconfig | 1 + configs/libretech-s912-pc_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig index ec51f2ad38..9abbcad3c0 100644 --- a/configs/libretech-ac_defconfig +++ b/configs/libretech-ac_defconfig @@ -39,6 +39,7 @@ CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MESON_GXL=y diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig index 97c8a9e47b..7dc6ed2f29 100644 --- a/configs/libretech-cc_v2_defconfig +++ b/configs/libretech-cc_v2_defconfig @@ -35,6 +35,7 @@ CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PHY_MESON_GXL=y CONFIG_DM_ETH=y diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig index c0301a0aa0..93523c23cf 100644 --- a/configs/libretech-s905d-pc_defconfig +++ b/configs/libretech-s905d-pc_defconfig @@ -36,6 +36,7 @@ CONFIG_SARADC_MESON=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig index e2faea6242..669f000f7f 100644 --- a/configs/libretech-s912-pc_defconfig +++ b/configs/libretech-s912-pc_defconfig @@ -35,6 +35,7 @@ CONFIG_SARADC_MESON=y CONFIG_MMC_MESON_GX=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y -- 2.30.2

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[PATCH 0/7] efi: Various tidy-ups and drop the default
by Simon Glass 02 Jul '21

02 Jul '21

It has come to light that EFI_LOADER adds an extraordinary amount of code to U-Boot. For example, with nokia_rx51 the size delta is about 90KB. About 170 boards explicitly disable the option, but is is clear that many more could, thus saving image size and boot time. The current situation is affecting U-Boot's image as a svelt bootloader. EFI_LOADER is required by EBBR, a new boot standard which aims to bring in UEFI protocols to U-Boot. But EBRR is not required for booting. U-Boot already provides support for FIT, the 'bootm' command and a suitable hand-off to Linux. EBRR has made the decision to create a parallel infrastructure, e.g. does not use FIT, nor U-Boot's signing infrastructure. EBBR should be truly optional, enabled only by boards that use it. Most don't use it but it is enabled anyway. The default boot path should be one that makes use of the existing U-Boot support. To try to retify this situation, this series adds a new Kconfig option for EBBR so that the naming is more explicit. Then EFI_LOADER is updated to depend on it. For now, only sandbox enables EBBR. Other boards can be added as needed, presumably by distributions that require it. Another approach would be to add 'CONFIG_EBBR=y' to the .config before building, in the build system. That might be more friendly to U-Boot users. This series also fixes a minor issue noticed during testing. Simon Glass (7): configs: Resync with savedefconfig Makefile: Drop include/asm directory as well as symlink disk: Tidy up #ifdefs in part_efi Use LIB_UUID with ACPIGEN and FS_BTRFS Allow efi_loader header to be included always lib: Create a new Kconfig option for charset conversion efi: Make EBBR optional Makefile | 2 +- common/Kconfig.boot | 15 ++ configs/am335x_igep003x_defconfig | 1 - configs/am335x_pdu001_defconfig | 1 - configs/am64x_evm_a53_defconfig | 31 ++- configs/am64x_evm_r5_defconfig | 6 +- configs/apalis-imx8_defconfig | 1 - configs/apalis-imx8x_defconfig | 1 - configs/aristainetos2c_defconfig | 1 - configs/aristainetos2ccslb_defconfig | 1 - ...edev_cc_v1_0_ultrazedev_som_v1_0_defconfig | 1 - configs/bcm7260_defconfig | 1 - configs/bcm7445_defconfig | 1 - configs/bcm963158_ram_defconfig | 1 - configs/bcm968580xref_ram_defconfig | 1 - configs/bitmain_antminer_s9_defconfig | 1 - configs/bk4r1_defconfig | 1 - configs/brppt1_mmc_defconfig | 1 - configs/brppt1_nand_defconfig | 1 - configs/brppt1_spi_defconfig | 1 - configs/brppt2_defconfig | 1 - configs/brsmarc1_defconfig | 1 - configs/brxre1_defconfig | 1 - configs/chromebook_coral_defconfig | 1 - configs/chromebook_link_defconfig | 1 - configs/colibri-imx8x_defconfig | 1 - configs/colibri_vf_defconfig | 1 - configs/controlcenterdc_defconfig | 1 - configs/crs305-1g-4s-bit_defconfig | 1 - configs/crs305-1g-4s_defconfig | 1 - configs/crs326-24g-2s-bit_defconfig | 1 - configs/crs326-24g-2s_defconfig | 1 - configs/crs328-4c-20s-4s-bit_defconfig | 1 - configs/crs328-4c-20s-4s_defconfig | 1 - configs/deneb_defconfig | 1 - configs/draco_defconfig | 2 +- configs/dragonboard820c_defconfig | 1 - configs/efi-x86_app_defconfig | 1 - configs/etamin_defconfig | 2 +- configs/evb-ast2600_defconfig | 1 - configs/evb-px30_defconfig | 1 - configs/evb-rk3308_defconfig | 1 - configs/firefly-px30_defconfig | 1 - configs/ge_bx50v3_defconfig | 1 - configs/giedi_defconfig | 1 - configs/grpeach_defconfig | 1 - configs/imx8mm-cl-iot-gate_defconfig | 8 - configs/imx8qm_mek_defconfig | 1 - configs/imx8qm_rom7720_a1_4G_defconfig | 1 - configs/imx8qxp_mek_defconfig | 1 - configs/j7200_evm_r5_defconfig | 15 +- configs/j721e_evm_r5_defconfig | 13 +- configs/kontron_sl28_defconfig | 2 - configs/kp_imx53_defconfig | 1 - configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1028aqds_tfa_defconfig | 1 - configs/ls1028aqds_tfa_lpuart_defconfig | 1 - configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1028ardb_tfa_defconfig | 1 - configs/ls1043aqds_defconfig | 1 - configs/ls1043aqds_lpuart_defconfig | 1 - configs/ls1043aqds_nand_defconfig | 1 - configs/ls1043aqds_nor_ddr3_defconfig | 1 - configs/ls1043aqds_qspi_defconfig | 1 - configs/ls1043aqds_sdcard_ifc_defconfig | 1 - configs/ls1043aqds_sdcard_qspi_defconfig | 1 - configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1043aqds_tfa_defconfig | 1 - configs/ls1043ardb_SECURE_BOOT_defconfig | 1 - configs/ls1043ardb_defconfig | 1 - configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 - configs/ls1043ardb_nand_defconfig | 1 - .../ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 - configs/ls1043ardb_sdcard_defconfig | 1 - configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1043ardb_tfa_defconfig | 1 - configs/ls1046aqds_SECURE_BOOT_defconfig | 1 - configs/ls1046aqds_defconfig | 1 - configs/ls1046aqds_lpuart_defconfig | 1 - configs/ls1046aqds_nand_defconfig | 1 - configs/ls1046aqds_qspi_defconfig | 1 - configs/ls1046aqds_sdcard_ifc_defconfig | 1 - configs/ls1046aqds_sdcard_qspi_defconfig | 1 - configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1046aqds_tfa_defconfig | 1 - configs/ls1046ardb_emmc_defconfig | 1 - configs/ls1046ardb_qspi_SECURE_BOOT_defconfig | 1 - configs/ls1046ardb_qspi_defconfig | 1 - configs/ls1046ardb_qspi_spl_defconfig | 1 - .../ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 - configs/ls1046ardb_sdcard_defconfig | 1 - configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1046ardb_tfa_defconfig | 1 - configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 1 - configs/ls1088aqds_qspi_defconfig | 1 - configs/ls1088aqds_tfa_defconfig | 1 - configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 - configs/ls1088ardb_qspi_defconfig | 1 - configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 - configs/ls1088ardb_tfa_defconfig | 1 - configs/ls2080aqds_SECURE_BOOT_defconfig | 1 - configs/ls2080aqds_defconfig | 1 - configs/ls2080aqds_nand_defconfig | 1 - configs/ls2080aqds_qspi_defconfig | 1 - configs/ls2080aqds_sdcard_defconfig | 1 - configs/ls2080ardb_SECURE_BOOT_defconfig | 1 - configs/ls2080ardb_defconfig | 1 - configs/ls2080ardb_nand_defconfig | 1 - configs/ls2081ardb_defconfig | 1 - configs/ls2088aqds_tfa_defconfig | 1 - configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 1 - configs/ls2088ardb_qspi_defconfig | 1 - configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 - configs/ls2088ardb_tfa_defconfig | 1 - configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 - configs/lx2160aqds_tfa_defconfig | 1 - configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 - configs/lx2160ardb_tfa_defconfig | 1 - configs/lx2160ardb_tfa_stmm_defconfig | 4 - configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 - configs/lx2162aqds_tfa_defconfig | 1 - .../lx2162aqds_tfa_verified_boot_defconfig | 1 - configs/mt7623n_bpir2_defconfig | 1 - configs/mt7629_rfb_defconfig | 1 - configs/mt8183_pumpkin_defconfig | 1 - configs/mt8516_pumpkin_defconfig | 1 - configs/mvebu_puzzle-m801-88f8040_defconfig | 1 - configs/mx6memcal_defconfig | 1 - configs/octeontx2_95xx_defconfig | 1 - configs/octeontx2_96xx_defconfig | 1 - configs/octeontx_81xx_defconfig | 1 - configs/octeontx_83xx_defconfig | 1 - configs/omap4_sdp4430_defconfig | 1 - configs/opos6uldev_defconfig | 1 - configs/pcm052_defconfig | 1 - configs/phycore-am335x-r2-regor_defconfig | 1 - configs/phycore-am335x-r2-wega_defconfig | 1 - configs/pxm2_defconfig | 2 +- configs/qemu-riscv32_defconfig | 2 - configs/qemu-riscv32_smode_defconfig | 2 - configs/qemu-riscv64_defconfig | 2 - configs/qemu-riscv64_smode_defconfig | 2 - configs/qemu-x86_64_defconfig | 2 - configs/qemu-x86_defconfig | 2 - configs/qemu_arm64_defconfig | 2 - configs/qemu_arm_defconfig | 2 - configs/rastaban_defconfig | 2 +- configs/roc-cc-rk3308_defconfig | 1 - configs/rock-pi-n10-rk3399pro_defconfig | 1 - configs/rock-pi-n8-rk3288_defconfig | 1 - configs/rpi_0_w_defconfig | 1 - configs/rpi_defconfig | 1 - configs/rut_defconfig | 2 +- configs/sama5d27_wlsom1_ek_mmc_defconfig | 1 - .../sama5d27_wlsom1_ek_qspiflash_defconfig | 1 - configs/sama5d2_icp_mmc_defconfig | 1 - configs/sama7g5ek_mmc1_defconfig | 1 - configs/sama7g5ek_mmc_defconfig | 1 - configs/sipeed_maix_bitm_defconfig | 1 - configs/sipeed_maix_smode_defconfig | 1 - configs/socfpga_de1_soc_defconfig | 1 - configs/somlabs_visionsom_6ull_defconfig | 1 - configs/stemmy_defconfig | 1 - configs/stm32mp15_basic_defconfig | 3 - configs/stm32mp15_trusted_defconfig | 3 - configs/tbs2910_defconfig | 1 - configs/thuban_defconfig | 2 +- configs/vf610twr_defconfig | 1 - configs/vf610twr_nand_defconfig | 1 - configs/xenguest_arm64_defconfig | 1 - configs/xilinx_versal_mini_defconfig | 1 - configs/xilinx_versal_mini_emmc0_defconfig | 1 - configs/xilinx_versal_mini_emmc1_defconfig | 1 - configs/xilinx_versal_virt_defconfig | 2 - configs/xilinx_zynqmp_mini_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 - configs/xilinx_zynqmp_mini_nand_defconfig | 1 - .../xilinx_zynqmp_mini_nand_single_defconfig | 1 - configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - configs/xilinx_zynqmp_r5_defconfig | 1 - configs/xilinx_zynqmp_virt_defconfig | 9 - configs/zynq_cse_nand_defconfig | 1 - configs/zynq_cse_nor_defconfig | 1 - configs/zynq_cse_qspi_defconfig | 1 - disk/part_efi.c | 11 +- drivers/core/Kconfig | 1 + fs/btrfs/Kconfig | 1 + include/efi_loader.h | 186 +++++++++--------- lib/Kconfig | 8 + lib/Makefile | 2 +- lib/efi_loader/Kconfig | 5 +- 192 files changed, 160 insertions(+), 353 deletions(-) -- 2.32.0.93.g670b81a890-goog

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Re: [PATCH V2] spi: Update speed/mode on change
by Marek Vasut 02 Jul '21

02 Jul '21

On 7/2/21 8:03 PM, Da Xue wrote: > SF: Detected gd25lq128 with page size 256 Bytes, erase size 64 KiB, total > 16 MiB > SPI mode: 3 > meson_spifc spi@8c80: Cannot set mode (err=-19) > Failed to initialize SPI flash at 0:0 (error -19) > > I added spi-rx-bus-width = <1> and spi-tx-bus-width = <1> > > On Fri, Jul 2, 2021 at 1:44 PM Marek Vasut <marex(a)denx.de> wrote: > >> On 7/2/21 7:24 PM, Da Xue wrote: >>> Hi Marek, >>> >>> This patch breaks meson_spifc: >>> >>> SF: Detected gd25lq128 with page size 256 Bytes, erase size 64 KiB, total >>> 16 MiB >>> meson_spifc spi@8c80: Cannot set mode (err=-19) >>> Failed to initialize SPI flash at 0:0 (error -19) >>> >>> Best, >>> >>> Da >>> >>> On Wed, Jun 30, 2021 at 12:49 PM Tom Rini <trini(a)konsulko.com> wrote: >>> >>>> On Thu, Jun 10, 2021 at 02:00:00PM +0200, Marek Vasut wrote: >>>> >>>>> The spi_get_bus_and_cs() may be called on the same bus and chipselect >>>>> with different frequency or mode. This is valid usecase, but the code >>>>> fails to notify the controller of such a configuration change. Call >>>>> spi_set_speed_mode() in case bus frequency or bus mode changed to let >>>>> the controller update the configuration. >>>>> >>>>> The problem can easily be triggered using the sspi command: >>>>> => sspi 0:0@1000 >>>>> => sspi 0:0@2000 >>>>> Without this patch, both transfers happen at 1000 Hz. With this patch, >>>>> the later transfer happens correctly at 2000 Hz. >>>>> >>>>> Signed-off-by: Marek Vasut <marex(a)denx.de> >>>>> Cc: Jagan Teki <jagan(a)amarulasolutions.com> >>>>> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> >>>> >>>> Applied to u-boot/master, thanks! >>>> >>>> -- >>>> Tom >> >> Seems like you're hitting this code in drivers/spi/meson_spifc.c >> >> 250 static int meson_spifc_set_mode(struct udevice *dev, uint mode) >> 251 { >> 252 struct meson_spifc_priv *spifc = dev_get_priv(dev); >> 253 >> 254 if (mode & (SPI_CPHA | SPI_RX_QUAD | SPI_RX_DUAL | >> 255 SPI_TX_QUAD | SPI_TX_DUAL)) >> 256 return -ENODEV; >> >> (the -ENODEV code doesn't look right, it should be some -EOPNOTSUP or so) >> >> Can you check which of the mode bits is set and triggers the condition ? >> >> I think you might be missing something like >> spi-rx-bus-width = <1>; >> spi-tx-bus-width = <1>; >> in your DT, but that's a guess. Can you check which of the mode bits is set and triggers the condition ? Also, where in the DT did you add spi-rx-bus-width = <1> and spi-tx-bus-width = <1> ? Finally, please do not top-post and keep the list on CC.

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[PATCH V2] spi: Update speed/mode on change
by Marek Vasut 02 Jul '21

02 Jul '21

The spi_get_bus_and_cs() may be called on the same bus and chipselect with different frequency or mode. This is valid usecase, but the code fails to notify the controller of such a configuration change. Call spi_set_speed_mode() in case bus frequency or bus mode changed to let the controller update the configuration. The problem can easily be triggered using the sspi command: => sspi 0:0@1000 => sspi 0:0@2000 Without this patch, both transfers happen at 1000 Hz. With this patch, the later transfer happens correctly at 2000 Hz. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Jagan Teki <jagan(a)amarulasolutions.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- V2: Set plat in case it is NULL --- drivers/spi/spi-uclass.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index ee30110b56..d867b27806 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -391,6 +391,8 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, } else if (ret) { dev_err(bus, "Invalid chip select %d:%d (err=%d)\n", busnum, cs, ret); return ret; + } else if (dev) { + plat = dev_get_parent_plat(dev); } if (!device_active(dev)) { @@ -416,12 +418,22 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, goto err; } + /* In case bus frequency or mode changed, update it. */ + if ((speed && bus_data->speed && bus_data->speed != speed) || + (plat && plat->mode != mode)) { + ret = spi_set_speed_mode(bus, speed, mode); + if (ret) + goto err_speed_mode; + } + *busp = bus; *devp = slave; log_debug("%s: bus=%p, slave=%p\n", __func__, bus, *devp); return 0; +err_speed_mode: + spi_release_bus(slave); err: log_debug("%s: Error path, created=%d, device '%s'\n", __func__, created, dev->name); -- 2.30.2

3 3

[PATCH v2 2/3] net: xilinx: axi_mrmac: Add MRMAC driver
by Ashok Reddy Soma 02 Jul '21

02 Jul '21

Add support for xilinx multirate(MRMAC) ethernet driver. This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC. Added support for 4 ports of MRMAC for speeds 10G and 25G. MCDMA supports upto 16 channels but in this driver we have setup only one channel which is enough. Tested 10G and 25G on all 4 ports. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> --- Changes in v2: - Changed all static allocations to dynamic and freed them. - Used setbits_le32 and clrbits_le32 wherever applicable - All return's are changed to proper error codes instead of 1 or -1 - Changed return type of isrxready() from int to bool - Changed all printf's to log_warning, and debug to log_debug - Added function headers with desciption - Changed all capital hex numbers to small hex numbers MAINTAINERS | 1 + drivers/net/Kconfig | 9 + drivers/net/Makefile | 1 + drivers/net/xilinx_axi_mrmac.c | 564 +++++++++++++++++++++++++++++++++ drivers/net/xilinx_axi_mrmac.h | 203 ++++++++++++ 5 files changed, 778 insertions(+) create mode 100644 drivers/net/xilinx_axi_mrmac.c create mode 100644 drivers/net/xilinx_axi_mrmac.h diff --git a/MAINTAINERS b/MAINTAINERS index 2accd1fb83..cc05e13968 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -543,6 +543,7 @@ M: Michal Simek <michal.simek(a)xilinx.com> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-versal/ +F: drivers/net/xilinx_axi_mrmac.* F: drivers/watchdog/xilinx_wwdt.c N: (?<!uni)versal diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 9fc28b149d..ccc5fc8fb6 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -617,6 +617,15 @@ config XILINX_AXIEMAC help This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs. +config XILINX_AXIMRMAC + depends on DM_ETH && ARCH_VERSAL + bool "Xilinx AXI MRMAC" + help + MRMAC is a high performance, low latency, adaptable Ethernet + integrated hard IP. This can be configured up to four ports with MAC + rates from 10GE to 100GE. This could be present in some of the Xilinx + Versal designs. + config XILINX_EMACLITE depends on DM_ETH select PHYLIB diff --git a/drivers/net/Makefile b/drivers/net/Makefile index d56baa65b2..77a1d23dd3 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -78,6 +78,7 @@ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o obj-$(CONFIG_ULI526X) += uli526x.o obj-$(CONFIG_VSC7385_ENET) += vsc7385.o obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o +obj-$(CONFIG_XILINX_AXIMRMAC) += xilinx_axi_mrmac.o obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ diff --git a/drivers/net/xilinx_axi_mrmac.c b/drivers/net/xilinx_axi_mrmac.c new file mode 100644 index 0000000000..6d15386c66 --- /dev/null +++ b/drivers/net/xilinx_axi_mrmac.c @@ -0,0 +1,564 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx Multirate Ethernet MAC(MRMAC) driver + * + * Author(s): Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> + * Michal Simek <michal.simek(a)xilinx.com> + * + * Copyright (C) 2021 Xilinx, Inc. All rights reserved. + */ + +#include <config.h> +#include <common.h> +#include <cpu_func.h> +#include <dm.h> +#include <log.h> +#include <net.h> +#include <malloc.h> +#include <wait_bit.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <linux/ethtool.h> +#include "xilinx_axi_mrmac.h" + +static void axi_mrmac_dma_write(struct mcdma_bd *bd, u32 *desc) +{ + if (IS_ENABLED(CONFIG_PHYS_64BIT)) + writeq((unsigned long)bd, desc); + else + writel((uintptr_t)bd, desc); +} + +/** + * axi_mrmac_ethernet_init - MRMAC init function + * @priv: MRMAC private structure + * + * Return: 0 on success, negative value on errors + * + * This function is called to reset and initialize MRMAC core. This is + * typically called during initialization. It does a reset of MRMAC Rx/Tx + * channels and Rx/Tx SERDES. It configures MRMAC speed based on mrmac_rate + * which is read from DT. This function waits for block lock bit to get set, + * if it is not set within 100ms time returns a timeout error. + */ +static int axi_mrmac_ethernet_init(struct axi_mrmac_priv *priv) +{ + struct mrmac_regs *regs = priv->iobase; + u32 reg; + u32 ret; + + /* Perform all the RESET's required */ + setbits_le32(&regs->reset, MRMAC_RX_SERDES_RST_MASK | MRMAC_RX_RST_MASK + | MRMAC_TX_SERDES_RST_MASK | MRMAC_TX_RST_MASK); + + mdelay(MRMAC_RESET_DELAY); + + /* Configure Mode register */ + reg = readl(&regs->mode); + + log_debug("Configuring MRMAC speed to %d\n", priv->mrmac_rate); + + if (priv->mrmac_rate == SPEED_25000) { + reg &= ~MRMAC_CTL_RATE_CFG_MASK; + reg |= MRMAC_CTL_DATA_RATE_25G; + reg |= (MRMAC_CTL_AXIS_CFG_25G_IND << MRMAC_CTL_AXIS_CFG_SHIFT); + reg |= (MRMAC_CTL_SERDES_WIDTH_25G << + MRMAC_CTL_SERDES_WIDTH_SHIFT); + } else { + reg &= ~MRMAC_CTL_RATE_CFG_MASK; + reg |= MRMAC_CTL_DATA_RATE_10G; + reg |= (MRMAC_CTL_AXIS_CFG_10G_IND << MRMAC_CTL_AXIS_CFG_SHIFT); + reg |= (MRMAC_CTL_SERDES_WIDTH_10G << + MRMAC_CTL_SERDES_WIDTH_SHIFT); + } + + /* For tick reg */ + reg |= MRMAC_CTL_PM_TICK_MASK; + writel(reg, &regs->mode); + + clrbits_le32(&regs->reset, MRMAC_RX_SERDES_RST_MASK | MRMAC_RX_RST_MASK + | MRMAC_TX_SERDES_RST_MASK | MRMAC_TX_RST_MASK); + + mdelay(MRMAC_RESET_DELAY); + + /* Setup MRMAC hardware options */ + setbits_le32(&regs->rx_config, MRMAC_RX_DEL_FCS_MASK); + setbits_le32(&regs->tx_config, MRMAC_TX_INS_FCS_MASK); + setbits_le32(&regs->tx_config, MRMAC_TX_EN_MASK); + setbits_le32(&regs->rx_config, MRMAC_RX_EN_MASK); + + /* Check for block lock bit to be set. This ensures that + * MRMAC ethernet IP is functioning normally. + */ + writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase + + MRMAC_TX_STS_OFFSET); + writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase + + MRMAC_RX_STS_OFFSET); + writel(MRMAC_STS_ALL_MASK, (phys_addr_t)priv->iobase + + MRMAC_STATRX_BLKLCK_OFFSET); + + ret = wait_for_bit_le32((u32 *)((phys_addr_t)priv->iobase + + MRMAC_STATRX_BLKLCK_OFFSET), + MRMAC_RX_BLKLCK_MASK, true, + MRMAC_BLKLCK_TIMEOUT, true); + if (ret) { + log_warning("Error: MRMAC block lock not complete!\n"); + return -EIO; + } + + writel(MRMAC_TICK_TRIGGER, &regs->tick_reg); + + return 0; +} + +/** + * axi_mcdma_init - Reset MCDMA engine + * @priv: MRMAC private structure + * + * Return: 0 on success, negative value on timeouts + * + * This function is called to reset and initialize MCDMA engine + */ +static int axi_mcdma_init(struct axi_mrmac_priv *priv) +{ + u32 ret; + + /* Reset the engine so the hardware starts from a known state */ + writel(XMCDMA_CR_RESET, &priv->mm2s_cmn->control); + writel(XMCDMA_CR_RESET, &priv->s2mm_cmn->control); + + /* Check Tx/Rx MCDMA.RST. Reset is done when the reset bit is low */ + ret = wait_for_bit_le32(&priv->mm2s_cmn->control, XMCDMA_CR_RESET, + false, MRMAC_DMARST_TIMEOUT, true); + if (ret) { + log_warning("Tx MCDMA reset Timeout\n"); + return -ETIMEDOUT; + } + + ret = wait_for_bit_le32(&priv->s2mm_cmn->control, XMCDMA_CR_RESET, + false, MRMAC_DMARST_TIMEOUT, true); + if (ret) { + log_warning("Rx MCDMA reset Timeout\n"); + return -ETIMEDOUT; + } + + /* Enable channel 1 for Tx and Rx */ + writel(XMCDMA_CHANNEL_1, &priv->mm2s_cmn->chen); + writel(XMCDMA_CHANNEL_1, &priv->s2mm_cmn->chen); + + return 0; +} + +/** + * axi_mrmac_start - MRMAC start + * @dev: udevice structure + * + * Return: 0 on success, negative value on errors + * + * This is a initialization function of MRMAC. Call MCDMA initialization + * function and setup Rx buffer descriptors for starting reception of packets. + * Enable Tx and Rx channels and trigger Rx channel fetch. + */ +static int axi_mrmac_start(struct udevice *dev) +{ + struct axi_mrmac_priv *priv = dev_get_priv(dev); + struct mrmac_regs *regs = priv->iobase; + + /* + * Initialize MCDMA engine. MCDMA engine must be initialized before + * MRMAC. During MCDMA engine initialization, MCDMA hardware is reset, + * since MCDMA reset line is connected to MRMAC, this would ensure a + * reset of MRMAC. + */ + axi_mcdma_init(priv); + + /* Initialize MRMAC hardware */ + if (axi_mrmac_ethernet_init(priv)) + return -EIO; + + /* Disable all Rx interrupts before RxBD space setup */ + clrbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK); + + /* Update current descriptor */ + axi_mrmac_dma_write(priv->rx_bd[0], &priv->mcdma_rx->current); + + /* Setup Rx BD. MRMAC needs atleast two descriptors */ + memset(priv->rx_bd[0], 0, RX_BD_TOTAL_SIZE); + + priv->rx_bd[0]->next_desc = lower_32_bits((u64)priv->rx_bd[1]); + priv->rx_bd[0]->buf_addr = lower_32_bits((u64)net_rx_packets[0]); + + priv->rx_bd[1]->next_desc = lower_32_bits((u64)priv->rx_bd[0]); + priv->rx_bd[1]->buf_addr = lower_32_bits((u64)net_rx_packets[1]); + + if (IS_ENABLED(CONFIG_PHYS_64BIT)) { + priv->rx_bd[0]->next_desc_msb = upper_32_bits((u64)priv->rx_bd[1]); + priv->rx_bd[0]->buf_addr_msb = upper_32_bits((u64)net_rx_packets[0]); + + priv->rx_bd[1]->next_desc_msb = upper_32_bits((u64)priv->rx_bd[0]); + priv->rx_bd[1]->buf_addr_msb = upper_32_bits((u64)net_rx_packets[1]); + } + + priv->rx_bd[0]->cntrl = PKTSIZE_ALIGN; + priv->rx_bd[1]->cntrl = PKTSIZE_ALIGN; + + /* Flush the last BD so DMA core could see the updates */ + flush_cache((phys_addr_t)priv->rx_bd[0], RX_BD_TOTAL_SIZE); + + /* It is necessary to flush rx buffers because if you don't do it + * then cache can contain uninitialized data + */ + flush_cache((phys_addr_t)priv->rx_bd[0]->buf_addr, RX_BUFF_TOTAL_SIZE); + + /* Start the hardware */ + setbits_le32(&priv->s2mm_cmn->control, XMCDMA_CR_RUNSTOP_MASK); + setbits_le32(&priv->mm2s_cmn->control, XMCDMA_CR_RUNSTOP_MASK); + setbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK); + + /* Channel fetch */ + setbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK); + + /* Update tail descriptor. Now it's ready to receive data */ + axi_mrmac_dma_write(priv->rx_bd[1], &priv->mcdma_rx->tail); + + /* Enable Tx */ + setbits_le32(&regs->tx_config, MRMAC_TX_EN_MASK); + + /* Enable Rx */ + setbits_le32(&regs->rx_config, MRMAC_RX_EN_MASK); + + return 0; +} + +/** + * axi_mrmac_send - MRMAC Tx function + * @dev: udevice structure + * @ptr: pointer to Tx buffer + * @len: transfer length + * + * Return: 0 on success, negative value on errors + * + * This is a Tx send function of MRMAC. Setup Tx buffer descriptors and trigger + * transfer. Wait till the data is transferred. + */ +static int axi_mrmac_send(struct udevice *dev, void *ptr, int len) +{ + struct axi_mrmac_priv *priv = dev_get_priv(dev); + u32 ret; + +#ifdef DEBUG + print_buffer(ptr, ptr, 1, len, 16); +#endif + if (len > PKTSIZE_ALIGN) + len = PKTSIZE_ALIGN; + + /* If size is less than min packet size, pad to min size */ + if (len < MIN_PKT_SIZE) { + memset(priv->txminframe, 0, MIN_PKT_SIZE); + memcpy(priv->txminframe, ptr, len); + len = MIN_PKT_SIZE; + ptr = priv->txminframe; + } + + writel(XMCDMA_IRQ_ALL_MASK, &priv->mcdma_tx->status); + + clrbits_le32(&priv->mcdma_tx->control, XMCDMA_CR_RUNSTOP_MASK); + + /* Flush packet to main memory to be trasfered by DMA */ + flush_cache((phys_addr_t)ptr, len); + + /* Setup Tx BD. MRMAC needs atleast two descriptors */ + memset(priv->tx_bd[0], 0, TX_BD_TOTAL_SIZE); + + priv->tx_bd[0]->next_desc = lower_32_bits((u64)priv->tx_bd[1]); + priv->tx_bd[0]->buf_addr = lower_32_bits((u64)ptr); + + /* At the end of the ring, link the last BD back to the top */ + priv->tx_bd[1]->next_desc = lower_32_bits((u64)priv->tx_bd[0]); + priv->tx_bd[1]->buf_addr = lower_32_bits((u64)ptr + len / 2); + + if (IS_ENABLED(CONFIG_PHYS_64BIT)) { + priv->tx_bd[0]->next_desc_msb = upper_32_bits((u64)priv->tx_bd[1]); + priv->tx_bd[0]->buf_addr_msb = upper_32_bits((u64)ptr); + + priv->tx_bd[1]->next_desc_msb = upper_32_bits((u64)priv->tx_bd[0]); + priv->tx_bd[1]->buf_addr_msb = upper_32_bits((u64)ptr + len / 2); + } + + /* Split Tx data in to half and send in two descriptors */ + priv->tx_bd[0]->cntrl = (len / 2) | XMCDMA_BD_CTRL_TXSOF_MASK; + priv->tx_bd[1]->cntrl = (len - len / 2) | XMCDMA_BD_CTRL_TXEOF_MASK; + + /* Flush the last BD so DMA core could see the updates */ + flush_cache((phys_addr_t)priv->tx_bd[0], TX_BD_TOTAL_SIZE); + + if (readl(&priv->mcdma_tx->status) & XMCDMA_CH_IDLE) { + axi_mrmac_dma_write(priv->tx_bd[0], &priv->mcdma_tx->current); + /* Channel fetch */ + setbits_le32(&priv->mcdma_tx->control, XMCDMA_CR_RUNSTOP_MASK); + } else { + log_warning("Error: current desc is not updated\n"); + return -EIO; + } + + setbits_le32(&priv->mcdma_tx->control, XMCDMA_IRQ_ALL_MASK); + + /* Start transfer */ + axi_mrmac_dma_write(priv->tx_bd[1], &priv->mcdma_tx->tail); + + /* Wait for transmission to complete */ + ret = wait_for_bit_le32(&priv->mcdma_tx->status, XMCDMA_IRQ_IOC_MASK, + true, 1, true); + if (ret) { + log_warning("%s: Timeout\n", __func__); + return -ETIMEDOUT; + } + + /* Clear status */ + priv->tx_bd[0]->sband_stats = 0; + priv->tx_bd[1]->sband_stats = 0; + + log_debug("Sending complete\n"); + + return 0; +} + +static bool isrxready(struct axi_mrmac_priv *priv) +{ + u32 status; + + /* Read pending interrupts */ + status = readl(&priv->mcdma_rx->status); + + /* Acknowledge pending interrupts */ + writel(status & XMCDMA_IRQ_ALL_MASK, &priv->mcdma_rx->status); + + /* + * If Reception done interrupt is asserted, call Rx call back function + * to handle the processed BDs and then raise the according flag. + */ + if (status & (XMCDMA_IRQ_IOC_MASK | XMCDMA_IRQ_DELAY_MASK)) + return 1; + + return 0; +} + +/** + * axi_mrmac_recv - MRMAC Rx function + * @dev: udevice structure + * @flags: flags from network stack + * @packetp pointer to received data + * + * Return: received data length on success, negative value on errors + * + * This is a Rx function of MRMAC. Check if any data is received on MCDMA. + * Copy buffer pointer to packetp and return received data length. + */ +static int axi_mrmac_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct axi_mrmac_priv *priv = dev_get_priv(dev); + u32 rx_bd_end; + u32 length; + + /* Wait for an incoming packet */ + if (!isrxready(priv)) + return -EAGAIN; + + /* Clear all interrupts */ + writel(XMCDMA_IRQ_ALL_MASK, &priv->mcdma_rx->status); + + /* Disable IRQ for a moment till packet is handled */ + clrbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK); + + /* Disable channel fetch */ + clrbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK); + + rx_bd_end = (ulong)priv->rx_bd[0] + roundup(RX_BD_TOTAL_SIZE, + ARCH_DMA_MINALIGN); + /* Invalidate Rx descriptors to see proper Rx length */ + invalidate_dcache_range((phys_addr_t)priv->rx_bd[0], rx_bd_end); + + length = priv->rx_bd[0]->status & XMCDMA_BD_STS_ACTUAL_LEN_MASK; + *packetp = (uchar *)(ulong)priv->rx_bd[0]->buf_addr; + + if (!length) { + length = priv->rx_bd[1]->status & XMCDMA_BD_STS_ACTUAL_LEN_MASK; + *packetp = (uchar *)(ulong)priv->rx_bd[1]->buf_addr; + } + +#ifdef DEBUG + print_buffer(*packetp, *packetp, 1, length, 16); +#endif + /* Clear status */ + priv->rx_bd[0]->status = 0; + priv->rx_bd[1]->status = 0; + + return length; +} + +/** + * axi_mrmac_free_pkt - MRMAC free packet function + * @dev: udevice structure + * @packet: receive buffer pointer + * @length received data length + * + * Return: 0 on success, negative value on errors + * + * This is Rx free packet function of MRMAC. Prepare MRMAC for reception of + * data again. Invalidate previous data from Rx buffers and set Rx buffer + * descriptors. Trigger reception by updating tail descriptor. + */ +static int axi_mrmac_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct axi_mrmac_priv *priv = dev_get_priv(dev); + +#ifdef DEBUG + /* It is useful to clear buffer to be sure that it is consistent */ + memset(priv->rx_bd[0]->buf_addr, 0, RX_BUFF_TOTAL_SIZE); +#endif + /* Disable all Rx interrupts before RxBD space setup */ + clrbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK); + + /* Disable channel fetch */ + clrbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK); + + /* Update current descriptor */ + axi_mrmac_dma_write(priv->rx_bd[0], &priv->mcdma_rx->current); + + /* Write bd to HW */ + flush_cache((phys_addr_t)priv->rx_bd[0], RX_BD_TOTAL_SIZE); + + /* It is necessary to flush rx buffers because if you don't do it + * then cache will contain previous packet + */ + flush_cache((phys_addr_t)priv->rx_bd[0]->buf_addr, RX_BUFF_TOTAL_SIZE); + + /* Enable all IRQ */ + setbits_le32(&priv->mcdma_rx->control, XMCDMA_IRQ_ALL_MASK); + + /* Channel fetch */ + setbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK); + + /* Update tail descriptor. Now it's ready to receive data */ + axi_mrmac_dma_write(priv->rx_bd[1], &priv->mcdma_rx->tail); + + log_debug("Rx completed, framelength = %x\n", length); + + return 0; +} + +/** + * axi_mrmac_stop - Stop MCDMA transfers + * @dev: udevice structure + * + * Return: 0 on success, negative value on errors + * + * Stop MCDMA engine for both Tx and Rx transfers. + */ +static void axi_mrmac_stop(struct udevice *dev) +{ + struct axi_mrmac_priv *priv = dev_get_priv(dev); + + /* Stop the hardware */ + clrbits_le32(&priv->mcdma_tx->control, XMCDMA_CR_RUNSTOP_MASK); + clrbits_le32(&priv->mcdma_rx->control, XMCDMA_CR_RUNSTOP_MASK); + + log_debug("Halted\n"); +} + +static int axi_mrmac_probe(struct udevice *dev) +{ + struct axi_mrmac_plat *plat = dev_get_plat(dev); + struct eth_pdata *pdata = &plat->eth_pdata; + struct axi_mrmac_priv *priv = dev_get_priv(dev); + + priv->iobase = (struct mrmac_regs *)pdata->iobase; + + priv->mm2s_cmn = plat->mm2s_cmn; + priv->mcdma_tx = (struct mcdma_chan_reg *)((phys_addr_t)priv->mm2s_cmn + + XMCDMA_CHAN_OFFSET); + priv->s2mm_cmn = (struct mcdma_common_regs *)((phys_addr_t)priv->mm2s_cmn + + XMCDMA_RX_OFFSET); + priv->mcdma_rx = (struct mcdma_chan_reg *)((phys_addr_t)priv->s2mm_cmn + + XMCDMA_CHAN_OFFSET); + priv->mrmac_rate = plat->mrmac_rate; + + /* Align buffers to ARCH_DMA_MINALIGN */ + priv->tx_bd[0] = memalign(ARCH_DMA_MINALIGN, TX_BD_TOTAL_SIZE); + priv->tx_bd[1] = (struct mcdma_bd *)((ulong)priv->tx_bd[0] + + sizeof(struct mcdma_bd)); + + priv->rx_bd[0] = memalign(ARCH_DMA_MINALIGN, RX_BD_TOTAL_SIZE); + priv->rx_bd[1] = (struct mcdma_bd *)((ulong)priv->rx_bd[0] + + sizeof(struct mcdma_bd)); + + priv->txminframe = memalign(ARCH_DMA_MINALIGN, MIN_PKT_SIZE); + + return 0; +} + +static int axi_mrmac_remove(struct udevice *dev) +{ + struct axi_mrmac_priv *priv = dev_get_priv(dev); + + /* Free buffer descriptors */ + free(priv->tx_bd[0]); + free(priv->rx_bd[0]); + free(priv->txminframe); + + return 0; +} + +static int axi_mrmac_of_to_plat(struct udevice *dev) +{ + struct axi_mrmac_plat *plat = dev_get_plat(dev); + struct eth_pdata *pdata = &plat->eth_pdata; + struct ofnode_phandle_args phandle_args; + int ret = 0; + + pdata->iobase = dev_read_addr(dev); + + ret = dev_read_phandle_with_args(dev, "axistream-connected", NULL, 0, 0, + &phandle_args); + if (ret) { + log_debug("axistream not found\n"); + return -EINVAL; + } + + plat->mm2s_cmn = (struct mcdma_common_regs *)ofnode_read_u64_default + (phandle_args.node, "reg", -1); + if (!plat->mm2s_cmn) { + log_warning("MRMAC dma register space not found\n"); + return -EINVAL; + } + + /* Set default MRMAC rate to 10000 */ + plat->mrmac_rate = dev_read_u32_default(dev, "xlnx,mrmac-rate", 10000); + + return 0; +} + +static const struct eth_ops axi_mrmac_ops = { + .start = axi_mrmac_start, + .send = axi_mrmac_send, + .recv = axi_mrmac_recv, + .free_pkt = axi_mrmac_free_pkt, + .stop = axi_mrmac_stop, +}; + +static const struct udevice_id axi_mrmac_ids[] = { + { .compatible = "xlnx,mrmac-ethernet-1.0" }, + { } +}; + +U_BOOT_DRIVER(axi_mrmac) = { + .name = "axi_mrmac", + .id = UCLASS_ETH, + .of_match = axi_mrmac_ids, + .of_to_plat = axi_mrmac_of_to_plat, + .probe = axi_mrmac_probe, + .remove = axi_mrmac_remove, + .ops = &axi_mrmac_ops, + .priv_auto = sizeof(struct axi_mrmac_priv), + .plat_auto = sizeof(struct axi_mrmac_plat), +}; diff --git a/drivers/net/xilinx_axi_mrmac.h b/drivers/net/xilinx_axi_mrmac.h new file mode 100644 index 0000000000..4f875857cf --- /dev/null +++ b/drivers/net/xilinx_axi_mrmac.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Multirate Ethernet MAC(MRMAC) driver + * + * Author(s): Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> + * Michal Simek <michal.simek(a)xilinx.com> + * + * Copyright (C) 2021 Xilinx, Inc. All rights reserved. + */ + +#ifndef __XILINX_AXI_MRMAC_H +#define __XILINX_AXI_MRMAC_H + +#define MIN_PKT_SIZE 60 + +/* MRMAC needs atleast two buffer descriptors for Tx/Rx to work. + * Otherwise MRMAC will drop the packets. So, have atleast two Tx and + * two Rx bd's. + */ +#define TX_DESC 2 +#define RX_DESC 2 + +/* MRMAC platform data structure */ +struct axi_mrmac_plat { + struct eth_pdata eth_pdata; + struct mcdma_common_regs *mm2s_cmn; + u32 mrmac_rate; /* Hold the value from DT property "mrmac-rate" */ +}; + +/* MRMAC private driver structure */ +struct axi_mrmac_priv { + struct mrmac_regs *iobase; + struct mcdma_common_regs *mm2s_cmn; + struct mcdma_common_regs *s2mm_cmn; + struct mcdma_chan_reg *mcdma_tx; + struct mcdma_chan_reg *mcdma_rx; + struct mcdma_bd *tx_bd[TX_DESC]; + struct mcdma_bd *rx_bd[RX_DESC]; + u8 *txminframe; /* Pointer to hold min length Tx frame(60) */ + u32 mrmac_rate; /* Speed to configure(Read from DT 10G/25G..) */ +}; + +/* MRMAC Register Definitions */ +struct mrmac_regs { + u32 revision; /* 0x0: Revision Register */ + u32 reset; /* 0x4: Reset Register */ + u32 mode; /* 0x8: Mode */ + u32 tx_config; /* 0xc: Tx Configuration */ + u32 rx_config; /* 0x10: Rx Configuration */ + u32 reserved[6];/* 0x14-0x28: Reserved */ + u32 tick_reg; /* 0x2c: Tick Register */ +}; + +#define TX_BD_TOTAL_SIZE (TX_DESC * sizeof(struct mcdma_bd)) +#define RX_BD_TOTAL_SIZE (RX_DESC * sizeof(struct mcdma_bd)) + +#define RX_BUFF_TOTAL_SIZE (RX_DESC * PKTSIZE_ALIGN) + +/* Status Registers */ +#define MRMAC_TX_STS_OFFSET 0x740 +#define MRMAC_RX_STS_OFFSET 0x744 +#define MRMAC_TX_RT_STS_OFFSET 0x748 +#define MRMAC_RX_RT_STS_OFFSET 0x74c +#define MRMAC_STATRX_BLKLCK_OFFSET 0x754 + +/* Register bit masks */ +#define MRMAC_RX_SERDES_RST_MASK (BIT(3) | BIT(2) | BIT(1) | BIT(0)) +#define MRMAC_TX_SERDES_RST_MASK BIT(4) +#define MRMAC_RX_RST_MASK BIT(5) +#define MRMAC_TX_RST_MASK BIT(6) +#define MRMAC_RX_AXI_RST_MASK BIT(8) +#define MRMAC_TX_AXI_RST_MASK BIT(9) +#define MRMAC_STS_ALL_MASK 0xffffffff + +#define MRMAC_RX_EN_MASK BIT(0) +#define MRMAC_RX_DEL_FCS_MASK BIT(1) + +#define MRMAC_TX_EN_MASK BIT(0) +#define MRMAC_TX_INS_FCS_MASK BIT(1) + +#define MRMAC_RX_BLKLCK_MASK BIT(0) + +#define MRMAC_TICK_TRIGGER BIT(0) + +#define MRMAC_RESET_DELAY 1 /* Delay in msecs */ +#define MRMAC_BLKLCK_TIMEOUT 100 /* Block lock timeout in msecs */ +#define MRMAC_DMARST_TIMEOUT 500 /* MCDMA reset timeout in msecs */ + +#define XMCDMA_RX_OFFSET 0x500 +#define XMCDMA_CHAN_OFFSET 0x40 + +/* MCDMA Channel numbers are from 1-16 */ +#define XMCDMA_CHANNEL_1 BIT(0) +#define XMCDMA_CHANNEL_2 BIT(1) + +#define XMCDMA_CR_RUNSTOP BIT(0) +#define XMCDMA_CR_RESET BIT(2) + +#define XMCDMA_BD_CTRL_TXSOF_MASK BIT(31) /* First tx packet */ +#define XMCDMA_BD_CTRL_TXEOF_MASK BIT(30) /* Last tx packet */ +#define XMCDMA_BD_CTRL_ALL_MASK GENMASK(31, 30) /* All control bits */ +#define XMCDMA_BD_STS_ALL_MASK GENMASK(31, 28) /* All status bits */ + +/* MCDMA Mask registers */ +#define XMCDMA_CR_RUNSTOP_MASK BIT(0) /* Start/stop DMA channel */ +#define XMCDMA_CR_RESET_MASK BIT(2) /* Reset DMA engine */ + +#define XMCDMA_SR_HALTED_MASK BIT(0) +#define XMCDMA_SR_IDLE_MASK BIT(1) + +#define XMCDMA_CH_IDLE BIT(0) + +#define XMCDMA_BD_STS_COMPLETE BIT(31) /* Completed */ +#define XMCDMA_BD_STS_DEC_ERR BIT(20) /* Decode error */ +#define XMCDMA_BD_STS_SLV_ERR BIT(29) /* Slave error */ +#define XMCDMA_BD_STS_INT_ERR BIT(28) /* Internal err */ +#define XMCDMA_BD_STS_ALL_ERR GENMASK(30, 28) /* All errors */ + +#define XMCDMA_IRQ_ERRON_OTHERQ_MASK BIT(3) +#define XMCDMA_IRQ_PKTDROP_MASK BIT(4) +#define XMCDMA_IRQ_IOC_MASK BIT(5) +#define XMCDMA_IRQ_DELAY_MASK BIT(6) +#define XMCDMA_IRQ_ERR_MASK BIT(7) +#define XMCDMA_IRQ_ALL_MASK GENMASK(7, 5) +#define XMCDMA_PKTDROP_COALESCE_MASK GENMASK(15, 8) +#define XMCDMA_COALESCE_MASK GENMASK(23, 16) +#define XMCDMA_DELAY_MASK GENMASK(31, 24) + +#define MRMAC_CTL_DATA_RATE_MASK GENMASK(2, 0) +#define MRMAC_CTL_DATA_RATE_10G 0 +#define MRMAC_CTL_DATA_RATE_25G 1 +#define MRMAC_CTL_DATA_RATE_40G 2 +#define MRMAC_CTL_DATA_RATE_50G 3 +#define MRMAC_CTL_DATA_RATE_100G 4 + +#define MRMAC_CTL_AXIS_CFG_MASK GENMASK(11, 9) +#define MRMAC_CTL_AXIS_CFG_SHIFT 9 +#define MRMAC_CTL_AXIS_CFG_10G_IND 1 +#define MRMAC_CTL_AXIS_CFG_25G_IND 1 + +#define MRMAC_CTL_SERDES_WIDTH_MASK GENMASK(6, 4) +#define MRMAC_CTL_SERDES_WIDTH_SHIFT 4 +#define MRMAC_CTL_SERDES_WIDTH_10G 4 +#define MRMAC_CTL_SERDES_WIDTH_25G 6 + +#define MRMAC_CTL_RATE_CFG_MASK (MRMAC_CTL_DATA_RATE_MASK | \ + MRMAC_CTL_AXIS_CFG_MASK | \ + MRMAC_CTL_SERDES_WIDTH_MASK) + +#define MRMAC_CTL_PM_TICK_MASK BIT(30) +#define MRMAC_TICK_TRIGGER BIT(0) + +#define XMCDMA_BD_STS_ACTUAL_LEN_MASK 0x007fffff /* Actual length */ + +/* MCDMA common offsets */ +struct mcdma_common_regs { + u32 control; /* Common control */ + u32 status; /* Common status */ + u32 chen; /* Channel enable/disable */ + u32 chser; /* Channel in progress */ + u32 err; /* Error */ + u32 ch_schd_type; /* Channel Q scheduler type */ + u32 wrr_reg1; /* Weight of each channel (ch1-8) */ + u32 wrr_reg2; /* Weight of each channel (ch9-16) */ + u32 ch_serviced; /* Channels completed */ + u32 arcache_aruser; /* ARCACHE and ARUSER values for AXI4 read */ + u32 intr_status; /* Interrupt monitor */ + u32 reserved[5]; +}; + +/* MCDMA per-channel registers */ +struct mcdma_chan_reg { + u32 control; /* Control */ + u32 status; /* Status */ + u32 current; /* Current descriptor */ + u32 current_hi; /* Current descriptor high 32bit */ + u32 tail; /* Tail descriptor */ + u32 tail_hi; /* Tail descriptor high 32bit */ + u32 pktcnt; /* Packet processed count */ +}; + +/* MCDMA buffer descriptors */ +struct mcdma_bd { + u32 next_desc; /* Next descriptor pointer */ + u32 next_desc_msb; + u32 buf_addr; /* Buffer address */ + u32 buf_addr_msb; + u32 reserved1; + u32 cntrl; /* Control */ + u32 status; /* Status */ + u32 sband_stats; + u32 app0; + u32 app1; /* Tx start << 16 | insert */ + u32 app2; /* Tx csum seed */ + u32 app3; + u32 app4; + u32 sw_id_offset; + u32 reserved2; + u32 reserved3; + u32 reserved4[16]; +}; + +#endif /* __XILINX_AXI_MRMAC_H */ -- 2.17.1

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