June 2021 - U-Boot

[PATCH 00/10] stm32mp: stm32prog: several features and fixes
by Patrick Delaunay 18 Jun '21

18 Jun '21

This serie provides several evolution and patches for the command stm32prog used on STM32MP platform to communicate with the STMicroelectonics tools STM32CubeProgrammer. Patrick Delaunay (10): stm32mp: stm32prog: remove all the header check for UART download stm32mp: stm32prog: add timeout in stm32prog_serial_get_buffer stm32mp: stm32prog: add support of initrd in flashlayout stm32mp: stm32prog: solve compilation with CONFIG_FIT_SIGNATURE stm32mp: stm32prog: handle the next phase after USB re-enumeration stm32mp: stm32prog: correctly handle DM_PMIC stm32mp: stm32prog: use get_cpu_dev for GetID command stm32mp: stm32prog: change one message level to debug dfu: add error callback stm32mp: stm32prog: handle dfu error .../cmd_stm32prog/cmd_stm32prog.c | 26 ++- .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 43 +++-- .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 7 +- .../cmd_stm32prog/stm32prog_serial.c | 173 ++++-------------- .../cmd_stm32prog/stm32prog_usb.c | 7 +- drivers/dfu/dfu.c | 12 ++ include/dfu.h | 11 ++ 7 files changed, 108 insertions(+), 171 deletions(-) -- 2.17.1

3 31

[PATCH] board: freescale: common: Refactor I2C mux driver
by Stephen Carlson 18 Jun '21

18 Jun '21

Refactors the NXP I2C mux driver to clean up duplicate code and allow it to be disabled with a config. New config: CONFIG_FSL_USE_PCA9547_MUX. Defaults to Y since this multiplexer was always enabled before on these targets. When enabled, adds functions for selecting the current I2C channel on the PCA9547 mux, which can be used when accessing I2C peripherals on the board. Signed-off-by: Stephen Carlson <stcarlso(a)linux.microsoft.com> Signed-off-by: Wasim Khan <wasim.khan(a)nxp.com> Tested-by: Zhao Zheng <zhao.zheng(a)nxp.com> --- board/freescale/common/Kconfig | 6 ++ board/freescale/common/Makefile | 11 ++++ board/freescale/common/i2c_common.c | 32 ++++++++++ board/freescale/common/i2c_common.h | 28 +++++++++ board/freescale/common/i2c_mux.c | 38 ++++++++++++ board/freescale/common/i2c_mux.h | 13 +++++ board/freescale/common/vid.c | 58 ++++--------------- board/freescale/ls1021aqds/dcu.c | 26 +-------- board/freescale/ls1021aqds/ls1021aqds.c | 26 +-------- board/freescale/ls1043aqds/ls1043aqds.c | 27 +-------- board/freescale/ls1046afrwy/ls1046afrwy.c | 27 +-------- board/freescale/ls1046aqds/ls1046aqds.c | 26 +-------- board/freescale/ls1088a/ls1088a.c | 32 ++-------- board/freescale/ls2080aqds/ls2080aqds.c | 25 +------- board/freescale/ls2080ardb/ls2080ardb.c | 27 +-------- board/freescale/lx2160a/lx2160a.c | 31 ++-------- board/freescale/t208xqds/t208xqds.c | 26 +-------- configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SECURE_BOOT_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080QDS_defconfig | 1 + configs/ls1021aqds_ddr4_nor_defconfig | 1 + configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021aqds_nor_defconfig | 1 + configs/ls1021aqds_nor_lpuart_defconfig | 1 + configs/ls1021aqds_qspi_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_defconfig | 1 + configs/ls1043aqds_lpuart_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_nor_ddr3_defconfig | 1 + configs/ls1043aqds_qspi_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1043aqds_tfa_defconfig | 1 + configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046afrwy_tfa_defconfig | 1 + configs/ls1046aqds_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_defconfig | 1 + configs/ls1046aqds_lpuart_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_qspi_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig | 1 + configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046aqds_tfa_defconfig | 1 + configs/ls1088aqds_defconfig | 1 + configs/ls1088aqds_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088aqds_qspi_defconfig | 1 + configs/ls1088aqds_sdcard_ifc_defconfig | 1 + configs/ls1088aqds_sdcard_qspi_defconfig | 1 + configs/ls1088aqds_tfa_defconfig | 1 + configs/ls1088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_qspi_defconfig | 1 + ...1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_defconfig | 1 + configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_tfa_defconfig | 1 + configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080aqds_qspi_defconfig | 1 + configs/ls2080aqds_sdcard_defconfig | 1 + configs/ls2080ardb_SECURE_BOOT_defconfig | 1 + configs/ls2080ardb_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 1 + configs/ls2081ardb_defconfig | 1 + configs/ls2088aqds_tfa_defconfig | 1 + configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_qspi_defconfig | 1 + configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2162aqds_tfa_defconfig | 1 + .../lx2162aqds_tfa_verified_boot_defconfig | 1 + 86 files changed, 232 insertions(+), 296 deletions(-) create mode 100644 board/freescale/common/i2c_common.c create mode 100644 board/freescale/common/i2c_common.h create mode 100644 board/freescale/common/i2c_mux.c create mode 100644 board/freescale/common/i2c_mux.h diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 17db755951..ab9c14ae88 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -21,6 +21,12 @@ config CMD_ESBC_VALIDATE esbc_validate - validate signature using RSA verification esbc_halt - put the core in spin loop (Secure Boot Only) +config FSL_USE_PCA9547_MUX + bool "Enable PCA9547 I2C Mux on Freescale boards" + default n + help + This option enables the PCA9547 I2C mux on Freescale boards. + config VID depends on DM_I2C bool "Enable Freescale VID" diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 114b7ba8f9..45aaa16ca4 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -15,6 +15,15 @@ ifdef MINIMAL # necessary to create built-in.o obj- := __dummy__.o else +# include i2c_common.o once if either VID or FSL_USE_PCA9547_MUX +I2C_COMMON= +ifdef CONFIG_VID +I2C_COMMON=y +endif +ifdef CONFIG_FSL_USE_PCA9547_MUX +I2C_COMMON=y +endif + obj-$(CONFIG_FSL_CADMUS) += cadmus.o obj-$(CONFIG_FSL_VIA) += cds_via.o obj-$(CONFIG_FMAN_ENET) += fman.o @@ -22,6 +31,8 @@ obj-$(CONFIG_FSL_PIXIS) += pixis.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o endif +obj-$(I2C_COMMON) += i2c_common.o +obj-$(CONFIG_FSL_USE_PCA9547_MUX) += i2c_mux.o obj-$(CONFIG_VID) += vid.o obj-$(CONFIG_FSL_QIXIS) += qixis.o obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o diff --git a/board/freescale/common/i2c_common.c b/board/freescale/common/i2c_common.c new file mode 100644 index 0000000000..bfae94720e --- /dev/null +++ b/board/freescale/common/i2c_common.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Microsoft Corporation + */ + +#include <common.h> +#include <i2c.h> +#include "i2c_common.h" + +#ifdef CONFIG_DM_I2C + +/* If DM is in use, retrieve the chip for the specified bus number */ +int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev) +{ + int ret = i2c_get_chip_for_busnum(bus, address, 1, dev); + + if (ret) + printf("I2C: Bus %d has no device with address 0x%02X\n", + bus, address); + return ret; +} + +#else + +/* Handle is passed directly */ +int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev) +{ + *dev = address; + return 0; +} + +#endif diff --git a/board/freescale/common/i2c_common.h b/board/freescale/common/i2c_common.h new file mode 100644 index 0000000000..23b465b08c --- /dev/null +++ b/board/freescale/common/i2c_common.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 Microsoft Corporation + */ + +#ifndef __I2C_COMMON_H__ +#define __I2C_COMMON_H__ + +/* Common functionality shared by the I2C drivers for VID and the mux. */ +#ifdef CONFIG_DM_I2C +#define DEVICE_HANDLE_T struct udevice * + +#define I2C_READ(dev, register, data, length) \ + dm_i2c_read(dev, register, data, length) +#define I2C_WRITE(dev, register, data, length) \ + dm_i2c_write(dev, register, data, length) +#else +#define DEVICE_HANDLE_T int + +#define I2C_READ(dev, register, data, length) \ + i2c_read(dev, register, 1, data, length) +#define I2C_WRITE(dev, register, data, length) \ + i2c_write(dev, register, 1, data, length) +#endif + +int fsl_i2c_get_device(int address, int bus, DEVICE_HANDLE_T *dev); + +#endif diff --git a/board/freescale/common/i2c_mux.c b/board/freescale/common/i2c_mux.c new file mode 100644 index 0000000000..18fad6b5a5 --- /dev/null +++ b/board/freescale/common/i2c_mux.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 Microsoft Corporation + */ + +#include <common.h> +#include <i2c.h> +#include "i2c_common.h" +#include "i2c_mux.h" + +/* + * A new Kconfig option for something that used to always be built should be + * “default y”. + */ +#ifdef CONFIG_FSL_USE_PCA9547_MUX + +int select_i2c_ch_pca9547(u8 ch, int bus) +{ + int ret; + DEVICE_HANDLE_T dev; + + /* Open device handle */ + ret = fsl_i2c_get_device(I2C_MUX_PCA_ADDR_PRI, bus, &dev); + if (ret) { + printf("PCA: No PCA9547 device found\n"); + return ret; + } + + ret = I2C_WRITE(dev, 0, &ch, sizeof(ch)); + if (ret) { + printf("PCA: Unable to select channel %d (%d)\n", (int)ch, ret); + return ret; + } + + return 0; +} + +#endif diff --git a/board/freescale/common/i2c_mux.h b/board/freescale/common/i2c_mux.h new file mode 100644 index 0000000000..49ec7b2fbe --- /dev/null +++ b/board/freescale/common/i2c_mux.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 Microsoft Corporation + */ + +#ifndef __I2C_MUX_H__ +#define __I2C_MUX_H__ + +#ifdef CONFIG_FSL_USE_PCA9547_MUX +int select_i2c_ch_pca9547(u8 ch, int bus); +#endif + +#endif diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 6e8296293b..f042627eac 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -20,8 +20,13 @@ #include <asm/immap_85xx.h> #endif #include <linux/delay.h> +#include "i2c_common.h" #include "vid.h" +#ifndef I2C_VOL_MONITOR_BUS +#define I2C_VOL_MONITOR_BUS 0 +#endif + /* Voltages are generally handled in mV to keep them as integers */ #define MV_PER_V 1000 @@ -95,44 +100,6 @@ u16 __weak soc_get_fuse_vid(int vid_index) #define I2C_VOL_MONITOR_ADDR 0 #endif -#if CONFIG_IS_ENABLED(DM_I2C) -#define DEVICE_HANDLE_T struct udevice * - -#ifndef I2C_VOL_MONITOR_BUS -#define I2C_VOL_MONITOR_BUS 0 -#endif - -/* If DM is in use, retrieve the udevice chip for the specified bus number */ -static int vid_get_device(int address, DEVICE_HANDLE_T *dev) -{ - int ret = i2c_get_chip_for_busnum(I2C_VOL_MONITOR_BUS, address, 1, dev); - - if (ret) - printf("VID: Bus %d has no device with address 0x%02X\n", - I2C_VOL_MONITOR_BUS, address); - return ret; -} - -#define I2C_READ(dev, register, data, length) \ - dm_i2c_read(dev, register, data, length) -#define I2C_WRITE(dev, register, data, length) \ - dm_i2c_write(dev, register, data, length) -#else -#define DEVICE_HANDLE_T int - -/* If DM is not in use, I2C addresses are passed directly */ -static int vid_get_device(int address, DEVICE_HANDLE_T *dev) -{ - *dev = address; - return 0; -} - -#define I2C_READ(dev, register, data, length) \ - i2c_read(dev, register, 1, data, length) -#define I2C_WRITE(dev, register, data, length) \ - i2c_write(dev, register, 1, data, length) -#endif - #if defined(CONFIG_VOL_MONITOR_IR36021_SET) || \ defined(CONFIG_VOL_MONITOR_IR36021_READ) /* @@ -158,7 +125,7 @@ static int find_ir_chip_on_i2c(void) /* Check all the address */ for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) { i2caddress = ir_i2c_addr[i]; - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (!ret) { ret = I2C_READ(dev, IR36021_MFR_ID_OFFSET, (void *)&mfrID, sizeof(mfrID)); @@ -202,7 +169,7 @@ static int read_voltage_from_INA220(int i2caddress) DEVICE_HANDLE_T dev; /* Open device handle */ - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -243,7 +210,7 @@ static int read_voltage_from_IR(int i2caddress) DEVICE_HANDLE_T dev; /* Open device handle */ - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -344,7 +311,7 @@ static int read_voltage_from_pmbus(int i2caddress) DEVICE_HANDLE_T dev; /* Open device handle */ - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -457,7 +424,7 @@ static int set_voltage_to_IR(int i2caddress, int vdd) DEVICE_HANDLE_T dev; /* Open device handle */ - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -503,7 +470,7 @@ static int set_voltage_to_pmbus(int i2caddress, int vdd) DEVICE_HANDLE_T dev; /* Open device handle */ - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -653,7 +620,7 @@ int adjust_vdd(ulong vdd_override) debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress); } - ret = vid_get_device(i2caddress, &dev); + ret = fsl_i2c_get_device(i2caddress, I2C_VOL_MONITOR_BUS, &dev); if (ret) return ret; @@ -785,7 +752,6 @@ exit: i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT); return ret < 0 ? -1 : 0; - } static int do_vdd_override(struct cmd_tbl *cmdtp, diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c index 7532f7c0b2..b5fee06b5b 100644 --- a/board/freescale/ls1021aqds/dcu.c +++ b/board/freescale/ls1021aqds/dcu.c @@ -11,37 +11,13 @@ #include <common.h> #include <fsl_dcu_fb.h> #include <i2c.h> +#include "../common/i2c_mux.h" #include "div64.h" #include "../common/diu_ch7301.h" #include "ls1021aqds_qixis.h" DECLARE_GLOBAL_DATA_PTR; -static int select_i2c_ch_pca9547(u8 ch, int bus_num) -{ - int ret; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - ret = dm_i2c_write(dev, 0, &ch, 1); -#else - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - unsigned int dcu_set_pixel_clock(unsigned int pixclock) { unsigned long long div; diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index aa1f6025c1..fcbde2ceb7 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -25,6 +25,7 @@ #include <fsl_devdis.h> #include <fsl_validate.h> #include <fsl_ddr.h> +#include "../common/i2c_mux.h" #include "../common/sleep.h" #include "../common/qixis.h" #include "ls1021aqds_qixis.h" @@ -141,31 +142,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -int select_i2c_ch_pca9547(u8 ch, int bus_num) -{ - int ret; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - ret = dm_i2c_write(dev, 0, &ch, 1); -#else - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - int dram_init(void) { /* diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 5b131d1d67..76bbb6087a 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -28,6 +28,7 @@ #include <fsl_esdhc.h> #include <fsl_ifc.h> #include <spl.h> +#include "../common/i2c_mux.h" #include "../common/qixis.h" #include "ls1043aqds_qixis.h" @@ -279,32 +280,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -int select_i2c_ch_pca9547(u8 ch, int bus_num) -{ - int ret; - -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - ret = dm_i2c_write(dev, 0, &ch, 1); -#else - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - int dram_init(void) { /* diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c index f1709dcd1c..f1c08a13f7 100644 --- a/board/freescale/ls1046afrwy/ls1046afrwy.c +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -22,6 +22,7 @@ #include <fsl_esdhc.h> #include <fsl_sec.h> #include <fsl_dspi.h> +#include "../common/i2c_mux.h" #define LS1046A_PORSR1_REG 0x1EE0000 #define BOOT_SRC_SD 0x20000000 @@ -38,32 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; -int select_i2c_ch_pca9547(u8 ch, int bus_num) -{ - int ret; - -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - ret = dm_i2c_write(dev, 0, &ch, 1); -#else - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - static inline void demux_select_usb2(void) { u32 val; diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 20694426af..2b0786ac30 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -29,6 +29,7 @@ #include <fsl_ifc.h> #include <fsl_sec.h> #include <spl.h> +#include "../common/i2c_mux.h" #include "../common/vid.h" #include "../common/qixis.h" @@ -276,31 +277,6 @@ u32 get_lpuart_clk(void) } #endif -int select_i2c_ch_pca9547(u8 ch, int bus_num) -{ - int ret; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - ret = dm_i2c_write(dev, 0, &ch, 1); -#else - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - int dram_init(void) { /* diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index f5dc449d89..2f422634d5 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -26,6 +26,7 @@ #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> +#include "../common/i2c_mux.h" #include "../common/qixis.h" #include "ls1088a_qixis.h" @@ -415,34 +416,13 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -int select_i2c_ch_pca9547(u8 ch) -{ - int ret; - -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); - if (!ret) - ret = dm_i2c_write(dev, 0, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - #if !defined(CONFIG_SPL_BUILD) void board_retimer_init(void) { u8 reg; /* Retimer is connected to I2C1_CH5 */ - select_i2c_ch_pca9547(I2C_MUX_CH5); + select_i2c_ch_pca9547(I2C_MUX_CH5, 0); /* Access to Control/Shared register */ reg = 0x0; @@ -532,7 +512,7 @@ void board_retimer_init(void) #ifdef CONFIG_TARGET_LS1088AQDS /* Retimer is connected to I2C1_CH5 */ - select_i2c_ch_pca9547(I2C_MUX_CH5); + select_i2c_ch_pca9547(I2C_MUX_CH5, 0); /* Access to Control/Shared register */ reg = 0x0; @@ -620,7 +600,7 @@ void board_retimer_init(void) #endif /*return the default channel*/ - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); } #ifdef CONFIG_MISC_INIT_R @@ -669,7 +649,7 @@ int misc_init_r(void) int i2c_multiplexer_select_vid_channel(u8 channel) { - return select_i2c_ch_pca9547(channel); + return select_i2c_ch_pca9547(channel, 0); } #ifdef CONFIG_TARGET_LS1088AQDS @@ -827,7 +807,7 @@ int board_init(void) u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); board_retimer_init(); #ifdef CONFIG_ENV_IS_NOWHERE diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 9572319234..c48b01f7d7 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -23,7 +23,7 @@ #include <fsl_sec.h> #include <asm/arch/ppa.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> - +#include "../common/i2c_mux.h" #include "../common/qixis.h" #include "ls2080aqds_qixis.h" @@ -161,27 +161,6 @@ unsigned long get_board_ddr_clk(void) return 66666666; } -int select_i2c_ch_pca9547(u8 ch) -{ - int ret; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); - if (!ret) - ret = dm_i2c_write(dev, 0, &ch, 1); - -#else - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - int config_board_mux(int ctrl_type) { u8 reg5; @@ -235,7 +214,7 @@ int board_init(void) #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT #if CONFIG_IS_ENABLED(DM_I2C) diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 3a026b0827..6504cf768f 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -25,6 +25,7 @@ #include <asm/arch/ppa.h> #include <fsl_sec.h> #include <asm/arch-fsl-layerscape/fsl_icid.h> +#include "../common/i2c_mux.h" #ifdef CONFIG_FSL_QIXIS #include "../common/qixis.h" @@ -205,31 +206,9 @@ unsigned long get_board_sys_clk(void) return 100000000; } -int select_i2c_ch_pca9547(u8 ch) -{ - int ret; - -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); - if (!ret) - ret = dm_i2c_write(dev, 0, &ch, 1); -#endif - - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - int i2c_multiplexer_select_vid_channel(u8 channel) { - return select_i2c_ch_pca9547(channel); + return select_i2c_ch_pca9547(channel, 0); } int config_board_mux(int ctrl_type) @@ -267,7 +246,7 @@ int board_init(void) #ifdef CONFIG_ENV_IS_NOWHERE gd->env_addr = (ulong)&default_environment[0]; #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); #ifdef CONFIG_FSL_QIXIS QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 47a7024f33..04a6296a36 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -29,6 +29,8 @@ #include <asm/arch/config.h> #include <asm/arch/fsl_serdes.h> #include <asm/arch/soc.h> +#include "../common/i2c_mux.h" + #include "../common/qixis.h" #include "../common/vid.h" #include <fsl_immap.h> @@ -79,27 +81,6 @@ U_BOOT_DRVINFO(nxp_serial1) = { .plat = &serial1, }; -int select_i2c_ch_pca9547(u8 ch) -{ - int ret; - -#if !CONFIG_IS_ENABLED(DM_I2C) - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#else - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); - if (!ret) - ret = dm_i2c_write(dev, 0, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - static void uart_get_clock(void) { serial0.clock = get_serial_clock(); @@ -115,10 +96,10 @@ int board_early_init_f(void) uart_get_clock(); #ifdef CONFIG_EMC2305 - select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305); + select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305, 0); emc2305_init(I2C_EMC2305_ADDR); set_fan_speed(I2C_EMC2305_PWM, I2C_EMC2305_ADDR); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); #endif fsl_lsch3_early_init_f(); @@ -275,7 +256,7 @@ int esdhc_status_fixup(void *blob, const char *compat) #if defined(CONFIG_VID) int i2c_multiplexer_select_vid_channel(u8 channel) { - return select_i2c_ch_pca9547(channel); + return select_i2c_ch_pca9547(channel, 0); } int init_func_vid(void) @@ -611,7 +592,7 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) /* invert AQR107 IRQ pins polarity */ diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index fd3217f24d..715de106d6 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -22,6 +22,7 @@ #include <asm/fsl_serdes.h> #include <asm/fsl_liodn.h> #include <fm_eth.h> +#include "../common/i2c_mux.h" #include "../common/qixis.h" #include "../common/vsc3316_3308.h" @@ -79,31 +80,6 @@ int checkboard(void) return 0; } -int select_i2c_ch_pca9547(u8 ch, int bus_num) -{ - int ret; - -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - bus_num); - return ret; - } - ret = dm_i2c_write(dev, 0, &ch, 1); -#else - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); -#endif - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - int i2c_multiplexer_select_vid_channel(u8 channel) { return select_i2c_ch_pca9547(channel, 0); diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index ffd23fab6b..62ce9eeecd 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -83,3 +83,4 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index cb5d7ff233..c7987fa3bf 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -80,3 +80,4 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 4d33dc6a3a..f8f031f778 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -70,3 +70,4 @@ CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 1029a8ec34..cdcbf37edc 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -82,3 +82,4 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 0677053e21..9ab1cdfe8c 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -60,3 +60,4 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index c9d1fec300..1cbc947454 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -68,3 +68,4 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_ADDR_MAP=y CONFIG_SYS_NUM_ADDR_MAP=64 +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index a02a9fd955..04ad866731 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -69,3 +69,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index d42e351754..700768294d 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -69,3 +69,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 93cb6bfbf2..d36d957995 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -84,3 +84,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index d3b68b9f95..43e77c95bc 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -68,3 +68,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index a67d040443..26d2e5e567 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -70,3 +70,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 46625f1430..f2d81ce0e1 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -70,3 +70,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 17a7a60b23..1f6f819d91 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -69,3 +69,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 344211826f..4dc3260296 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -83,3 +83,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index c6d5c1ec95..0c1d714eda 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -81,3 +81,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_STORAGE=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig index 42fd350075..2f1da44884 100644 --- a/configs/ls1043aqds_defconfig +++ b/configs/ls1043aqds_defconfig @@ -69,3 +69,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig index 1bafc2bb03..41b304cee8 100644 --- a/configs/ls1043aqds_lpuart_defconfig +++ b/configs/ls1043aqds_lpuart_defconfig @@ -71,3 +71,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index 8fb23acd88..25c5d93fcb 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -85,3 +85,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig index f87c9a7cbf..a324291824 100644 --- a/configs/ls1043aqds_nor_ddr3_defconfig +++ b/configs/ls1043aqds_nor_ddr3_defconfig @@ -70,3 +70,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig index 5de4e07457..3724d392bc 100644 --- a/configs/ls1043aqds_qspi_defconfig +++ b/configs/ls1043aqds_qspi_defconfig @@ -66,3 +66,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 6e3318b1ed..eedabdbc6b 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -86,3 +86,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index cd20980c98..3058442cdd 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -80,3 +80,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 4caabcadb8..ee92209d63 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -72,3 +72,4 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index fb28072638..c15f956b0a 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -79,3 +79,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index f953106a3d..61e3229431 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -60,3 +60,4 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y CONFIG_RSA=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index ea62d7fa7e..6861d22193 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -68,3 +68,4 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig index 7e7ae34226..5d58cc40a2 100644 --- a/configs/ls1046aqds_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_SECURE_BOOT_defconfig @@ -70,3 +70,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig index 8905d450da..205a129bce 100644 --- a/configs/ls1046aqds_defconfig +++ b/configs/ls1046aqds_defconfig @@ -72,3 +72,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig index 6627ac2bb0..0001b55aee 100644 --- a/configs/ls1046aqds_lpuart_defconfig +++ b/configs/ls1046aqds_lpuart_defconfig @@ -74,3 +74,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 9da564a788..d71e13df99 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -80,3 +80,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 6cf46ff2c9..3eb204fd07 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -70,3 +70,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 165c272c41..91fde75c9e 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -90,3 +90,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 8e60a35858..e81096fc2b 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -85,3 +85,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index 7e57b53a1f..f78bbcf695 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -72,3 +72,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 9366bc1d32..919c407618 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -82,3 +82,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig index c0fb4c9872..d9b8c9a18d 100644 --- a/configs/ls1088aqds_defconfig +++ b/configs/ls1088aqds_defconfig @@ -74,3 +74,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig index 57c91c1ad8..518a3ce6b9 100644 --- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig @@ -75,3 +75,4 @@ CONFIG_USB_GADGET=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig index 9abaead1c8..641efd982e 100644 --- a/configs/ls1088aqds_qspi_defconfig +++ b/configs/ls1088aqds_qspi_defconfig @@ -76,3 +76,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 44d4c13632..b70720c1d7 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -82,3 +82,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index dadea57078..764df3b698 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -85,3 +85,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index 5229a351e1..9edabc9c80 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -100,3 +100,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig index de3759951e..97912da79b 100644 --- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig @@ -77,3 +77,4 @@ CONFIG_USB_GADGET=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig index 0e32aeb634..0ef9ef3da5 100644 --- a/configs/ls1088ardb_qspi_defconfig +++ b/configs/ls1088ardb_qspi_defconfig @@ -78,3 +78,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 7b85bf6174..847afa9cef 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -88,3 +88,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_RSA=y CONFIG_SPL_RSA=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index 59469d3b7e..25115f4658 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -87,3 +87,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_GADGET=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig index 84fbab0f42..d1f75ef76c 100644 --- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig @@ -86,3 +86,4 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 007a80c2c6..f54339930b 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -92,3 +92,4 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index bfa697c9ef..9e687f8066 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -68,3 +68,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 6f9cce5b25..a13e471a68 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -69,3 +69,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index cc0f2b16aa..808140f10b 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -76,3 +76,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index cbdf733456..51ab47a583 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -68,3 +68,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 71174de458..79fa0e179f 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -75,3 +75,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index 1175aafadb..b3cc52ba03 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -66,3 +66,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index 53abd06ec6..b3c5001c50 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -67,3 +67,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 93032edc0c..63fadc5255 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -72,3 +72,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index ab1a9e22e0..d9134d6a01 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -65,3 +65,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 5620e8a786..bbd76e31d6 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -90,3 +90,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index 10c139c98e..fb77c8942e 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -67,3 +67,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 58fc6b2384..c09568b52a 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -72,3 +72,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index eed26fa898..032d6125f2 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -83,3 +83,4 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index 56cd02418c..522b381bb7 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -88,3 +88,4 @@ CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 54d88c88d5..75a6bdd19a 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -86,3 +86,4 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index d25d3e8b98..fafe42c559 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -92,3 +92,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 1d61807c11..501e9ae44a 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -77,3 +77,4 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index a160cfe21e..4b8e7edf94 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -87,3 +87,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index 8b69a36dd9..06cfacab6d 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -86,3 +86,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_EFI_MM_COMM_TEE=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index fcc78c6fe5..8dc601ff2c 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -89,3 +89,4 @@ CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index 42a3a3af44..d493bc1e7f 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -96,3 +96,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index bf0ac38ff2..8ff6f8113e 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -97,3 +97,4 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SBSA=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_FSL_USE_PCA9547_MUX=y -- 2.25.1

2 1

[PATCH] clk: cosmetic change in uclass
by Patrick Delaunay 18 Jun '21

18 Jun '21

Remove the tab in clk_get_bulk to respect the coding rules. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/clk/clk-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 4ab3c402ed..b126c5ed60 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -159,7 +159,7 @@ int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk) int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk) { int i, ret, err, count; - + bulk->count = 0; count = dev_count_phandle_with_args(dev, "clocks", "#clock-cells", 0); -- 2.17.1

2 2

[PATCH] board: stm32mp1: correct the property name for eth
by Patrick Delaunay 18 Jun '21

18 Jun '21

Use the correct name for STMicroelectronics phys config properties, replace '_' by '-': "st,eth_clk_sel" => "st,eth-clk-sel" "st,eth-ref-clk-sel" => st,eth-clk-sel" These property name are aligned with the upstreamed Linux kernel binding: linux/Documentation/devicetree/bindings/net/stm32-dwmac.yaml See Linux kernel commit "dt-bindings: net: stmmac: add phys config properties" merged in v5.1-rc1. This patch allow to reuse the kernel device tree directly in U-Boot. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- board/dhelectronics/dh_stm32mp1/board.c | 4 ++-- board/st/stm32mp1/stm32mp1.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index ac1af718d4..d7c1857c16 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -660,11 +660,11 @@ int board_interface_eth_init(struct udevice *dev, bool eth_ref_clk_sel_reg = false; /* Gigabit Ethernet 125MHz clock selection. */ - eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel"); + eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); /* Ethernet 50Mhz RMII clock selection */ eth_ref_clk_sel_reg = - dev_read_bool(dev, "st,eth_ref_clk_sel"); + dev_read_bool(dev, "st,eth-ref-clk-sel"); syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 261ec15e1b..18b8870269 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -733,11 +733,11 @@ int board_interface_eth_init(struct udevice *dev, bool eth_ref_clk_sel_reg = false; /* Gigabit Ethernet 125MHz clock selection. */ - eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel"); + eth_clk_sel_reg = dev_read_bool(dev, "st,eth-clk-sel"); /* Ethernet 50Mhz RMII clock selection */ eth_ref_clk_sel_reg = - dev_read_bool(dev, "st,eth_ref_clk_sel"); + dev_read_bool(dev, "st,eth-ref-clk-sel"); syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG); -- 2.17.1

2 3

[PATCH] nvme: Remove the redundant aqa value setting
by Wesley Sheng 18 Jun '21

18 Jun '21

From: wesleywesley <wesleyshenggit(a)sina.com> AQA (Admin Queue Attributes) register is a dword size with lower word of ASQS, and higher word of ACQS. The code set the variable aqa twice, but it is redundant. Signed-off-by: wesleywesley <wesleyshenggit(a)sina.com> --- drivers/nvme/nvme.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index fc64d93ab8..a062234163 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -379,7 +379,6 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev) aqa = nvmeq->q_depth - 1; aqa |= aqa << 16; - aqa |= aqa << 16; dev->page_size = 1 << page_shift; -- 2.25.1

2 1

[PATCH] nvme: Correct the prps per page calculation method
by Wesley Sheng 18 Jun '21

18 Jun '21

From: wesleywesley <wesleyshenggit(a)sina.com> Each prp is 8 bytes, calculate the number of prps per page should just divide page size by 8 there is no need to minus 1 Signed-off-by: wesleywesley <wesleyshenggit(a)sina.com> --- drivers/nvme/nvme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index fc64d93ab8..622bb378c0 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -79,7 +79,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, u64 *prp_pool; int length = total_len; int i, nprps; - u32 prps_per_page = (page_size >> 3) - 1; + u32 prps_per_page = page_size >> 3; u32 num_pages; length -= (page_size - offset); -- 2.25.1

2 1

u-boot driver model: using sandbox_defconfig, “demo hello 5” got error “Command 'demo' failed: Error -22”
by 王洪柱 18 Jun '21

18 Jun '21

u-boot version: 2021.07-RC3 environment: Ubuntu 18.04 64-bit [Description] Build and run u-boot: make sandbox_defconfig make ./u-boot -d u-boot.dtb Type the following on the command-line: => demo hello 5 I Got the following Error: Command 'demo' failed: Error -22 If I disable CONFIG_OF_LIVE, the command will get the right answer. [Analysis] Index 5 is the device named 'hexagon' defined in arch/sandbox/dts/sandbox.dtsi: hexagon { compatible = "demo-simple"; colour = "white"; sides = <6>; }; device_probe will call of_to_plat, which finally call demo_parse_dt in drivers/demo/demo-uclass.c. int demo_parse_dt(struct udevice *dev) { struct dm_demo_pdata *pdata = dev_get_plat(dev); int dn = dev_of_offset(dev); pdata->sides = fdtdec_get_int(gd->fdt_blob, dn, "sides", 0); pdata->colour = fdt_getprop(gd->fdt_blob, dn, "colour", NULL); if (!pdata->sides || !pdata->colour) { debug("%s: Invalid device tree data\n", __func__); return -EINVAL; } return 0; } With the default configurations, I got 0 for pdata->sides, and NULL for pdata->colour. Seem that fdtdec_get_int and fdt_getprop hadn't get the correct values from device tree. With CONFIG_OF_LIVE enabled, node_ member of struct udevice will be set as a node pointer instead of an offset. dn = dev_of_offset(dev) will get an incorrect result, so "sides" and "colour" cannot be reached. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Hongzhu Wang bj_wanghz(a)126.com

1 0

[PATCH] mtd: nand: NFC drivers for RK3308, RK2928 and others
by Yifeng Zhao 18 Jun '21

18 Jun '21

This driver supports Rockchip NFC (NAND Flash Controller) found on RK3308, RK2928, RKPX30, RV1108 and other SOCs. The driver has been tested using 8-bit NAND interface on the ARM based RK3308 platform. Support Rockchip SoCs and NFC versions: - PX30 and RK3326(NFCv900). ECC: 16/40/60/70 bits/1KB. CLOCK: ahb and nfc. - RK3308 and RV1108(NFCv800). ECC: 16 bits/1KB. CLOCK: ahb and nfc. - RK3036 and RK3128(NFCv622). ECC: 16/24/40/60 bits/1KB. CLOCK: ahb and nfc. - RK3066, RK3188 and RK2928(NFCv600). ECC: 16/24/40/60 bits/1KB. CLOCK: ahb. Supported features: - Read full page data by DMA. - Support HW ECC(one step is 1KB). - Support 2 - 32K page size. - Support 8 CS(depend on SoCs) Limitations: - No support for the ecc step size is 512. - Untested on some SoCs. - No support for subpages. - No support for the builtin randomizer. - The original bad block mask is not supported. It is recommended to use the BBT(bad block table). Signed-off-by: Yifeng Zhao <yifeng.zhao(a)rock-chips.com> --- drivers/mtd/nand/raw/Kconfig | 16 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/rockchip_nfc.c | 1253 +++++++++++++++++++++++++++ 3 files changed, 1270 insertions(+) create mode 100644 drivers/mtd/nand/raw/rockchip_nfc.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index ed151ee0a5..a901ce5511 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -333,6 +333,22 @@ config CORTINA_NAND The controller supports a maximum 8k page size and supports a maximum 40-bit error correction per sector of 1024 bytes. +config ROCKCHIP_NAND + bool "Support for NAND controller on Rockchip SoCs" + depends on ARCH_ROCKCHIP + select SYS_NAND_SELF_INIT + select DM_MTD + imply CMD_NAND + help + Enables support for NAND Flash chips on Rockchip SoCs platform. + This controller is found on Rockchip SoCs. + There are four different versions of NAND FLASH Controllers, + including: + NFC v600: RK2928, RK3066, RK3188 + NFC v622: RK3036, RK3128 + NFC v800: RK3308, RV1108 + NFC v900: PX30, RK3326 + comment "Generic NAND options" config SYS_NAND_BLOCK_SIZE diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index f3f0e15a15..a5ed2c536f 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o +obj-$(CONFIG_ROCKCHIP_NAND) += rockchip_nfc.o else # minimal SPL drivers diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c new file mode 100644 index 0000000000..21776f3b14 --- /dev/null +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -0,0 +1,1253 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Rockchip NAND Flash controller driver. + * Copyright (C) 2021 Rockchip Inc. + * Author: Yifeng Zhao <yifeng.zhao(a)rock-chips.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <fdtdec.h> +#include <inttypes.h> +#include <linux/delay.h> +#include <linux/dma-direction.h> +#include <linux/dma-mapping.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <memalign.h> +#include <nand.h> + +/* + * NFC Page Data Layout: + * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data + + * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data + + * ...... + * NAND Page Data Layout: + * 1024 * n data + m Bytes oob + * Original Bad Block Mask Location: + * First byte of oob(spare). + * nand_chip->oob_poi data layout: + * 4Bytes sys data + .... + 4Bytes sys data + ECC data. + */ + +/* NAND controller register definition */ +#define NFC_READ (0) +#define NFC_WRITE (1) + +#define NFC_FMCTL (0x00) +#define FMCTL_CE_SEL_M 0xFF +#define FMCTL_CE_SEL(x) (1 << (x)) +#define FMCTL_WP BIT(8) +#define FMCTL_RDY BIT(9) + +#define NFC_FMWAIT (0x04) +#define FLCTL_RST BIT(0) +#define FLCTL_WR (1) /* 0: read, 1: write */ +#define FLCTL_XFER_ST BIT(2) +#define FLCTL_XFER_EN BIT(3) +#define FLCTL_ACORRECT BIT(10) /* Auto correct error bits. */ +#define FLCTL_XFER_READY BIT(20) +#define FLCTL_XFER_SECTOR (22) +#define FLCTL_TOG_FIX BIT(29) + +#define BCHCTL_BANK_M (7 << 5) +#define BCHCTL_BANK (5) + +#define DMA_ST BIT(0) +#define DMA_WR (1) /* 0: write, 1: read */ +#define DMA_EN BIT(2) +#define DMA_AHB_SIZE (3) /* 0: 1, 1: 2, 2: 4 */ +#define DMA_BURST_SIZE (6) /* 0: 1, 3: 4, 5: 8, 7: 16 */ +#define DMA_INC_NUM (9) /* 1 - 16 */ + +#define ECC_ERR_CNT(x, e) ((((x) >> (e).low) & (e).low_mask) |\ + (((x) >> (e).high) & (e).high_mask) << (e).low_bn) +#define INT_DMA BIT(0) +#define NFC_BANK (0x800) +#define NFC_BANK_STEP (0x100) +#define BANK_DATA (0x00) +#define BANK_ADDR (0x04) +#define BANK_CMD (0x08) +#define NFC_SRAM0 (0x1000) +#define NFC_SRAM1 (0x1400) +#define NFC_SRAM_SIZE (0x400) +#define NFC_TIMEOUT_MS (500) +#define NFC_MAX_OOB_PER_STEP 128 +#define NFC_MIN_OOB_PER_STEP 64 +#define MAX_DATA_SIZE 0xFFFC +#define MAX_ADDRESS_CYC 6 +#define NFC_ECC_MAX_MODES 4 +#define NFC_RB_DELAY_US 50 +#define NFC_MAX_PAGE_SIZE (16 * 1024) +#define NFC_MAX_OOB_SIZE (16 * 128) +#define NFC_MAX_NSELS (8) /* Some Socs only have 1 or 2 CSs. */ +#define NFC_SYS_DATA_SIZE (4) /* 4 bytes sys data in oob pre 1024 data.*/ +#define RK_DEFAULT_CLOCK_RATE (150 * 1000 * 1000) /* 150 Mhz */ +#define ACCTIMING(csrw, rwpw, rwcs) ((csrw) << 12 | (rwpw) << 5 | (rwcs)) + +enum nfc_type { + NFC_V6, + NFC_V8, + NFC_V9, +}; + +/** + * struct rk_ecc_cnt_status: represent a ecc status data. + * @err_flag_bit: error flag bit index at register. + * @low: ECC count low bit index at register. + * @low_mask: mask bit. + * @low_bn: ECC count low bit number. + * @high: ECC count high bit index at register. + * @high_mask: mask bit + */ +struct ecc_cnt_status { + u8 err_flag_bit; + u8 low; + u8 low_mask; + u8 low_bn; + u8 high; + u8 high_mask; +}; + +/** + * @type: NFC version + * @ecc_strengths: ECC strengths + * @ecc_cfgs: ECC config values + * @flctl_off: FLCTL register offset + * @bchctl_off: BCHCTL register offset + * @dma_data_buf_off: DMA_DATA_BUF register offset + * @dma_oob_buf_off: DMA_OOB_BUF register offset + * @dma_cfg_off: DMA_CFG register offset + * @dma_st_off: DMA_ST register offset + * @bch_st_off: BCG_ST register offset + * @randmz_off: RANDMZ register offset + * @int_en_off: interrupt enable register offset + * @int_clr_off: interrupt clean register offset + * @int_st_off: interrupt status register offset + * @oob0_off: oob0 register offset + * @oob1_off: oob1 register offset + * @ecc0: represent ECC0 status data + * @ecc1: represent ECC1 status data + */ +struct nfc_cfg { + enum nfc_type type; + u8 ecc_strengths[NFC_ECC_MAX_MODES]; + u32 ecc_cfgs[NFC_ECC_MAX_MODES]; + u32 flctl_off; + u32 bchctl_off; + u32 dma_cfg_off; + u32 dma_data_buf_off; + u32 dma_oob_buf_off; + u32 dma_st_off; + u32 bch_st_off; + u32 randmz_off; + u32 int_en_off; + u32 int_clr_off; + u32 int_st_off; + u32 oob0_off; + u32 oob1_off; + struct ecc_cnt_status ecc0; + struct ecc_cnt_status ecc1; +}; + +struct rk_nfc_nand_chip { + struct nand_chip chip; + + u16 boot_blks; + u16 metadata_size; + u32 boot_ecc; + u32 timing; + + u8 nsels; + u8 sels[0]; + /* Nothing after this field. */ +}; + +struct rk_nfc { + struct nand_hw_control controller; + const struct nfc_cfg *cfg; + struct udevice *dev; + + struct clk *nfc_clk; + struct clk *ahb_clk; + void __iomem *regs; + + int selected_bank; + u32 band_offset; + u32 cur_ecc; + u32 cur_timing; + + u8 *page_buf; + u32 *oob_buf; + + unsigned long assigned_cs; +}; + +static inline struct rk_nfc_nand_chip *rk_nfc_to_rknand(struct nand_chip *chip) +{ + return container_of(chip, struct rk_nfc_nand_chip, chip); +} + +static inline u8 *rk_nfc_buf_to_data_ptr(struct nand_chip *chip, const u8 *p, int i) +{ + return (u8 *)p + i * chip->ecc.size; +} + +static inline u8 *rk_nfc_buf_to_oob_ptr(struct nand_chip *chip, int i) +{ + u8 *poi; + + poi = chip->oob_poi + i * NFC_SYS_DATA_SIZE; + + return poi; +} + +static inline u8 *rk_nfc_buf_to_oob_ecc_ptr(struct nand_chip *chip, int i) +{ + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + u8 *poi; + + poi = chip->oob_poi + rknand->metadata_size + chip->ecc.bytes * i; + + return poi; +} + +static inline int rk_nfc_data_len(struct nand_chip *chip) +{ + return chip->ecc.size + chip->ecc.bytes + NFC_SYS_DATA_SIZE; +} + +static inline u8 *rk_nfc_data_ptr(struct nand_chip *chip, int i) +{ + struct rk_nfc *nfc = nand_get_controller_data(chip); + + return nfc->page_buf + i * rk_nfc_data_len(chip); +} + +static inline u8 *rk_nfc_oob_ptr(struct nand_chip *chip, int i) +{ + struct rk_nfc *nfc = nand_get_controller_data(chip); + + return nfc->page_buf + i * rk_nfc_data_len(chip) + chip->ecc.size; +} + +static int rk_nfc_hw_ecc_setup(struct nand_chip *chip, u32 strength) +{ + struct rk_nfc *nfc = nand_get_controller_data(chip); + u32 reg, i; + + for (i = 0; i < NFC_ECC_MAX_MODES; i++) { + if (strength == nfc->cfg->ecc_strengths[i]) { + reg = nfc->cfg->ecc_cfgs[i]; + break; + } + } + + if (i >= NFC_ECC_MAX_MODES) + return -EINVAL; + + writel(reg, nfc->regs + nfc->cfg->bchctl_off); + + /* Save chip ECC setting */ + nfc->cur_ecc = strength; + + return 0; +} + +static void rk_nfc_select_chip(struct mtd_info *mtd, int cs) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc *nfc = nand_get_controller_data(chip); + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + u32 val; + + if (cs < 0) { + nfc->selected_bank = -1; + /* Deselect the currently selected target. */ + val = readl(nfc->regs + NFC_FMCTL); + val &= ~FMCTL_CE_SEL_M; + writel(val, nfc->regs + NFC_FMCTL); + return; + } + + nfc->selected_bank = rknand->sels[cs]; + nfc->band_offset = NFC_BANK + nfc->selected_bank * NFC_BANK_STEP; + + val = readl(nfc->regs + NFC_FMCTL); + val &= ~FMCTL_CE_SEL_M; + val |= FMCTL_CE_SEL(nfc->selected_bank); + + writel(val, nfc->regs + NFC_FMCTL); + + /* + * Compare current chip timing with selected chip timing and + * change if needed. + */ + if (nfc->cur_timing != rknand->timing) { + writel(rknand->timing, nfc->regs + NFC_FMWAIT); + nfc->cur_timing = rknand->timing; + } + + /* + * Compare current chip ECC setting with selected chip ECC setting and + * change if needed. + */ + if (nfc->cur_ecc != ecc->strength) + rk_nfc_hw_ecc_setup(chip, ecc->strength); +} + +static inline int rk_nfc_wait_ioready(struct rk_nfc *nfc) +{ + u32 timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000; + u32 time_start; + + time_start = get_timer(0); + do { + if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY) + return 0; + } while (get_timer(time_start) < timeout); + + dev_err(nfc->dev, "wait for io ready timedout\n"); + return -ETIMEDOUT; +} + +static void rk_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc *nfc = nand_get_controller_data(chip); + void __iomem *bank_base; + int i = 0; + + bank_base = nfc->regs + nfc->band_offset + BANK_DATA; + + for (i = 0; i < len; i++) + buf[i] = readl(bank_base); +} + +static void rk_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc *nfc = nand_get_controller_data(chip); + void __iomem *bank_base; + int i = 0; + + bank_base = nfc->regs + nfc->band_offset + BANK_DATA; + + for (i = 0; i < len; i++) + writel(buf[i], bank_base); +} + +static void rk_nfc_cmd(struct mtd_info *mtd, int dat, unsigned int ctrl) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc *nfc = nand_get_controller_data(chip); + void __iomem *bank_base; + + bank_base = nfc->regs + nfc->band_offset; + + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_ALE) + bank_base += BANK_ADDR; + else if (ctrl & NAND_CLE) + bank_base += BANK_CMD; + chip->IO_ADDR_W = bank_base; + } + + if (dat != NAND_CMD_NONE) + writel(dat & 0xFF, chip->IO_ADDR_W); +} + +static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd) +{ + uint8_t ret; + + rk_nfc_read_buf(mtd, &ret, 1); + + return ret; +} + +static int rockchip_nand_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc *nfc = nand_get_controller_data(chip); + + if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY) + return 1; + + return 0; +} + +static void rk_nfc_xfer_start(struct rk_nfc *nfc, u8 rw, u8 n_KB, + dma_addr_t dma_data, dma_addr_t dma_oob) +{ + u32 dma_reg, fl_reg, bch_reg; + + dma_reg = DMA_ST | ((!rw) << DMA_WR) | DMA_EN | (2 << DMA_AHB_SIZE) | + (7 << DMA_BURST_SIZE) | (16 << DMA_INC_NUM); + + fl_reg = (rw << FLCTL_WR) | FLCTL_XFER_EN | FLCTL_ACORRECT | + (n_KB << FLCTL_XFER_SECTOR) | FLCTL_TOG_FIX; + + if (nfc->cfg->type == NFC_V6 || nfc->cfg->type == NFC_V8) { + bch_reg = readl_relaxed(nfc->regs + nfc->cfg->bchctl_off); + bch_reg = (bch_reg & (~BCHCTL_BANK_M)) | + (nfc->selected_bank << BCHCTL_BANK); + writel(bch_reg, nfc->regs + nfc->cfg->bchctl_off); + } + + writel(dma_reg, nfc->regs + nfc->cfg->dma_cfg_off); + writel((u32)dma_data, nfc->regs + nfc->cfg->dma_data_buf_off); + writel((u32)dma_oob, nfc->regs + nfc->cfg->dma_oob_buf_off); + writel(fl_reg, nfc->regs + nfc->cfg->flctl_off); + fl_reg |= FLCTL_XFER_ST; + writel(fl_reg, nfc->regs + nfc->cfg->flctl_off); +} + +static int rk_nfc_wait_for_xfer_done(struct rk_nfc *nfc) +{ + unsigned long timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000; + void __iomem *ptr = nfc->regs + nfc->cfg->flctl_off; + u32 time_start; + + time_start = get_timer(0); + + do { + if (readl(ptr) & FLCTL_XFER_READY) + return 0; + } while (get_timer(time_start) < timeout); + + dev_err(nfc->dev, "wait for io ready timedout\n"); + return -ETIMEDOUT; +} + +static int rk_nfc_write_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, + const u8 *buf, + int oob_required, + int page) +{ + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + struct rk_nfc *nfc = nand_get_controller_data(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int i, pages_per_blk; + + pages_per_blk = mtd->erasesize / mtd->writesize; + if ((page < (pages_per_blk * rknand->boot_blks)) && + rknand->boot_ecc != ecc->strength) { + /* + * There's currently no method to notify the MTD framework that + * a different ECC strength is in use for the boot blocks. + */ + return -EIO; + } + + if (!buf) + memset(nfc->page_buf, 0xff, mtd->writesize + mtd->oobsize); + + for (i = 0; i < ecc->steps; i++) { + /* Copy data to the NFC buffer. */ + if (buf) + memcpy(rk_nfc_data_ptr(chip, i), + rk_nfc_buf_to_data_ptr(chip, buf, i), + ecc->size); + /* + * The first four bytes of OOB are reserved for the + * boot ROM. In some debugging cases, such as with a + * read, erase and write back test these 4 bytes stored + * in OOB also need to be written back. + * + * The function nand_block_bad detects bad blocks like: + * + * bad = chip->oob_poi[chip->badblockpos]; + * + * chip->badblockpos == 0 for a large page NAND Flash, + * so chip->oob_poi[0] is the bad block mask (BBM). + * + * The OOB data layout on the NFC is: + * + * PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ... + * + * or + * + * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ... + * + * The code here just swaps the first 4 bytes with the last + * 4 bytes without losing any data. + * + * The chip->oob_poi data layout: + * + * BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3 + * + * The rk_nfc_ooblayout_free() function already has reserved + * these 4 bytes with: + * + * oob_region->offset = NFC_SYS_DATA_SIZE + 2; + */ + if (!i) + memcpy(rk_nfc_oob_ptr(chip, i), + rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1), + NFC_SYS_DATA_SIZE); + else + memcpy(rk_nfc_oob_ptr(chip, i), + rk_nfc_buf_to_oob_ptr(chip, i - 1), + NFC_SYS_DATA_SIZE); + /* Copy ECC data to the NFC buffer. */ + memcpy(rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE, + rk_nfc_buf_to_oob_ecc_ptr(chip, i), + ecc->bytes); + } + + nand_prog_page_begin_op(chip, page, 0, NULL, 0); + rk_nfc_write_buf(mtd, buf, mtd->writesize + mtd->oobsize); + return nand_prog_page_end_op(chip); +} + +static int rk_nfc_write_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, + const u8 *buf, + int oob_required, + int page) +{ + struct rk_nfc *nfc = nand_get_controller_data(chip); + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP : + NFC_MIN_OOB_PER_STEP; + int pages_per_blk = mtd->erasesize / mtd->writesize; + int ret = 0, i, boot_rom_mode = 0; + dma_addr_t dma_data, dma_oob; + u32 reg; + u8 *oob; + + nand_prog_page_begin_op(chip, page, 0, NULL, 0); + + if (buf) + memcpy(nfc->page_buf, buf, mtd->writesize); + else + memset(nfc->page_buf, 0xFF, mtd->writesize); + + /* + * The first blocks (4, 8 or 16 depending on the device) are used + * by the boot ROM and the first 32 bits of OOB need to link to + * the next page address in the same block. We can't directly copy + * OOB data from the MTD framework, because this page address + * conflicts for example with the bad block marker (BBM), + * so we shift all OOB data including the BBM with 4 byte positions. + * As a consequence the OOB size available to the MTD framework is + * also reduced with 4 bytes. + * + * PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ... + * + * If a NAND is not a boot medium or the page is not a boot block, + * the first 4 bytes are left untouched by writing 0xFF to them. + * + * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ... + * + * Configure the ECC algorithm supported by the boot ROM. + */ + if (page < (pages_per_blk * rknand->boot_blks)) { + boot_rom_mode = 1; + if (rknand->boot_ecc != ecc->strength) + rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc); + } + + for (i = 0; i < ecc->steps; i++) { + if (!i) { + reg = 0xFFFFFFFF; + } else { + oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; + reg = oob[0] | oob[1] << 8 | oob[2] << 16 | + oob[3] << 24; + } + + if (!i && boot_rom_mode) + reg = (page & (pages_per_blk - 1)) * 4; + + if (nfc->cfg->type == NFC_V9) + nfc->oob_buf[i] = reg; + else + nfc->oob_buf[i * (oob_step / 4)] = reg; + } + + dma_data = dma_map_single((void *)nfc->page_buf, + mtd->writesize, DMA_TO_DEVICE); + dma_oob = dma_map_single(nfc->oob_buf, + ecc->steps * oob_step, + DMA_TO_DEVICE); + + rk_nfc_xfer_start(nfc, NFC_WRITE, ecc->steps, dma_data, + dma_oob); + ret = rk_nfc_wait_for_xfer_done(nfc); + + dma_unmap_single(dma_data, mtd->writesize, + DMA_TO_DEVICE); + dma_unmap_single(dma_oob, ecc->steps * oob_step, + DMA_TO_DEVICE); + + if (boot_rom_mode && rknand->boot_ecc != ecc->strength) + rk_nfc_hw_ecc_setup(chip, ecc->strength); + + if (ret) { + dev_err(nfc->dev, "write: wait transfer done timeout.\n"); + return -ETIMEDOUT; + } + + return nand_prog_page_end_op(chip); +} + +static int rk_nfc_write_oob(struct mtd_info *mtd, + struct nand_chip *chip, int page) +{ + return rk_nfc_write_page_hwecc(mtd, chip, NULL, 1, page); +} + +static int rk_nfc_read_page_raw(struct mtd_info *mtd, + struct nand_chip *chip, + u8 *buf, + int oob_required, + int page) +{ + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + struct rk_nfc *nfc = nand_get_controller_data(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int i, pages_per_blk; + + pages_per_blk = mtd->erasesize / mtd->writesize; + if ((page < (pages_per_blk * rknand->boot_blks)) && + nfc->selected_bank == 0 && + rknand->boot_ecc != ecc->strength) { + /* + * There's currently no method to notify the MTD framework that + * a different ECC strength is in use for the boot blocks. + */ + return -EIO; + } + + nand_read_page_op(chip, page, 0, NULL, 0); + rk_nfc_read_buf(mtd, nfc->page_buf, mtd->writesize + mtd->oobsize); + for (i = 0; i < ecc->steps; i++) { + /* + * The first four bytes of OOB are reserved for the + * boot ROM. In some debugging cases, such as with a read, + * erase and write back test, these 4 bytes also must be + * saved somewhere, otherwise this information will be + * lost during a write back. + */ + if (!i) + memcpy(rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1), + rk_nfc_oob_ptr(chip, i), + NFC_SYS_DATA_SIZE); + else + memcpy(rk_nfc_buf_to_oob_ptr(chip, i - 1), + rk_nfc_oob_ptr(chip, i), + NFC_SYS_DATA_SIZE); + + /* Copy ECC data from the NFC buffer. */ + memcpy(rk_nfc_buf_to_oob_ecc_ptr(chip, i), + rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE, + ecc->bytes); + + /* Copy data from the NFC buffer. */ + if (buf) + memcpy(rk_nfc_buf_to_data_ptr(chip, buf, i), + rk_nfc_data_ptr(chip, i), + ecc->size); + } + + return 0; +} + +static int rk_nfc_read_page_hwecc(struct mtd_info *mtd, + struct nand_chip *chip, + u8 *buf, + int oob_required, + int page) +{ + struct rk_nfc *nfc = nand_get_controller_data(chip); + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP : + NFC_MIN_OOB_PER_STEP; + int pages_per_blk = mtd->erasesize / mtd->writesize; + dma_addr_t dma_data, dma_oob; + int ret = 0, i, cnt, boot_rom_mode = 0; + int max_bitflips = 0, bch_st, ecc_fail = 0; + u8 *oob; + u32 tmp; + + nand_read_page_op(chip, page, 0, NULL, 0); + + dma_data = dma_map_single(nfc->page_buf, + mtd->writesize, + DMA_FROM_DEVICE); + dma_oob = dma_map_single(nfc->oob_buf, + ecc->steps * oob_step, + DMA_FROM_DEVICE); + + /* + * The first blocks (4, 8 or 16 depending on the device) + * are used by the boot ROM. + * Configure the ECC algorithm supported by the boot ROM. + */ + if (page < (pages_per_blk * rknand->boot_blks) && + nfc->selected_bank == 0) { + boot_rom_mode = 1; + if (rknand->boot_ecc != ecc->strength) + rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc); + } + + rk_nfc_xfer_start(nfc, NFC_READ, ecc->steps, dma_data, + dma_oob); + ret = rk_nfc_wait_for_xfer_done(nfc); + + dma_unmap_single(dma_data, mtd->writesize, + DMA_FROM_DEVICE); + dma_unmap_single(dma_oob, ecc->steps * oob_step, + DMA_FROM_DEVICE); + + if (ret) { + ret = -ETIMEDOUT; + dev_err(nfc->dev, "read: wait transfer done timeout.\n"); + goto timeout_err; + } + + for (i = 1; i < ecc->steps; i++) { + oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; + if (nfc->cfg->type == NFC_V9) + tmp = nfc->oob_buf[i]; + else + tmp = nfc->oob_buf[i * (oob_step / 4)]; + *oob++ = (u8)tmp; + *oob++ = (u8)(tmp >> 8); + *oob++ = (u8)(tmp >> 16); + *oob++ = (u8)(tmp >> 24); + } + + for (i = 0; i < (ecc->steps / 2); i++) { + bch_st = readl_relaxed(nfc->regs + + nfc->cfg->bch_st_off + i * 4); + if (bch_st & BIT(nfc->cfg->ecc0.err_flag_bit) || + bch_st & BIT(nfc->cfg->ecc1.err_flag_bit)) { + mtd->ecc_stats.failed++; + ecc_fail = 1; + } else { + cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc0); + mtd->ecc_stats.corrected += cnt; + max_bitflips = max_t(u32, max_bitflips, cnt); + + cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc1); + mtd->ecc_stats.corrected += cnt; + max_bitflips = max_t(u32, max_bitflips, cnt); + } + } + + if (buf) + memcpy(buf, nfc->page_buf, mtd->writesize); + +timeout_err: + if (boot_rom_mode && rknand->boot_ecc != ecc->strength) + rk_nfc_hw_ecc_setup(chip, ecc->strength); + + if (ret) + return ret; + + if (ecc_fail) { + dev_err(nfc->dev, "read page: %x ecc error!\n", page); + return 0; + } + + return max_bitflips; +} + +static int rk_nfc_read_oob(struct mtd_info *mtd, + struct nand_chip *chip, int page) +{ + return rk_nfc_read_page_hwecc(mtd, chip, NULL, 1, page); +} + +static inline void rk_nfc_hw_init(struct rk_nfc *nfc) +{ + /* Disable flash wp. */ + writel(FMCTL_WP, nfc->regs + NFC_FMCTL); + /* Config default timing 40ns at 150 Mhz NFC clock. */ + writel(0x1081, nfc->regs + NFC_FMWAIT); + nfc->cur_timing = 0x1081; + /* Disable randomizer and DMA. */ + writel(0, nfc->regs + nfc->cfg->randmz_off); + writel(0, nfc->regs + nfc->cfg->dma_cfg_off); + writel(FLCTL_RST, nfc->regs + nfc->cfg->flctl_off); +} + +static int rk_nfc_enable_clks(struct udevice *dev, struct rk_nfc *nfc) +{ + int ret; + + if (!IS_ERR(nfc->nfc_clk)) { + ret = clk_prepare_enable(nfc->nfc_clk); + if (ret) + dev_err(dev, "failed to enable NFC clk\n"); + } + + ret = clk_prepare_enable(nfc->ahb_clk); + if (ret) { + dev_err(dev, "failed to enable ahb clk\n"); + if (!IS_ERR(nfc->nfc_clk)) + clk_disable_unprepare(nfc->nfc_clk); + } + + return 0; +} + +static void rk_nfc_disable_clks(struct rk_nfc *nfc) +{ + if (!IS_ERR(nfc->nfc_clk)) + clk_disable_unprepare(nfc->nfc_clk); + clk_disable_unprepare(nfc->ahb_clk); +} + +static int rk_nfc_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *oob_region) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + + if (section) + return -ERANGE; + + /* + * The beginning of the OOB area stores the reserved data for the NFC, + * the size of the reserved data is NFC_SYS_DATA_SIZE bytes. + */ + oob_region->length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2; + oob_region->offset = NFC_SYS_DATA_SIZE + 2; + + return 0; +} + +static int rk_nfc_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *oob_region) +{ + struct nand_chip *chip = mtd_to_nand(mtd); + struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); + + if (section) + return -ERANGE; + + oob_region->length = mtd->oobsize - rknand->metadata_size; + oob_region->offset = rknand->metadata_size; + + return 0; +} + +static const struct mtd_ooblayout_ops rk_nfc_ooblayout_ops = { + .rfree = rk_nfc_ooblayout_free, + .ecc = rk_nfc_ooblayout_ecc, +}; + +static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip) +{ + const u8 *strengths = nfc->cfg->ecc_strengths; + struct mtd_info *mtd = nand_to_mtd(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + u8 max_strength, nfc_max_strength; + int i; + + nfc_max_strength = nfc->cfg->ecc_strengths[0]; + /* If optional dt settings not present. */ + if (!ecc->size || !ecc->strength || + ecc->strength > nfc_max_strength) { + chip->ecc.size = 1024; + ecc->steps = mtd->writesize / ecc->size; + + /* + * HW ECC always requests the number of ECC bytes per 1024 byte + * blocks. The first 4 OOB bytes are reserved for sys data. + */ + max_strength = ((mtd->oobsize / ecc->steps) - 4) * 8 / + fls(8 * 1024); + if (max_strength > nfc_max_strength) + max_strength = nfc_max_strength; + + for (i = 0; i < 4; i++) { + if (max_strength >= strengths[i]) + break; + } + + if (i >= 4) { + dev_err(nfc->dev, "unsupported ECC strength\n"); + return -EOPNOTSUPP; + } + + ecc->strength = strengths[i]; + } + ecc->steps = mtd->writesize / ecc->size; + ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8); + + return 0; +} + +static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum) +{ + struct rk_nfc_nand_chip *rknand; + struct udevice *dev = nfc->dev; + struct nand_ecc_ctrl *ecc; + struct nand_chip *chip; + struct mtd_info *mtd; + u32 cs[NFC_MAX_NSELS]; + int nsels, i, ret; + u32 tmp; + + if (!ofnode_get_property(node, "reg", &nsels)) + return -ENODEV; + nsels /= sizeof(u32); + if (!nsels || nsels > NFC_MAX_NSELS) { + dev_err(dev, "invalid reg property size %d\n", nsels); + return -EINVAL; + } + + rknand = kzalloc(sizeof(*rknand) + nsels * sizeof(u8), GFP_KERNEL); + if (!rknand) + return -ENOMEM; + + rknand->nsels = nsels; + rknand->timing = nfc->cur_timing; + + ret = ofnode_read_u32_array(node, "reg", cs, nsels); + if (ret < 0) { + dev_err(dev, "Could not retrieve reg property\n"); + return -EINVAL; + } + + for (i = 0; i < nsels; i++) { + if (cs[i] >= NFC_MAX_NSELS) { + dev_err(dev, "invalid CS: %u\n", cs[i]); + return -EINVAL; + } + + if (test_and_set_bit(cs[i], &nfc->assigned_cs)) { + dev_err(dev, "CS %u already assigned\n", cs[i]); + return -EINVAL; + } + + rknand->sels[i] = cs[i]; + } + + chip = &rknand->chip; + ecc = &chip->ecc; + ecc->mode = NAND_ECC_HW_SYNDROME; + + ret = ofnode_read_u32(node, "nand-ecc-strength", &tmp); + ecc->strength = ret ? 0 : tmp; + + ret = ofnode_read_u32(node, "nand-ecc-step-size", &tmp); + ecc->size = ret ? 0 : tmp; + + mtd = nand_to_mtd(chip); + mtd->owner = THIS_MODULE; + mtd->dev->parent = dev; + + nand_set_controller_data(chip, nfc); + + chip->chip_delay = NFC_RB_DELAY_US; + chip->select_chip = rk_nfc_select_chip; + chip->cmd_ctrl = rk_nfc_cmd; + chip->read_buf = rk_nfc_read_buf; + chip->write_buf = rk_nfc_write_buf; + chip->read_byte = rockchip_nand_read_byte; + chip->dev_ready = rockchip_nand_dev_ready; + chip->controller = &nfc->controller; + + chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; + chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER; + + mtd_set_ooblayout(mtd, &rk_nfc_ooblayout_ops); + rk_nfc_hw_init(nfc); + ret = nand_scan_ident(mtd, nsels, NULL); + if (ret) + return ret; + + ret = rk_nfc_ecc_init(nfc, chip); + if (ret) { + dev_err(dev, "rk_nfc_ecc_init failed: %d\n", ret); + return ret; + } + + ret = ofnode_read_u32(node, "rockchip,boot-blks", &tmp); + rknand->boot_blks = ret ? 0 : tmp; + + ret = ofnode_read_u32(node, "rockchip,boot-ecc-strength", &tmp); + rknand->boot_ecc = ret ? ecc->strength : tmp; + + rknand->metadata_size = NFC_SYS_DATA_SIZE * ecc->steps; + + if (rknand->metadata_size < NFC_SYS_DATA_SIZE + 2) { + dev_err(dev, + "driver needs at least %d bytes of meta data\n", + NFC_SYS_DATA_SIZE + 2); + return -EIO; + } + + if (!nfc->page_buf) { + nfc->page_buf = kzalloc(NFC_MAX_PAGE_SIZE, GFP_KERNEL); + if (!nfc->page_buf) + return -ENOMEM; + } + + if (!nfc->oob_buf) { + nfc->oob_buf = kzalloc(NFC_MAX_OOB_SIZE, GFP_KERNEL); + if (!nfc->oob_buf) { + kfree(nfc->page_buf); + nfc->page_buf = NULL; + return -ENOMEM; + } + } + + ecc->read_page = rk_nfc_read_page_hwecc; + ecc->read_page_raw = rk_nfc_read_page_raw; + ecc->read_oob = rk_nfc_read_oob; + ecc->write_page = rk_nfc_write_page_hwecc; + ecc->write_page_raw = rk_nfc_write_page_raw; + ecc->write_oob = rk_nfc_write_oob; + + ret = nand_scan_tail(mtd); + if (ret) { + dev_err(dev, "nand_scan_tail failed: %d\n", ret); + return ret; + } + + return nand_register(devnum, mtd); +} + +static int rk_nfc_nand_chips_init(struct udevice *dev, struct rk_nfc *nfc) +{ + int ret, i = 0; + ofnode child; + + ofnode_for_each_subnode(child, dev_ofnode(dev)) { + ret = rk_nfc_nand_chip_init(child, nfc, i++); + if (ret) + return ret; + } + + return 0; +} + +static struct nfc_cfg nfc_v6_cfg = { + .type = NFC_V6, + .ecc_strengths = {60, 40, 24, 16}, + .ecc_cfgs = { + 0x00040011, 0x00040001, 0x00000011, 0x00000001, + }, + .flctl_off = 0x08, + .bchctl_off = 0x0C, + .dma_cfg_off = 0x10, + .dma_data_buf_off = 0x14, + .dma_oob_buf_off = 0x18, + .dma_st_off = 0x1C, + .bch_st_off = 0x20, + .randmz_off = 0x150, + .int_en_off = 0x16C, + .int_clr_off = 0x170, + .int_st_off = 0x174, + .oob0_off = 0x200, + .oob1_off = 0x230, + .ecc0 = { + .err_flag_bit = 2, + .low = 3, + .low_mask = 0x1F, + .low_bn = 5, + .high = 27, + .high_mask = 0x1, + }, + .ecc1 = { + .err_flag_bit = 15, + .low = 16, + .low_mask = 0x1F, + .low_bn = 5, + .high = 29, + .high_mask = 0x1, + }, +}; + +static struct nfc_cfg nfc_v8_cfg = { + .type = NFC_V8, + .ecc_strengths = {16, 16, 16, 16}, + .ecc_cfgs = { + 0x00000001, 0x00000001, 0x00000001, 0x00000001, + }, + .flctl_off = 0x08, + .bchctl_off = 0x0C, + .dma_cfg_off = 0x10, + .dma_data_buf_off = 0x14, + .dma_oob_buf_off = 0x18, + .dma_st_off = 0x1C, + .bch_st_off = 0x20, + .randmz_off = 0x150, + .int_en_off = 0x16C, + .int_clr_off = 0x170, + .int_st_off = 0x174, + .oob0_off = 0x200, + .oob1_off = 0x230, + .ecc0 = { + .err_flag_bit = 2, + .low = 3, + .low_mask = 0x1F, + .low_bn = 5, + .high = 27, + .high_mask = 0x1, + }, + .ecc1 = { + .err_flag_bit = 15, + .low = 16, + .low_mask = 0x1F, + .low_bn = 5, + .high = 29, + .high_mask = 0x1, + }, +}; + +static struct nfc_cfg nfc_v9_cfg = { + .type = NFC_V9, + .ecc_strengths = {70, 60, 40, 16}, + .ecc_cfgs = { + 0x00000001, 0x06000001, 0x04000001, 0x02000001, + }, + .flctl_off = 0x10, + .bchctl_off = 0x20, + .dma_cfg_off = 0x30, + .dma_data_buf_off = 0x34, + .dma_oob_buf_off = 0x38, + .dma_st_off = 0x3C, + .bch_st_off = 0x150, + .randmz_off = 0x208, + .int_en_off = 0x120, + .int_clr_off = 0x124, + .int_st_off = 0x128, + .oob0_off = 0x200, + .oob1_off = 0x204, + .ecc0 = { + .err_flag_bit = 2, + .low = 3, + .low_mask = 0x7F, + .low_bn = 7, + .high = 0, + .high_mask = 0x0, + }, + .ecc1 = { + .err_flag_bit = 18, + .low = 19, + .low_mask = 0x7F, + .low_bn = 7, + .high = 0, + .high_mask = 0x0, + }, +}; + +static const struct udevice_id rk_nfc_id_table[] = { + { + .compatible = "rockchip,px30-nfc", + .data = (unsigned long)&nfc_v9_cfg + }, + { + .compatible = "rockchip,rk2928-nfc", + .data = (unsigned long)&nfc_v6_cfg + }, + { + .compatible = "rockchip,rv1108-nfc", + .data = (unsigned long)&nfc_v8_cfg + }, + { + .compatible = "rockchip,rk3308-nfc", + .data = (unsigned long)&nfc_v8_cfg + }, + { /* sentinel */ } +}; + +static int rk_nfc_probe(struct udevice *dev) +{ + struct rk_nfc *nfc = dev_get_priv(dev); + int ret = 0; + + nfc->cfg = (void *)dev_get_driver_data(dev); + nfc->dev = dev; + + nfc->regs = (void *)dev_read_addr(dev); + if (IS_ERR(nfc->regs)) { + ret = PTR_ERR(nfc->regs); + goto release_nfc; + } + + nfc->nfc_clk = devm_clk_get(dev, "nfc"); + if (IS_ERR(nfc->nfc_clk)) { + dev_dbg(dev, "no NFC clk\n"); + /* Some earlier models, such as rk3066, have no NFC clk. */ + } + + nfc->ahb_clk = devm_clk_get(dev, "ahb"); + if (IS_ERR(nfc->ahb_clk)) { + dev_err(dev, "no ahb clk\n"); + ret = PTR_ERR(nfc->ahb_clk); + goto release_nfc; + } + + ret = rk_nfc_enable_clks(dev, nfc); + if (ret) + goto release_nfc; + + spin_lock_init(&nfc->controller.lock); + init_waitqueue_head(&nfc->controller.wq); + + rk_nfc_hw_init(nfc); + + ret = rk_nfc_nand_chips_init(dev, nfc); + if (ret) { + dev_err(dev, "failed to init NAND chips\n"); + goto clk_disable; + } + return 0; + +clk_disable: + rk_nfc_disable_clks(nfc); +release_nfc: + return ret; +} + +U_BOOT_DRIVER(rockchip_nfc) = { + .name = "rockchip_nfc", + .id = UCLASS_MTD, + .of_match = rk_nfc_id_table, + .probe = rk_nfc_probe, + .priv_auto = sizeof(struct rk_nfc), +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, + DM_DRIVER_GET(rockchip_nfc), + &dev); + if (ret && ret != -ENODEV) + log_err("Failed to initialize ROCKCHIP NAND controller. (error %d)\n", + ret); +} + +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) +{ + struct mtd_info *mtd; + size_t length = size; + + mtd = get_nand_dev_by_index(0); + return nand_read_skip_bad(mtd, offs, &length, NULL, size, (u_char *)dst); +} + +void nand_deselect(void) {} -- 2.17.1

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[PATCHv4 1/3] pci: pcie_dw_rockchip: Fixed the below compilation error
by Anand Moon 18 Jun '21

18 Jun '21

Use the generic error number instead of specific error number. Changes fix the below error. drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read': drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 70 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_write': drivers/pci/pcie_dw_rockchip.c:90:10: error: 'PCIBIOS_UNSUPPORTED' undeclared (first use in this function) 90 | return PCIBIOS_UNSUPPORTED; | ^~~~~~~~~~~~~~~~~~~ Cc: Patrick Wildt <patrick(a)blueri.se> Cc: Neil Armstrong <narmstrong(a)baylibre.com> Cc: Kever Yang <kever.yang(a)rock-chips.com> Reviewed-by: Neil Armstrong <narmstrong(a)baylibre.com> Reviewed-by: Patrick Wildt <patrick(a)blueri.se> Signed-off-by: Anand Moon <linux.amoon(a)gmail.com> --- drivers/pci/pcie_dw_rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index bc22af4230..3ac2434b69 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -67,7 +67,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 *val) { if ((uintptr_t)addr & (size - 1)) { *val = 0; - return PCIBIOS_UNSUPPORTED; + return -EOPNOTSUPP; } if (size == 4) { @@ -87,7 +87,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 *val) static int rk_pcie_write(void __iomem *addr, int size, u32 val) { if ((uintptr_t)addr & (size - 1)) - return PCIBIOS_UNSUPPORTED; + return -EOPNOTSUPP; if (size == 4) writel(val, addr); -- 2.31.1

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[PATCH v1 0/5] Add RK3568 SoC support
by Joseph Chen 18 Jun '21

18 Jun '21

This series adds support for the rk3588 soc and its evaluation board. SPL will be supported after this series of patches. Joseph Chen (5): arm: dts: Sync rockchip-pinconf.dtsi from kernel arm: dts: rockchip: Add dts for rk3568 evb rockchip: rk3568: Add sdram driver rockchip: Add rk3568 architecture core board: rockchip: Add rk3568 evb support arch/arm/dts/Makefile | 3 + arch/arm/dts/rk3568-evb-u-boot.dtsi | 23 + arch/arm/dts/rk3568-evb.dts | 79 + arch/arm/dts/rk3568-pinctrl.dtsi | 3111 +++++++++++++++++ arch/arm/dts/rk3568-u-boot.dtsi | 37 + arch/arm/dts/rk3568.dtsi | 779 +++++ arch/arm/dts/rockchip-pinconf.dtsi | 344 ++ arch/arm/include/asm/arch-rk3568/boot0.h | 11 + arch/arm/include/asm/arch-rk3568/gpio.h | 11 + .../include/asm/arch-rockchip/grf_rk3568.h | 369 ++ arch/arm/mach-rockchip/Kconfig | 18 + arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3568/Kconfig | 20 + arch/arm/mach-rockchip/rk3568/Makefile | 9 + arch/arm/mach-rockchip/rk3568/clk_rk3568.c | 53 + arch/arm/mach-rockchip/rk3568/rk3568.c | 85 + arch/arm/mach-rockchip/rk3568/syscon_rk3568.c | 24 + board/rockchip/evb_rk3568/Kconfig | 15 + board/rockchip/evb_rk3568/MAINTAINERS | 6 + board/rockchip/evb_rk3568/Makefile | 7 + board/rockchip/evb_rk3568/evb_rk3568.c | 4 + configs/evb-rk3568_defconfig | 35 + drivers/ram/rockchip/Makefile | 1 + drivers/ram/rockchip/sdram_rk3568.c | 56 + include/configs/evb_rk3568.h | 17 + include/configs/rk3568_common.h | 43 + 26 files changed, 5161 insertions(+) create mode 100644 arch/arm/dts/rk3568-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-evb.dts create mode 100644 arch/arm/dts/rk3568-pinctrl.dtsi create mode 100644 arch/arm/dts/rk3568-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568.dtsi create mode 100644 arch/arm/dts/rockchip-pinconf.dtsi create mode 100644 arch/arm/include/asm/arch-rk3568/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3568/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3568.h create mode 100644 arch/arm/mach-rockchip/rk3568/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3568/Makefile create mode 100644 arch/arm/mach-rockchip/rk3568/clk_rk3568.c create mode 100644 arch/arm/mach-rockchip/rk3568/rk3568.c create mode 100644 arch/arm/mach-rockchip/rk3568/syscon_rk3568.c create mode 100644 board/rockchip/evb_rk3568/Kconfig create mode 100644 board/rockchip/evb_rk3568/MAINTAINERS create mode 100644 board/rockchip/evb_rk3568/Makefile create mode 100644 board/rockchip/evb_rk3568/evb_rk3568.c create mode 100644 configs/evb-rk3568_defconfig create mode 100644 drivers/ram/rockchip/sdram_rk3568.c create mode 100644 include/configs/evb_rk3568.h create mode 100644 include/configs/rk3568_common.h -- 2.17.1

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