June 2021 - U-Boot

Re: [PATCH] nvme: don't create block device for inactive namespace
by Bin Meng 21 Jun '21

21 Jun '21

+ML On Fri, Jun 18, 2021 at 1:47 PM Bin Meng <bmeng.cn(a)gmail.com> wrote: > > Hi Heinrich, > > On Thu, Jun 17, 2021 at 7:04 PM Heinrich Schuchardt <xypron.glpk(a)gmx.de> wrote: > > > > QEMU returns the highest supported namespace number NN as 255. This does > > not imply that there are 255 active namespaces. > > > > If a namespace is not active, the namespace identify command returns a zero > > filled data structure. We can use field NSZE (namespace size) to decide if > > a block device should be created. > > Thanks for the fix. Apparently QEMU has changed its behavior of namespaces. > > > > > Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> > > --- > > drivers/nvme/nvme-uclass.c | 30 +++++++++++++++++++++++++++++- > > 1 file changed, 29 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/nvme/nvme-uclass.c b/drivers/nvme/nvme-uclass.c > > index 277e31e1f3..f7861f5287 100644 > > --- a/drivers/nvme/nvme-uclass.c > > +++ b/drivers/nvme/nvme-uclass.c > > @@ -4,22 +4,50 @@ > > * Copyright (C) 2017 Bin Meng <bmeng.cn(a)gmail.com> > > */ > > > > +#define LOG_CATEGORY UCLASS_NVME > > + > > #include <common.h> > > #include <blk.h> > > #include <errno.h> > > #include <dm.h> > > #include <dm/device.h> > > +#include <log.h> > > +#include <memalign.h> > > +#include <nvme.h> > > #include "nvme.h" > > > > +/** > > + * nvme_probe_namespace() - check if namespace is active > > + * > > + * @dev: NVMe controller device > > + * @ns_id: namespace ID > > + * Return: 0 if namespace exists, -ve on error > > + */ > > +static int nvme_probe_namespace(struct nvme_dev *dev, unsigned int ns_id) > > +{ > > + ALLOC_CACHE_ALIGN_BUFFER(char, buf_ns, sizeof(struct nvme_id_ns)); > > + struct nvme_id_ns *id = (struct nvme_id_ns *)buf_ns; > > + > > + if (nvme_identify(dev, ns_id, 0, (dma_addr_t)(long)id)) > > + return -EIO; > > + log_debug("ns_id %u, nsze %llu\n", ns_id, id->nsze); > > + if (!id->nsze) > > + return -ENOENT; > > + return 0; > > +} > > + > > static int nvme_uclass_post_probe(struct udevice *udev) > > { > > char name[20]; > > struct udevice *ns_udev; > > - int i, ret; > > + unsigned int i; > > + int ret; > > struct nvme_dev *ndev = dev_get_priv(udev); > > > > /* Create a blk device for each namespace */ > > for (i = 0; i < ndev->nn; i++) { > > I suggest we assign correct number of namespaces in > nvme_get_info_from_identify() instead. > > > + if (nvme_probe_namespace(ndev, i + 1)) > > + continue; > > /* > > * Encode the namespace id to the device name so that > > * we can extract it when doing the probe. > > Regards, > Bin

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RE: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages
by raghu.ncstate＠icloud.com 21 Jun '21

21 Jun '21

My take: Don’t force device tree on platforms. Lets not make decisions about whether SDRAM is sufficient to expose device tree, that is assuming size may be the only problem with device tree. Some platforms don’t want to use device tree just like some platforms don’t want to use UUID’s(which b.t.w does not necessarily mean private use as was explained during the TF-A forums). I support ARM’s proposal that partitions the problem based on market segments and allows different platforms to choose what is right for them, that includes the ability to use UUID if a platform so chooses AND across boundaries. I wouldn’t vote for the proposal below about using bloblist for simple things and device tree for other complex things based on SRAM/SDRAM etc. that complicates things further. What if you need to pass information from the bloblist to later boot stages? Do we take data from bloblist and patch it into a device tree? I also think it is incorrect to partition platforms into what u-boot/linux boot/embdedded systems do and what “UEFI/private code” does. UEFI is a huge part of the ARM eco-system and is being used fairly extensively and supported across different markets and is not private code. Thanks -Raghu From: TF-A <tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of François Ozog via TF-A Sent: Thursday, June 17, 2021 12:57 PM To: Simon Glass <sjg(a)chromium.org> Cc: Ed Stuber <edstuber(a)amperecomputing.com>; Boot Architecture Mailman List <boot-architecture(a)lists.linaro.org>; Harb Abdulhamid OS <abdulhamid(a)os.amperecomputing.com>; U-Boot Mailing List <u-boot(a)lists.denx.de>; Arjun Khare <akhare(a)amperecomputing.com>; tf-a(a)lists.trustedfirmware.org; Paul Isaac's <paul.isaacs(a)linaro.org>; Ron Minnich <rminnich(a)google.com>; Moe Ammar <moe(a)amperecomputing.com> Subject: Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages Le jeu. 17 juin 2021 à 21:38, Simon Glass <sjg(a)chromium.org <mailto:sjg@chromium.org> > a écrit : Hi, On Fri, 11 Jun 2021 at 05:52, François Ozog <francois.ozog(a)linaro.org <mailto:francois.ozog@linaro.org> > wrote: On Thu, 10 Jun 2021 at 23:57, Manish Pandey2 <Manish.Pandey2(a)arm.com <mailto:Manish.Pandey2@arm.com> > wrote: Hi Everyone, I have tried to conclude the discussions we had in two of the TF-A tech forum sessions and on mailing list. The problem we are trying to solve is already solved in different projects in different ways, the purpose of these discussions was to come up with a standard way which can be adopted widely. Considering that many Firmware projects are not DT aware its better to avoid its usage and use simple C structures for wider acceptance. Based on the discussions following design came up as most acceptable solution * Use list of pre-defined C data structures(blobs) to pass information, let's call it bloblist * Only bootloaders stages will participate * Blobs will be identified by either tags or UUIDs They always have a tag, but one of the tags can be BLOBLISTT_UUID indicating it is for private use. But we should not allow this for passing across a boundary, so that no software needs to deal with UUID unless it is UEFI / private code. So, basically what Francios says below. * * Pass pointer to the bloblist head through x0 * Existing usage of x0 will be translated into a blob After all discussions, I now support Simon proposal to use existing bloblist: it does the job, is already upstream in key projects (core boot, U-Boot), is supported on x86 and Arm. I would think of a few additions on the bloblist_rec: struct <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/blob…> bloblist_rec { <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/u32> u32 <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/tag> tag; <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/u32> u32 <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/hdr_…> hdr_size; <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/u32> u32 size; <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/u32> u32 <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/spare> spare; }; enum <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/blob…> bloblist_tag_t { <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_NONE = 0, /* Vendor-specific tags are permitted here */ <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_EC_HOSTEVENT, /* Chromium OS EC host-event mask */ We can give these each a value (=1, =2) so it is clear. <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_SPL_HANDOFF, /* Hand-off info from SPL */ <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_VBOOT_CTX, /* Chromium OS verified boot context */ <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_VBOOT_HANDOFF, /* Chromium OS internal handoff info */ /* * Advanced Configuration and Power Interface Global Non-Volatile * Sleeping table. This forms part of the ACPI tables passed to Linux. */ <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_ACPI_GNVS, <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_INTEL_VBT, /* Intel Video-BIOS table */ <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_TPM2_TCG_LOG, /* TPM v2 log space */ <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_TCPA_LOG, /* TPM log space */ <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_ACPI_TABLES, /* ACPI tables for x86 */ <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_SMBIOS_TABLES, /* SMBIOS tables for x86 */ How about: BLOBLISTT_LOCAL = 0xf0000000u /* values in this space are for local use during development */ <https://elixir.bootlin.com/u-boot/latest/source/include/latest/C/ident/BLOB…> BLOBLISTT_COUNT }; I would add a BLOBLISTT_UUID for all proprietary things that people want to add. Using private space in a 64 bit field does not make the thing open. So by using this tag, we know exactly the nature of the blob. Negotiating for adding a new tag is a good open governance process. +1 We may have to deal with super small SRAM (256KB) and thus we can assume the bloblist will be a single region of blobs. So I would add a BLOBLISTT_CONTINUATION which would be a pointer from the SRAM bloblist to a DRAM backed bloblist. It is possible to relocate a bloblist, so I wonder if another approach would be to allow the bloblist to grow as it progresses through the boot (e.g. once SDRAM is available). That is what U-Boot does and it makes the code simpler (although only very slightly). However, it does introduce copying overhead...? looks good: just making the problem. Other tags to consider: PSCI interface details, DRAM information, SCMI stuff, Secure SRAM and DRAM information... * Going forward we would provide core changes to demonstrate this design on various TF-A boundries, BL1<->BL2, BL2<->BL31 and BL31<->BL33(only BL31 part) Please share your thoughts if you disagree to the proposed solution. Also, refer to attached slide deck which was presented during last tech forum session on 3rd june, it also captures the points discussed during meeting and next steps for implementing it in TF-A. Re devicetree, how about we use bloblist for simple things, but use a devicetree (perhaps in the bloblist) once SDRAM is available. Blobs that were created pre-SDRAM can continue to be passed on, but anything created after SDRAM is available should use devicetree? This would ensure that complex structures use devicetree rather than C structs, which are of course harder to extend / describe. +1 Regards, Simon Thanks Manish Pandey _____ From: Joanna Farley <Joanna.Farley(a)arm.com <mailto:Joanna.Farley@arm.com> > Sent: 02 June 2021 16:26 To: Madhukar Pappireddy <Madhukar.Pappireddy(a)arm.com <mailto:Madhukar.Pappireddy@arm.com> >; Okash Khawaja <okash.khawaja(a)gmail.com <mailto:okash.khawaja@gmail.com> >; Simon Glass <sjg(a)chromium.org <mailto:sjg@chromium.org> > Cc: Harb Abdulhamid OS <abdulhamid(a)os.amperecomputing.com <mailto:abdulhamid@os.amperecomputing.com> >; Boot Architecture Mailman List <boot-architecture(a)lists.linaro.org <mailto:boot-architecture@lists.linaro.org> >; Ed Stuber <edstuber(a)amperecomputing.com <mailto:edstuber@amperecomputing.com> >; Arjun Khare <akhare(a)amperecomputing.com <mailto:akhare@amperecomputing.com> >; U-Boot Mailing List <u-boot(a)lists.denx.de <mailto:u-boot@lists.denx.de> >; Paul Isaac's <paul.isaacs(a)linaro.org <mailto:paul.isaacs@linaro.org> >; Ron Minnich <rminnich(a)google.com <mailto:rminnich@google.com> >; Moe Ammar <moe(a)amperecomputing.com <mailto:moe@amperecomputing.com> >; tf-a(a)lists.trustedfirmware.org <mailto:tf-a@lists.trustedfirmware.org> <tf-a(a)lists.trustedfirmware.org <mailto:tf-a@lists.trustedfirmware.org> >; Manish Pandey2 <Manish.Pandey2(a)arm.com <mailto:Manish.Pandey2@arm.com> > Subject: Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages + TF-A list that got dropped (again)! Joanna From: Joanna Farley < <mailto:Joanna.Farley@arm.com> Joanna.Farley(a)arm.com> Date: Wednesday, 2 June 2021 at 15:29 To: Madhukar Pappireddy < <mailto:Madhukar.Pappireddy@arm.com> Madhukar.Pappireddy(a)arm.com>, Okash Khawaja < <mailto:okash.khawaja@gmail.com> okash.khawaja(a)gmail.com>, Simon Glass < <mailto:sjg@chromium.org> sjg(a)chromium.org> Cc: Harb Abdulhamid OS < <mailto:abdulhamid@os.amperecomputing.com> abdulhamid(a)os.amperecomputing.com>, Boot Architecture Mailman List < <mailto:boot-architecture@lists.linaro.org> boot-architecture(a)lists.linaro.org>, Ed Stuber < <mailto:edstuber@amperecomputing.com> edstuber(a)amperecomputing.com>, Arjun Khare < <mailto:akhare@amperecomputing.com> akhare(a)amperecomputing.com>, U-Boot Mailing List < <mailto:u-boot@lists.denx.de> u-boot(a)lists.denx.de>, Paul Isaac's < <mailto:paul.isaacs@linaro.org> paul.isaacs(a)linaro.org>, Ron Minnich < <mailto:rminnich@google.com> rminnich(a)google.com>, Moe Ammar < <mailto:moe@amperecomputing.com> moe(a)amperecomputing.com> Subject: Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages Hi Everyone, The Manish Pandy and Madhukar Pappireddy of the TF-A team are planning to host another TF-A Tech Forum this Thursday to continue the live discussion. Here is their agenda: On tech forum this week, we would like to continue discussions on HOB list design. The topics which we would like to cover is 1. Evaluate different proposals of passing information through boot phases. 2. If we don't get an agreement on one solution fit for all then we would try to get consensus for Infra segment platform(to solve original problem mentioned by Harb) 3. Try to get an agreement on size of tags and how "hybrid and tag only" HOB list can co-exist together? Details of the call are: ====================== TF-A Tech Forum When Every 2 weeks from 16:00 to 17:00 on Thursday United Kingdom Time Calendar <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org Who • Bill Fletcher- creator • <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: <https://www.trustedfirmware.org/meetings/tf-a-technical-forum/> https://www.trustedfirmware.org/meetings/tf-a-technical-forum/ Trusted Firmware is inviting you to a scheduled Zoom meeting. Join Zoom Meeting <https://zoom.us/j/9159704974> https://zoom.us/j/9159704974 Meeting ID: <tel:(915)%20970-4974> 915 970 4974 One tap mobile <tel:(646)%20558-8656> +16465588656,, <tel:(915)%20970-4974> 9159704974# US (New York) <tel:(669)%20900-9128> +16699009128,, <tel:(915)%20970-4974> 9159704974# US (San Jose) Dial by your location <tel:(646)%20558-8656> +1 646 558 8656 US (New York) <tel:(669)%20900-9128> +1 669 900 9128 US (San Jose) <tel:(877)%20853-5247> 877 853 5247 US Toll-free <tel:(888)%20788-0099> 888 788 0099 US Toll-free Meeting ID: <tel:(915)%20970-4974> 915 970 4974 Find your local number: <https://zoom.us/u/ad27hc6t7h> https://zoom.us/u/ad27hc6t7h ================ Joanna On 19/05/2021, 03:50, "Madhukar Pappireddy" < <mailto:Madhukar.Pappireddy@arm.com> Madhukar.Pappireddy(a)arm.com> wrote: Attached slides presented by Manish in the TF-A tech forum. -----Original Message----- From: TF-A < <mailto:tf-a-bounces@lists.trustedfirmware.org> tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Madhukar Pappireddy via TF-A Sent: Tuesday, May 18, 2021 8:59 PM To: Joanna Farley < <mailto:Joanna.Farley@arm.com> Joanna.Farley(a)arm.com>; Okash Khawaja < <mailto:okash.khawaja@gmail.com> okash.khawaja(a)gmail.com>; Simon Glass < <mailto:sjg@chromium.org> sjg(a)chromium.org> Cc: Harb Abdulhamid OS < <mailto:abdulhamid@os.amperecomputing.com> abdulhamid(a)os.amperecomputing.com>; Boot Architecture Mailman List < <mailto:boot-architecture@lists.linaro.org> boot-architecture(a)lists.linaro.org>; Ed Stuber < <mailto:edstuber@amperecomputing.com> edstuber(a)amperecomputing.com>; Arjun Khare < <mailto:akhare@amperecomputing.com> akhare(a)amperecomputing.com>; U-Boot Mailing List < <mailto:u-boot@lists.denx.de> u-boot(a)lists.denx.de>; <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org; Paul Isaac's < <mailto:paul.isaacs@linaro.org> paul.isaacs(a)linaro.org>; Ron Minnich < <mailto:rminnich@google.com> rminnich(a)google.com>; Moe Ammar < <mailto:moe@amperecomputing.com> moe(a)amperecomputing.com> Subject: Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages Hi, I tried to summarize the discussions in the previous TF-A tech forum regarding the proposal to adopt Hand-off Blocks (HOBs) for passing information along the boot chain. I am certain I could not capture all suggestions/concerns brought up during the call. I apologize if I missed and/or misinterpreted any comments and would appreciate it if everyone could share their thoughts in response to this email thread. The idea is to share information to other boot phases: > Dynamic information: Created during runtime. Shared in the form of a chain of blobs(built as a linked list of C structure objects i.e., HOB list). > Static information: Known at compile time. Historically, shared through the use of Device Tree/ACPI tables Both the above requirements are common in many ecosystems and need to co-exist. There are broadly 3 problems to solve: 1. Format of HOB structures: It looks like the consensus is that we could use existing mechanisms for this (BL_AUX_PARAM in TF-A or bloblist in u-boot). 2. Identification of HOB list entries: There is a debate about whether tags would suffice or if the HOB list producer and consumer would depend on UUID/GUIDs for identifying a specific HOB structure. Another suggestion was to use a hybrid approach. Reserve a single tag ID for identifying/constructing a HOB structure that further leverages UUID based identifier. This way, the generic HOB list doesn't need to support UUIDs and can work with tags. 3. The design contract for the static interface between two boot phases: The problem at hand is whether to pass a pointer to a HOB list or a device tree blob through the general-purpose registers for configuration hand-off between two boot phases. Some proposals that came up: > Proposal 1: Always pass a pointer to the device tree blob through the GP register and capture the pointer to the HOB list as a property of a node that is uniquely identifiable by the downstream boot phase. This needs to define a device tree binding such that producer and consumer agree on the information passed. > Proposal 2: Pass a pointer to a generic container through the GP register that can be interpreted appropriately by both boot loaders(i.e., producer and consumer of the boot info). This container can either be a dtb or a HOB list which can be simply inferred by checking for a magic header that indicates if the buffer appears to be a flattened device tree. > One another concern that was brought up offline is to make sure we don't break current design contracts between various boot loader phases in TF-A. Many of the general-purpose registers have a designated purpose such as to share configurations between BL images( such as firmware config dtb, SoC config dtb, Non trusted firmware config dtb, memory layout, entry point info, etc.). If I am not mistaken, a single design may not fit the needs of every segment(client, Infra, embedded) and the forum is open to solutions tailored for individual segments. Joanna will be sending a follow up email with more information about future TF-A tech forums that serves as a platform for further discussions. Thanks, Madhukar -----Original Message----- From: TF-A < <mailto:tf-a-bounces@lists.trustedfirmware.org> tf-a-bounces(a)lists.trustedfirmware.org> On Behalf Of Joanna Farley via TF-A Sent: Sunday, May 16, 2021 5:19 AM To: Okash Khawaja < <mailto:okash.khawaja@gmail.com> okash.khawaja(a)gmail.com>; Simon Glass < <mailto:sjg@chromium.org> sjg(a)chromium.org> Cc: Harb Abdulhamid OS < <mailto:abdulhamid@os.amperecomputing.com> abdulhamid(a)os.amperecomputing.com>; Boot Architecture Mailman List < <mailto:boot-architecture@lists.linaro.org> boot-architecture(a)lists.linaro.org>; <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org; Ed Stuber < <mailto:edstuber@amperecomputing.com> edstuber(a)amperecomputing.com>; Arjun Khare < <mailto:akhare@amperecomputing.com> akhare(a)amperecomputing.com>; U-Boot Mailing List < <mailto:u-boot@lists.denx.de> u-boot(a)lists.denx.de>; Paul Isaac's < <mailto:paul.isaacs@linaro.org> paul.isaacs(a)linaro.org>; Ron Minnich < <mailto:rminnich@google.com> rminnich(a)google.com>; Moe Ammar < <mailto:moe@amperecomputing.com> moe(a)amperecomputing.com> Subject: Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages Apologies I failed with the recording. Manish/Madhu will reply early next week with the slides and some notes to help with a follow up session which we hope to hold this Thursday. Invite and agenda will also be sent out early next week. Thanks Joanna On 14/05/2021, 13:30, "TF-A on behalf of Okash Khawaja via TF-A" < <mailto:tf-a-bounces@lists.trustedfirmware.org> tf-a-bounces(a)lists.trustedfirmware.org on behalf of <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org> wrote: Hi, Do we have slides and video from last week's discussion? Thanks, Okash On Wed, May 5, 2021 at 11:52 PM Simon Glass via TF-A < <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org> wrote: > > Hi Harb, > > Thanks for the idea. I am still not completely sure what benefit UUID provides to an open project. I'd like to propose something different, more in the spirit of open collaboration. I also worry that the word 'standard' seems to be a synonym for UUIDs, UEFI, etc., i.e. enabling/preferring closed-source firmware and the continued decline of open-source projects. It really should not be. > > So I suggest: Use simple integer IDs and reserve some area for 'private' use. If you want to collaborate across projects outside your company, you either need to allocate a 'public' ID or agree privately between the parties which private ID to use. > > This means that the default and easiest option is for collaboration and a public ID, with private ones (whose purpose may be secret) reserved just for private use. > > Regards, > Simon > > On Wed, 5 May 2021 at 11:42, Harb Abdulhamid OS < <mailto:abdulhamid@os.amperecomputing.com> abdulhamid(a)os.amperecomputing.com> wrote: >> >> Hey Folks, >> >> We wanted to put out a middle-ground proposal to help guide the discussion on the call tomorrow. >> >> >> >> A proposal that we have been discussing offline involves reserving a single tag ID for the purpose of construction UEFI PI HOB List structure, and that tag would be used to identify a HOB-specific structure that does leverage UUID based identifier. This will eliminate the burden of having to support UUID as the tag, and this enables projects that require UUID based identifiers for the broad range of HOB structures that need to be produced during the booting of the platform. Once we have a tag for a HOB list, this will enable various HOB producers that can add/extend the HOB list in TF-A code (or even pre-TF-A code), with a HOB consumer for that UUID/GUID on the other side (i.e. whatever the BL33 image is booting on that platform). >> >> >> >> Essentially, the idea is if someone would like to support HOB structures in a standard way using TF-A, they would wrap it up in a BL_AUX_PARAM/BLOB structure (whatever the group decides) and the way we identify the structure as a HOB list is with this new reserved tag. >> >> >> >> Hopefully that makes sense and less contentious. Look forward to discuss this further on the call. >> >> >> >> Thanks, >> >> --Harb >> >> >> >> From: Manish Pandey2 < <mailto:Manish.Pandey2@arm.com> Manish.Pandey2(a)arm.com> >> Sent: Friday, April 30, 2021 8:14 AM >> To: François Ozog < <mailto:francois.ozog@linaro.org> francois.ozog(a)linaro.org> >> Cc: Simon Glass < <mailto:sjg@chromium.org> sjg(a)chromium.org>; Julius Werner < <mailto:jwerner@chromium.org> jwerner(a)chromium.org>; Harb Abdulhamid OS < <mailto:abdulhamid@os.amperecomputing.com> abdulhamid(a)os.amperecomputing.com>; Boot Architecture Mailman List < <mailto:boot-architecture@lists.linaro.org> boot-architecture(a)lists.linaro.org>; <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org; U-Boot Mailing List < <mailto:u-boot@lists.denx.de> u-boot(a)lists.denx.de>; Paul Isaac's < <mailto:paul.isaacs@linaro.org> paul.isaacs(a)linaro.org>; Ron Minnich < <mailto:rminnich@google.com> rminnich(a)google.com> >> Subject: Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages >> >> >> >> Hi All, >> >> >> >> Please find invite for next TF-A Tech Forum session to continue our discussions on HOB implementation, feel free to forward it to others. >> >> >> >> The next TF-A Tech Forum is scheduled for Thu 6th May 2021 16:00 – 17:00 (BST). >> >> >> >> Agenda: >> >> Discussion Session: Static and Dynamic Information Handling in TF-A >> >> Lead by Manish Pandey and Madhukar Pappireddy >> >> · There is ongoing mailing lists discussion[1] related with adopting a mechanism to pass information through boot stages. >> >> The requirement is two-fold: >> >> 1. Passing static information(config files) >> >> 2. Passing dynamic information (Hob list) >> >> In the upcoming TF-A tech forum, we can start with a discussion on dynamic information passing and if time permits, we can cover static information passing. The purpose of the call is to have an open discussion and continue the discussion from the trusted-substrate call[2] done earlier. We would like to understand the various requirements and possible ways to implement it in TF-A in a generalized way so that it can work with other Firmware projects. >> >> >> >> The two specific item which we would like to discuss are: >> >> 1. HOB format: TF-A/u-boot both has an existing bloblist implementation, which uses tag values. Question, can this be enhanced to use hybrid values(Tag and UUID) both? >> >> 2. Standardization on Physical register use to pass base of HoB data structure. >> >> References: >> >> [1] <https://lists.trustedfirmware.org/pipermail/tf-a/2021-April/001069.html> https://lists.trustedfirmware.org/pipermail/tf-a/2021-April/001069.html >> >> [2] <https://linaro-org.zoom.us/rec/share/zjfHeMIumkJhirLCVQYTHR6ftaqyWvF_0klgQn…> https://linaro-org.zoom.us/rec/share/zjfHeMIumkJhirLCVQYTHR6ftaqyWvF_0klgQn… Passcode: IPn+5q% >> >> >> >> Thanks >> >> >> >> Joanna >> >> >> >> You have been invited to the following event. >> >> TF-A Tech Forum >> >> When >> >> Every 2 weeks from 16:00 to 17:00 on Thursday United Kingdom Time >> >> Calendar >> >> <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org >> >> Who >> >> • >> >> Bill Fletcher- creator >> >> • >> >> <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org >> >> more details » >> >> >> >> We run an open technical forum call for anyone to participate and it is not restricted to Trusted Firmware project members. It will operate under the guidance of the TF TSC. >> >> >> >> Feel free to forward this invite to colleagues. Invites are via the TF-A mailing list and also published on the Trusted Firmware website. Details are here: <https://www.trustedfirmware.org/meetings/tf-a-technical-forum/> https://www.trustedfirmware.org/meetings/tf-a-technical-forum/ >> >> >> >> Trusted Firmware is inviting you to a scheduled Zoom meeting. >> >> >> >> Join Zoom Meeting >> >> <https://zoom.us/j/9159704974> https://zoom.us/j/9159704974 >> >> >> >> Meeting ID: <tel:(915)%20970-4974> 915 970 4974 >> >> >> >> One tap mobile >> >> <tel:(646)%20558-8656> +16465588656,,9159704974# US (New York) >> >> <tel:(669)%20900-9128> +16699009128,,9159704974# US (San Jose) >> >> >> >> Dial by your location >> >> <tel:(646)%20558-8656> +1 646 558 8656 US (New York) >> >> <tel:(669)%20900-9128> +1 669 900 9128 US (San Jose) >> >> <tel:(877)%20853-5247> 877 853 5247 US Toll-free >> >> <tel:(888)%20788-0099> 888 788 0099 US Toll-free >> >> Meeting ID: <tel:(915)%20970-4974> 915 970 4974 >> >> Find your local number: <https://zoom.us/u/ad27hc6t7h> https://zoom.us/u/ad27hc6t7h >> >> >> >> ________________________________ >> >> From: François Ozog < <mailto:francois.ozog@linaro.org> francois.ozog(a)linaro.org> >> Sent: 08 April 2021 16:50 >> To: Manish Pandey2 < <mailto:Manish.Pandey2@arm.com> Manish.Pandey2(a)arm.com> >> Cc: Simon Glass < <mailto:sjg@chromium.org> sjg(a)chromium.org>; Julius Werner < <mailto:jwerner@chromium.org> jwerner(a)chromium.org>; Harb Abdulhamid OS < <mailto:abdulhamid@os.amperecomputing.com> abdulhamid(a)os.amperecomputing.com>; Boot Architecture Mailman List < <mailto:boot-architecture@lists.linaro.org> boot-architecture(a)lists.linaro.org>; <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org < <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org>; U-Boot Mailing List < <mailto:u-boot@lists.denx.de> u-boot(a)lists.denx.de>; Paul Isaac's < <mailto:paul.isaacs@linaro.org> paul.isaacs(a)linaro.org>; Ron Minnich < <mailto:rminnich@google.com> rminnich(a)google.com> >> Subject: Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages >> >> >> >> Hi >> >> >> >> here is the meeting recording: >> >> <https://linaro-org.zoom.us/rec/share/zjfHeMIumkJhirLCVQYTHR6ftaqyWvF_0klgQn…> https://linaro-org.zoom.us/rec/share/zjfHeMIumkJhirLCVQYTHR6ftaqyWvF_0klgQn… Passcode: IPn+5q%z >> >> >> >> I am really sorry about the confusion related to the meeting time. I have now understood: the Collaborate portal uses a specific calendar which is tied to US/Chicago timezone while the actual Google Calendar is tied to Central Europe timezone. I am going to drop the Collaborate portal and use a shared Google calendar (it should be visible on the <http://trusted-substrate.org> trusted-substrate.org page). >> >> >> >> I'll try to summarize what I learnt and highlight my view on what can be next steps in a future mail. >> >> >> >> Cheers >> >> >> >> FF >> >> >> >> On Thu, 8 Apr 2021 at 13:56, Manish Pandey2 via TF-A < <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org> wrote: >> >> Hi, >> >> >> >> From TF-A project point of view, we prefer to use existing mechanism to pass parameters across boot stages using linked list of tagged elements (as suggested by Julius). It has support for both generic and SiP-specific tags. Having said that, it does not stop partners to introduce new mechanisms suitable for their usecase in platform port initially and later move to generic code if its suitable for other platforms. >> >> >> >> To start with, Ampere can introduce a platform specific implementation of memory tag(speed/NUMA topology etc) which can be evaluated and discussed for generalization in future. The tag will be populated in BL2 stage and can be forwarded to further stages(and to BL33) by passing the head of list pointer in one of the registers. Initially any register can be used but going forward a standardization will be needed. >> >> >> >> The U-boot bloblist mentioned by Simon is conceptually similar to what TF-A is using, if there is consensus of using bloblist/taglist then TF-A tag list may be enhanced to take best of both the implementations. >> >> >> >> One of the potential problems of having structure used in different projects is maintainability, this can be avoided by having a single copy of these structures in TF-A (kept inside "include/export" which intended to be used by other projects.) >> >> >> >> Regarding usage of either UUID or tag, I echo the sentiments of Simon and Julius to keep it simple and use tag values. >> >> >> >> Looking forward to having further discussions on zoom call today. >> >> >> >> Thanks >> >> Manish P >> >> >> >> ________________________________ >> >> From: TF-A < <mailto:tf-a-bounces@lists.trustedfirmware.org> tf-a-bounces(a)lists.trustedfirmware.org> on behalf of Julius Werner via TF-A < <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org> >> Sent: 25 March 2021 02:43 >> To: Simon Glass < <mailto:sjg@chromium.org> sjg(a)chromium.org> >> Cc: Harb Abdulhamid OS < <mailto:abdulhamid@os.amperecomputing.com> abdulhamid(a)os.amperecomputing.com>; Boot Architecture Mailman List < <mailto:boot-architecture@lists.linaro.org> boot-architecture(a)lists.linaro.org>; <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org < <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org>; U-Boot Mailing List < <mailto:u-boot@lists.denx.de> u-boot(a)lists.denx.de>; Paul Isaac's < <mailto:paul.isaacs@linaro.org> paul.isaacs(a)linaro.org>; Ron Minnich < <mailto:rminnich@google.com> rminnich(a)google.com> >> Subject: Re: [TF-A] Proposal: TF-A to adopt hand-off blocks (HOBs) for information passing between boot stages >> >> >> >> Just want to point out that TF-A currently already supports a (very simple) mechanism like this: >> >> >> >> <https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/…> https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… >> >> <https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/…> https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… >> >> <https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/…> https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… >> >> >> >> It's just a linked list of tagged elements. The tag space is split into TF-A-wide generic tags and SiP-specific tags (with plenty of room to spare if more areas need to be defined -- a 64-bit tag can fit a lot). This is currently being used by some platforms that run coreboot in place of BL1/BL2, to pass information from coreboot (BL2) to BL31. >> >> >> >> I would echo Simon's sentiment of keeping this as simple as possible and avoiding complicated and bloated data structures with UUIDs. You usually want to parse something like this as early as possible in the passed-to firmware stage, particularly if the structure encodes information about the debug console (like it does for the platforms I mentioned above). For example, in BL31 this basically means doing it right after moving from assembly to C in bl31_early_platform_setup2() to get the console up before running anything else. At that point in the BL31 initialization, the MMU and caches are disabled, so data accesses are pretty expensive and you don't want to spend a lot of parsing effort or calculate complicated checksums or the like. You just want something extremely simple where you ideally have to touch every data word only once. >> >> >> >> On Wed, Mar 24, 2021 at 5:06 PM Simon Glass via TF-A < <mailto:tf-a@lists.trustedfirmware.org> tf-a(a)lists.trustedfirmware.org> wrote: >> >> Hi Harb, >> >> >> >> On Wed, 24 Mar 2021 at 11:39, Harb Abdulhamid OS < <mailto:abdulhamid@os.amperecomputing.com> abdulhamid(a)os.amperecomputing.com> wrote: >> >> Hello Folks, >> >> Appreciate the feedback and replies on this. Glad to see that there is interest in this topic. >> >> >> >> I try to address the comments/feedback from Francois and Simon below…. >> >> >> >> @François Ozog – happy to discuss this on a zoom call. I will make that time slot work, and will be available to attend April 8, 4pm CT. >> >> >> >> Note that I’m using the term “HOB” here more generically, as there are typically vendor specific structures beyond the resource descriptor HOB, which provides only a small subset of the information that needs to be passed between the boot phases. >> >> >> >> The whole point here is to provide mechanism to develop firmware that we can build ARM Server SoC’s that support *any* BL33 payload (e.g. EDK2, AptioV, CoreBoot, and maybe even directly boot strapping LinuxBoot at some point). In other-words, we are trying to come up with a TF-A that would be completely agnostic to the implementation of BL33 (i.e. BL33 is built completely independently by a separate entity – e.g. an ODM/OEM). >> >> >> >> Keep in mind, in the server/datacenter market segment we are not building vertically integrated systems with a single entity compiling firmware/software stacks like most folks in TF-A have become use to. There are two categories of higher level firmware code blobs in the server/datacenter model: >> >> “SoC” or “silicon” firmware – in TF-A this may map to BL1, BL2, BL31, and *possibly* one or more BL32 instances >> “Platform” or “board” firmware – in TF-A this may map to BL33 and *possibly* one or more BL32 instances. >> >> >> >> Even the platform firmware stack could be further fragmented by having multiple entities involved in delivering the entire firmware stack: IBVs, ODMs, OEMs, CSPs, and possibly even device vendor code. >> >> >> >> To support a broad range of platform designs with a broad range of memory devices, we need a crisp and clear contract between the SoC firmware that initializes memory (e.g. BL2) and how that platform boot firmware (e.g. BL33) gathers information about what memory that was initialized, at what speeds, NUMA topology, and many other relevant information that needs to be known and comprehended by the platform firmware and eventually by the platform software. >> >> >> >> I understand the versatility of DT, but I see two major problems with DT: >> >> DT requires more complicated parsing to get properties, and even more complex to dynamically set properties – this HOB structures may need to be generated in boot phases where DDR is not available, and therefore we will be extremely memory constrained. >> DT is probably overkill for this purpose – We really just want a list of pointers to simple C structures that code cast (e.g. JEDEC SPD data blob) >> >> >> >> I think that we should not mix the efforts around DT/ACPI specs with what we are doing here, because those specs and concepts were developed for a completely different purpose (i.e. abstractions needed for OS / RTOS software, and not necessarily suitable for firmware-to-firmware hand-offs). >> >> >> >> Frankly, I would personally push back pretty hard on defining SMC’s for something that should be one way information passing. Every SMC we add is another attack vector to the secure world and an increased burden on the folks that have to do security auditing and threat analysis. I see no benefit in exposing these boot/HOB/BOB structures at run-time via SMC calls. >> >> >> >> Please do let me know if you disagree and why. Look forward to discussing on this thread or on the call. >> >> >> >> @Simon Glass - Thanks for the pointer to bloblist. I briefly reviewed and it seems like a goo -- <https://drive.google.com/a/linaro.org/uc?id=0BxTAygkus3RgQVhuNHMwUi1mYWc&ex…> François-Frédéric Ozog | Director Linaro Edge & Fog Computing Group T: +33.67221.6485 <mailto:francois.ozog@linaro.org> francois.ozog(a)linaro.org | Skype: ffozog

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Re:[v9,23/28] mtd: spi-nor-core: Perform a Soft Reset on shutdown
by jaimeliao＠mxic.com.tw 21 Jun '21

21 Jun '21

Hi Pratyush +#ifdef CONFIG_SPI_FLASH_SOFT_RESET +/** + * spi_nor_soft_reset() - perform the JEDEC Software Reset sequence + * @nor: the spi_nor structure + * + * This function can be used to switch from Octal DTR mode to legacy mode on a + * flash that supports it. The soft reset is executed in Octal DTR mode. + * + * Return: 0 for success, -errno for failure. + */ +static int spi_nor_soft_reset(struct spi_nor *nor) +{ + struct spi_mem_op op; + int ret; + enum spi_nor_cmd_ext ext; + + ext = nor->cmd_ext_type; + nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; According JEDEC, cmd_ext_type has two different types, REPEAT and INVERT. Some Flash vendor using "INVERT" as cmd_ext_type so that it is not suitable for hard coding the type as REPEAT. Sending twice reset command with different types is clumsy but useful before read ID for getting Flash information. It would be great if you have any other ideas for this part. + + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DATA); + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) { + dev_warn(nor->dev, "Software reset enable failed: %d\n", ret); + goto out; + } + + op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DATA); + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); + ret = spi_mem_exec_op(nor->spi, &op); + if (ret) { + dev_warn(nor->dev, "Software reset failed: %d\n", ret); + goto out; + } + + /* + * Software Reset is not instant, and the delay varies from flash to + * flash. Looking at a few flashes, most range somewhere below 100 + * microseconds. So, wait for 200ms just to be sure. + */ + udelay(SPI_NOR_SRST_SLEEP_LEN); + +out: + nor->cmd_ext_type = ext; + return ret; +} Thanks Jaime CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. Macronix International Co., Ltd. ===================================================================== CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. Macronix International Co., Ltd. ===================================================================== ============================================================================ CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. Macronix International Co., Ltd. =====================================================================

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[PATCH v1] rockchip: rk3188-cru-common: sync clock dt-binding header from Linux
by Johan Jonker 21 Jun '21

21 Jun '21

In order to update the DT for rk3066 and rk3188 sync the clock dt-binding header. This is the state as of v5.12 in Linux. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- include/dt-bindings/clock/rk3188-cru-common.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 1e7931da0c..afad90680f 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <heiko(a)sntech.de> @@ -59,12 +59,14 @@ #define ACLK_LCDC1 196 #define ACLK_GPU 197 #define ACLK_SMC 198 -#define ACLK_CIF 199 +#define ACLK_CIF1 199 #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 #define ACLK_CPU 203 #define ACLK_PERI 204 +#define ACLK_VEPU 205 +#define ACLK_VDPU 206 /* pclk gates */ #define PCLK_GRF 320 @@ -125,8 +127,12 @@ #define HCLK_NANDC0 467 #define HCLK_CPU 468 #define HCLK_PERI 469 +#define HCLK_CIF1 470 +#define HCLK_VEPU 471 +#define HCLK_VDPU 472 +#define HCLK_HDMI 473 -#define CLK_NR_CLKS (HCLK_PERI + 1) +#define CLK_NR_CLKS (HCLK_HDMI + 1) /* soft-reset indices */ #define SRST_MCORE 2 -- 2.11.0

2 1

[PATCH] arm: add initial support for the Phytium Pomelo Board
by nicholas_zheng＠outlook.com 21 Jun '21

21 Jun '21

From: weichangzheng <nicholas_zheng(a)outlook.com> This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE. Signed-off-by: weichangzheng <nicholas_zheng(a)outlook.com> --- arch/arm/Kconfig | 8 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 103 +++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 164 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 61 ++++++++++++ board/phytium/pomelo/pll.c | 75 ++++++++++++++ board/phytium/pomelo/pomelo.c | 120 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 40 ++++++++ configs/pomelo_defconfig | 36 +++++++ include/configs/pomelo.h | 45 +++++++++ 14 files changed, 760 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..6110fcddad 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1800,6 +1800,13 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie. +config TARGET_POMELO + bool "Support Phytium Pomelo Platform" + select ARM64 + help + Support for pomelo platform. + It has 2GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2019,6 +2026,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 096068261d..c26692c17e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1098,6 +1098,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..4961682058 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium Pomelo board + * Copyright (C) 2021, Phytium Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ +/dts-v1/; + +/memreserve/ 0x0000000080000000 0x0000000000100000; +/ { + model = "Phytium Pomelo"; + compatible = "phytium,pomelo"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu8: cpu@8 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu9: cpu@9 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu12: cpu@12 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu13: cpu@13 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x301>; + enable-method = "psci"; + numa-node-id = <0>; + }; + }; + + pcie-controller@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + uart@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clock = <48000000>; + }; +}; diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig new file mode 100644 index 0000000000..281aa8feff --- /dev/null +++ b/board/phytium/pomelo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POMELO + +config SYS_BOARD + default "pomelo" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pomelo" + +endif diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS new file mode 100644 index 0000000000..950449392b --- /dev/null +++ b/board/phytium/pomelo/MAINTAINERS @@ -0,0 +1,8 @@ +POMELO BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pomelo/* +F: include/configs/pomelo.h +F: configs/pomelo_defconfig + diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile new file mode 100644 index 0000000000..b9cb3609bd --- /dev/null +++ b/board/phytium/pomelo/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pomelo.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o + + diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h new file mode 100644 index 0000000000..e15917609b --- /dev/null +++ b/board/phytium/pomelo/cpu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 + * Phytium Technology Ltd <www.phytium.com> + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_POMELO_H +#define _FT_POMELO_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/*CPU RESET*/ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460010 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460011 +#define CONFIG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define RC_MODE 0x1 +#define X8X8 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460014 +#define PARAM_MCU_VERSION 0x1 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x3 +#define PARAM_ECC_ENABLE 0x3 +#define PARAM_FORCE_SPD_DISABLE 0x0 +#define PARAM_MCU_MISC_ENABLE 0x0 + +#define UDIMM_TYPE 0x2 +#define DIMM_X8 0x1 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_POMELO_H */ diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c new file mode 100644 index 0000000000..88756f5fc1 --- /dev/null +++ b/board/phytium/pomelo/ddr.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct ddr_spd { + /******************* read from spd *****************/ + unsigned char dimm_type; /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */ + unsigned char data_width; /* 0: x4; 1: x8; 2: x16 */ + unsigned char mirror_type; /* 0: stardard; 1: mirror */ + unsigned char ecc_type; /* 0: no-ecc; 1:ecc */ + unsigned char dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + unsigned char rank_num; + unsigned char row_num; + unsigned char col_num; + + unsigned char bg_num; /*only DDR4*/ + unsigned char bank_num; + unsigned short int module_manufacturer_id; + unsigned short int taamin; + unsigned short int trcdmin; + + unsigned short int trpmin; + unsigned short int trasmin; + unsigned short int trcmin; + unsigned short int tfawmin; + + unsigned short int trrd_smin; /*only DDR4*/ + unsigned short int trrd_lmin; /*only DDR4*/ + unsigned short int tccd_lmin; /*only DDR4*/ + unsigned short int twrmin; + + unsigned short int twtr_smin; /*only DDR4*/ + unsigned short int twtr_lmin; /*only DDR4*/ + unsigned short int twtrmin; /*only DDR3*/ + unsigned short int trrdmin; /*only DDR3*/ + + /******************* RCD control words *****************/ + unsigned char f0rc03; /*bit[3:2]:CS bit[1:0]:CA */ + unsigned char f0rc04; /*bit[3:2]:ODT bit[1:0]:CKE */ + unsigned char f0rc05; /*bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + unsigned char bc00; + unsigned char bc01; + unsigned char bc02; + unsigned char bc03; + unsigned char bc04; + + unsigned char bc05; + unsigned char f5bc5x; + unsigned char f5bc6x; + /******************* LRDIMM special *****************/ + unsigned char vrefdq_pr0; + unsigned char vrefdq_mdram; + unsigned char rtt_mdram_1866; + unsigned char rtt_mdram_2400; + unsigned char rtt_mdram_3200; + + unsigned char drive_dram; + unsigned char odt_dram_1866; + unsigned char odt_dram_2400; + unsigned char odt_dram_3200; + unsigned char park_dram_1866; + unsigned char park_dram_2400; + unsigned char park_dram_3200; + unsigned char rcd_num; +} __attribute((aligned(4))); + +struct mcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + + unsigned char ch_enable; + unsigned char misc1_enable; + unsigned char misc2_enable; + unsigned char force_spd_enable; + unsigned char misc3_enable; + unsigned char train_debug; + unsigned char train_recover; + unsigned char rev2[9]; + + struct ddr_spd ddr_spd_info[2]; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; + pm->misc1_enable = PARAM_ECC_ENABLE; + pm->force_spd_enable = PARAM_FORCE_SPD_DISABLE; + pm->misc3_enable = PARAM_MCU_MISC_ENABLE; + pm->train_recover = 0x0; +} + +static unsigned char init_dimm_param(unsigned char ch, struct mcu_config *pm) +{ + printf("manual config dimm info...\n"); + pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE; + pm->ddr_spd_info[ch].data_width = DIMM_X8; + pm->ddr_spd_info[ch].mirror_type = NO_MIRROR; + pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info[ch].dram_type = DDR4_TYPE; + pm->ddr_spd_info[ch].rank_num = 1; + pm->ddr_spd_info[ch].row_num = 16; + pm->ddr_spd_info[ch].col_num = 10; + pm->ddr_spd_info[ch].bg_num = 4; + pm->ddr_spd_info[ch].bank_num = 4; + pm->ddr_spd_info[ch].taamin = 13750; + pm->ddr_spd_info[ch].trcdmin = 13750; + + pm->ddr_spd_info[ch].trpmin = 13750; + pm->ddr_spd_info[ch].trasmin = 32000; + pm->ddr_spd_info[ch].trcmin = 45750; + pm->ddr_spd_info[ch].tfawmin = 21000; + + pm->ddr_spd_info[ch].trrd_smin = 3000; + pm->ddr_spd_info[ch].trrd_lmin = 4900; + pm->ddr_spd_info[ch].tccd_lmin = 5000; + pm->ddr_spd_info[ch].twrmin = 15000; + + pm->ddr_spd_info[ch].twtr_smin = 2500; + pm->ddr_spd_info[ch].twtr_lmin = 7500; + + return 0; +} + +void get_default_mcu_info(unsigned char *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(unsigned char *data) +{ + unsigned char ch; + struct mcu_config *mcu_info = (struct mcu_config *)data; + + for (ch = 0; ch < 2; ch++) + init_dimm_param(ch, mcu_info); +} + +void ddr_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + printf("error x0: 0x%lx, x1: 0x%lx\n", res.a0, res.a1); + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c new file mode 100644 index 0000000000..3754d8eb9b --- /dev/null +++ b/board/phytium/pomelo/pcie.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pcu_ctr { + unsigned int base_config[3]; + unsigned int equalization[3]; + unsigned char rev[80]; +} __attribute((aligned(4))); + +struct pcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int independent_tree; + unsigned int base_cfg; + unsigned char rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x2, + .size = 0x100, + .independent_tree = CONFIG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))), + .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c new file mode 100644 index 0000000000..1227b7dd80 --- /dev/null +++ b/board/phytium/pomelo/pll.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pll_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int core_pll; + unsigned int res1; + unsigned int lmu_pll; + unsigned int res2; + unsigned int res3; + unsigned int res4; + unsigned int res5; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x1, + .size = 0x30, + .core_pll = 2300, /*MHz*/ + .lmu_pll = 667, /*MHz*/ +}; + +unsigned int get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +void pll_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} + +void check_reset(void) +{ + unsigned int rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c new file mode 100644 index 0000000000..693e891d20 --- /dev/null +++ b/board/phytium/pomelo/pomelo.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->mem_clk = 0; + gd->ram_size = PHYS_SDRAM_1_SIZE; + + printf("Phytium ddr init\n"); + + ddr_init(); + sec_init(); + printf("PBF relocate done\n"); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + printf("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + printf("reset cpu error, %lx\n", res.a0); +} + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +int board_early_init_r(void) +{ + return 0; +} + +static struct mm_region pomelo_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + { + .virt = (u64)PHYS_SDRAM_1, + .phys = (u64)PHYS_SDRAM_1, + .size = (u64)PHYS_SDRAM_1_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NS | + PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pomelo_mem_map; + +int __asm_flush_l3_dcache(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); + for (i = 0; i < HNF_COUNT; i++) { + do { + pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); + + return 0; +} + +int last_stage_init(void) +{ + int ret; + + /* pci e */ + pci_init(); + /* scsi scan */ + ret = scsi_scan(true); + if (ret) { + printf("scsi scan failed\n"); + return CMD_RET_FAILURE; + } + return ret; +} diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c new file mode 100644 index 0000000000..8ec0fa797b --- /dev/null +++ b/board/phytium/pomelo/sec.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct common_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned long long core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + + if (res.a0 != 0) { + printf("error ret %lx\n", res.a0); + while (true) + ; + } +} diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig new file mode 100644 index 0000000000..3e6c18196d --- /dev/null +++ b/configs/pomelo_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_POMELO=y +CONFIG_SYS_TEXT_BASE=0x180000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pomelo#" +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_PCI=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_BLK=y +# CONFIG_MMC is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_PHYTIUM=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h new file mode 100644 index 0000000000..69c4195d86 --- /dev/null +++ b/include/configs/pomelo.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __POMELO_CONFIG_H__ +#define __POMELO_CONFIG_H__ + +/* SDRAM Bank #1 start address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x7B000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000) + +/* SIZE of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) + +/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1 +#define CONFIG_PCI_SCAN_SHOW + +/* SCSI */ +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE 128 +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA_MAX_DEVICE 4 + +/*BOOT*/ +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "load_kernel=ext4load scsi 0:1 0x90100000 uImage_old\0" \ + "load_fdt=ext4load scsi 0:1 0x95000000 ft-d2000.dtb\0"\ + "boot_fdt=bootm 0x90100000 -:- 0x17c000\0" \ + "distro_bootcmd=run load_kernel; run boot_fdt" + +#endif -- 2.17.1

1 0

[PATCH] arm: add initial support for the Phytium Pomelo Board
by nicholas_zheng＠outlook.com 21 Jun '21

21 Jun '21

From: weichangzheng <nicholas_zheng(a)outlook.com> This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE. Signed-off-by: weichangzheng <nicholas_zheng(a)outlook.com> --- arch/arm/Kconfig | 8 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 103 +++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 164 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 61 ++++++++++++ board/phytium/pomelo/pll.c | 75 ++++++++++++++ board/phytium/pomelo/pomelo.c | 120 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 40 ++++++++ configs/pomelo_defconfig | 36 +++++++ include/configs/pomelo.h | 45 +++++++++ 14 files changed, 760 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..6110fcddad 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1800,6 +1800,13 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie. +config TARGET_POMELO + bool "Support Phytium Pomelo Platform" + select ARM64 + help + Support for pomelo platform. + It has 2GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2019,6 +2026,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 096068261d..c26692c17e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1098,6 +1098,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..4961682058 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium Pomelo board + * Copyright (C) 2021, Phytium Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ +/dts-v1/; + +/memreserve/ 0x0000000080000000 0x0000000000100000; +/ { + model = "Phytium Pomelo"; + compatible = "phytium,pomelo"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu8: cpu@8 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu9: cpu@9 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu12: cpu@12 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu13: cpu@13 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x301>; + enable-method = "psci"; + numa-node-id = <0>; + }; + }; + + pcie-controller@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + uart@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clock = <48000000>; + }; +}; diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig new file mode 100644 index 0000000000..281aa8feff --- /dev/null +++ b/board/phytium/pomelo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POMELO + +config SYS_BOARD + default "pomelo" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pomelo" + +endif diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS new file mode 100644 index 0000000000..950449392b --- /dev/null +++ b/board/phytium/pomelo/MAINTAINERS @@ -0,0 +1,8 @@ +POMELO BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pomelo/* +F: include/configs/pomelo.h +F: configs/pomelo_defconfig + diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile new file mode 100644 index 0000000000..b9cb3609bd --- /dev/null +++ b/board/phytium/pomelo/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pomelo.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o + + diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h new file mode 100644 index 0000000000..e15917609b --- /dev/null +++ b/board/phytium/pomelo/cpu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 + * Phytium Technology Ltd <www.phytium.com> + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_POMELO_H +#define _FT_POMELO_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/*CPU RESET*/ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460010 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460011 +#define CONFIG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define RC_MODE 0x1 +#define X8X8 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460014 +#define PARAM_MCU_VERSION 0x1 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x3 +#define PARAM_ECC_ENABLE 0x3 +#define PARAM_FORCE_SPD_DISABLE 0x0 +#define PARAM_MCU_MISC_ENABLE 0x0 + +#define UDIMM_TYPE 0x2 +#define DIMM_X8 0x1 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_POMELO_H */ diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c new file mode 100644 index 0000000000..88756f5fc1 --- /dev/null +++ b/board/phytium/pomelo/ddr.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct ddr_spd { + /******************* read from spd *****************/ + unsigned char dimm_type; /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */ + unsigned char data_width; /* 0: x4; 1: x8; 2: x16 */ + unsigned char mirror_type; /* 0: stardard; 1: mirror */ + unsigned char ecc_type; /* 0: no-ecc; 1:ecc */ + unsigned char dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + unsigned char rank_num; + unsigned char row_num; + unsigned char col_num; + + unsigned char bg_num; /*only DDR4*/ + unsigned char bank_num; + unsigned short int module_manufacturer_id; + unsigned short int taamin; + unsigned short int trcdmin; + + unsigned short int trpmin; + unsigned short int trasmin; + unsigned short int trcmin; + unsigned short int tfawmin; + + unsigned short int trrd_smin; /*only DDR4*/ + unsigned short int trrd_lmin; /*only DDR4*/ + unsigned short int tccd_lmin; /*only DDR4*/ + unsigned short int twrmin; + + unsigned short int twtr_smin; /*only DDR4*/ + unsigned short int twtr_lmin; /*only DDR4*/ + unsigned short int twtrmin; /*only DDR3*/ + unsigned short int trrdmin; /*only DDR3*/ + + /******************* RCD control words *****************/ + unsigned char f0rc03; /*bit[3:2]:CS bit[1:0]:CA */ + unsigned char f0rc04; /*bit[3:2]:ODT bit[1:0]:CKE */ + unsigned char f0rc05; /*bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + unsigned char bc00; + unsigned char bc01; + unsigned char bc02; + unsigned char bc03; + unsigned char bc04; + + unsigned char bc05; + unsigned char f5bc5x; + unsigned char f5bc6x; + /******************* LRDIMM special *****************/ + unsigned char vrefdq_pr0; + unsigned char vrefdq_mdram; + unsigned char rtt_mdram_1866; + unsigned char rtt_mdram_2400; + unsigned char rtt_mdram_3200; + + unsigned char drive_dram; + unsigned char odt_dram_1866; + unsigned char odt_dram_2400; + unsigned char odt_dram_3200; + unsigned char park_dram_1866; + unsigned char park_dram_2400; + unsigned char park_dram_3200; + unsigned char rcd_num; +} __attribute((aligned(4))); + +struct mcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + + unsigned char ch_enable; + unsigned char misc1_enable; + unsigned char misc2_enable; + unsigned char force_spd_enable; + unsigned char misc3_enable; + unsigned char train_debug; + unsigned char train_recover; + unsigned char rev2[9]; + + struct ddr_spd ddr_spd_info[2]; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; + pm->misc1_enable = PARAM_ECC_ENABLE; + pm->force_spd_enable = PARAM_FORCE_SPD_DISABLE; + pm->misc3_enable = PARAM_MCU_MISC_ENABLE; + pm->train_recover = 0x0; +} + +static unsigned char init_dimm_param(unsigned char ch, struct mcu_config *pm) +{ + printf("manual config dimm info...\n"); + pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE; + pm->ddr_spd_info[ch].data_width = DIMM_X8; + pm->ddr_spd_info[ch].mirror_type = NO_MIRROR; + pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info[ch].dram_type = DDR4_TYPE; + pm->ddr_spd_info[ch].rank_num = 1; + pm->ddr_spd_info[ch].row_num = 16; + pm->ddr_spd_info[ch].col_num = 10; + pm->ddr_spd_info[ch].bg_num = 4; + pm->ddr_spd_info[ch].bank_num = 4; + pm->ddr_spd_info[ch].taamin = 13750; + pm->ddr_spd_info[ch].trcdmin = 13750; + + pm->ddr_spd_info[ch].trpmin = 13750; + pm->ddr_spd_info[ch].trasmin = 32000; + pm->ddr_spd_info[ch].trcmin = 45750; + pm->ddr_spd_info[ch].tfawmin = 21000; + + pm->ddr_spd_info[ch].trrd_smin = 3000; + pm->ddr_spd_info[ch].trrd_lmin = 4900; + pm->ddr_spd_info[ch].tccd_lmin = 5000; + pm->ddr_spd_info[ch].twrmin = 15000; + + pm->ddr_spd_info[ch].twtr_smin = 2500; + pm->ddr_spd_info[ch].twtr_lmin = 7500; + + return 0; +} + +void get_default_mcu_info(unsigned char *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(unsigned char *data) +{ + unsigned char ch; + struct mcu_config *mcu_info = (struct mcu_config *)data; + + for (ch = 0; ch < 2; ch++) + init_dimm_param(ch, mcu_info); +} + +void ddr_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + printf("error x0: 0x%lx, x1: 0x%lx\n", res.a0, res.a1); + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c new file mode 100644 index 0000000000..3754d8eb9b --- /dev/null +++ b/board/phytium/pomelo/pcie.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pcu_ctr { + unsigned int base_config[3]; + unsigned int equalization[3]; + unsigned char rev[80]; +} __attribute((aligned(4))); + +struct pcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int independent_tree; + unsigned int base_cfg; + unsigned char rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x2, + .size = 0x100, + .independent_tree = CONFIG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))), + .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c new file mode 100644 index 0000000000..1227b7dd80 --- /dev/null +++ b/board/phytium/pomelo/pll.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pll_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int core_pll; + unsigned int res1; + unsigned int lmu_pll; + unsigned int res2; + unsigned int res3; + unsigned int res4; + unsigned int res5; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x1, + .size = 0x30, + .core_pll = 2300, /*MHz*/ + .lmu_pll = 667, /*MHz*/ +}; + +unsigned int get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +void pll_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} + +void check_reset(void) +{ + unsigned int rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c new file mode 100644 index 0000000000..693e891d20 --- /dev/null +++ b/board/phytium/pomelo/pomelo.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->mem_clk = 0; + gd->ram_size = PHYS_SDRAM_1_SIZE; + + printf("Phytium ddr init\n"); + + ddr_init(); + sec_init(); + printf("PBF relocate done\n"); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + printf("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + printf("reset cpu error, %lx\n", res.a0); +} + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +int board_early_init_r(void) +{ + return 0; +} + +static struct mm_region pomelo_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + { + .virt = (u64)PHYS_SDRAM_1, + .phys = (u64)PHYS_SDRAM_1, + .size = (u64)PHYS_SDRAM_1_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NS | + PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pomelo_mem_map; + +int __asm_flush_l3_dcache(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); + for (i = 0; i < HNF_COUNT; i++) { + do { + pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); + + return 0; +} + +int last_stage_init(void) +{ + int ret; + + /* pci e */ + pci_init(); + /* scsi scan */ + ret = scsi_scan(true); + if (ret) { + printf("scsi scan failed\n"); + return CMD_RET_FAILURE; + } + return ret; +} diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c new file mode 100644 index 0000000000..8ec0fa797b --- /dev/null +++ b/board/phytium/pomelo/sec.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct common_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned long long core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + + if (res.a0 != 0) { + printf("error ret %lx\n", res.a0); + while (true) + ; + } +} diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig new file mode 100644 index 0000000000..3e6c18196d --- /dev/null +++ b/configs/pomelo_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_POMELO=y +CONFIG_SYS_TEXT_BASE=0x180000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pomelo#" +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_PCI=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_BLK=y +# CONFIG_MMC is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_PHYTIUM=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h new file mode 100644 index 0000000000..69c4195d86 --- /dev/null +++ b/include/configs/pomelo.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __POMELO_CONFIG_H__ +#define __POMELO_CONFIG_H__ + +/* SDRAM Bank #1 start address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x7B000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000) + +/* SIZE of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) + +/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1 +#define CONFIG_PCI_SCAN_SHOW + +/* SCSI */ +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE 128 +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA_MAX_DEVICE 4 + +/*BOOT*/ +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "load_kernel=ext4load scsi 0:1 0x90100000 uImage_old\0" \ + "load_fdt=ext4load scsi 0:1 0x95000000 ft-d2000.dtb\0"\ + "boot_fdt=bootm 0x90100000 -:- 0x17c000\0" \ + "distro_bootcmd=run load_kernel; run boot_fdt" + +#endif -- 2.17.1

1 0

[PATCH] arm: add initial support for the Phytium Pomelo Board
by nicholas_zheng＠outlook.com 21 Jun '21

21 Jun '21

From: weichangzheng <nicholas_zheng(a)outlook.com> This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE. Signed-off-by: weichangzheng <nicholas_zheng(a)outlook.com> --- arch/arm/Kconfig | 8 ++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 103 +++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 164 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 61 ++++++++++++ board/phytium/pomelo/pll.c | 75 ++++++++++++++ board/phytium/pomelo/pomelo.c | 120 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 40 ++++++++ configs/pomelo_defconfig | 36 +++++++ include/configs/pomelo.h | 45 +++++++++ 14 files changed, 760 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..6110fcddad 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1800,6 +1800,13 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie. +config TARGET_POMELO + bool "Support Phytium Pomelo Platform" + select ARM64 + help + Support for pomelo platform. + It has 2GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2019,6 +2026,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 096068261d..c26692c17e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1098,6 +1098,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..4961682058 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium Pomelo board + * Copyright (C) 2021, Phytium Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ +/dts-v1/; + +/memreserve/ 0x0000000080000000 0x0000000000100000; +/ { + model = "Phytium Pomelo"; + compatible = "phytium,pomelo"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu8: cpu@8 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu9: cpu@9 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu12: cpu@12 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu13: cpu@13 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x301>; + enable-method = "psci"; + numa-node-id = <0>; + }; + }; + + pcie-controller@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + uart@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clock = <48000000>; + }; +}; diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig new file mode 100644 index 0000000000..281aa8feff --- /dev/null +++ b/board/phytium/pomelo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POMELO + +config SYS_BOARD + default "pomelo" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pomelo" + +endif diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS new file mode 100644 index 0000000000..950449392b --- /dev/null +++ b/board/phytium/pomelo/MAINTAINERS @@ -0,0 +1,8 @@ +POMELO BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pomelo/* +F: include/configs/pomelo.h +F: configs/pomelo_defconfig + diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile new file mode 100644 index 0000000000..b9cb3609bd --- /dev/null +++ b/board/phytium/pomelo/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pomelo.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o + + diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h new file mode 100644 index 0000000000..e15917609b --- /dev/null +++ b/board/phytium/pomelo/cpu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 + * Phytium Technology Ltd <www.phytium.com> + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_POMELO_H +#define _FT_POMELO_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/*CPU RESET*/ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460010 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460011 +#define CONFIG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define RC_MODE 0x1 +#define X8X8 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460014 +#define PARAM_MCU_VERSION 0x1 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x3 +#define PARAM_ECC_ENABLE 0x3 +#define PARAM_FORCE_SPD_DISABLE 0x0 +#define PARAM_MCU_MISC_ENABLE 0x0 + +#define UDIMM_TYPE 0x2 +#define DIMM_X8 0x1 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_POMELO_H */ diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c new file mode 100644 index 0000000000..88756f5fc1 --- /dev/null +++ b/board/phytium/pomelo/ddr.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct ddr_spd { + /******************* read from spd *****************/ + unsigned char dimm_type; /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */ + unsigned char data_width; /* 0: x4; 1: x8; 2: x16 */ + unsigned char mirror_type; /* 0: stardard; 1: mirror */ + unsigned char ecc_type; /* 0: no-ecc; 1:ecc */ + unsigned char dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + unsigned char rank_num; + unsigned char row_num; + unsigned char col_num; + + unsigned char bg_num; /*only DDR4*/ + unsigned char bank_num; + unsigned short int module_manufacturer_id; + unsigned short int taamin; + unsigned short int trcdmin; + + unsigned short int trpmin; + unsigned short int trasmin; + unsigned short int trcmin; + unsigned short int tfawmin; + + unsigned short int trrd_smin; /*only DDR4*/ + unsigned short int trrd_lmin; /*only DDR4*/ + unsigned short int tccd_lmin; /*only DDR4*/ + unsigned short int twrmin; + + unsigned short int twtr_smin; /*only DDR4*/ + unsigned short int twtr_lmin; /*only DDR4*/ + unsigned short int twtrmin; /*only DDR3*/ + unsigned short int trrdmin; /*only DDR3*/ + + /******************* RCD control words *****************/ + unsigned char f0rc03; /*bit[3:2]:CS bit[1:0]:CA */ + unsigned char f0rc04; /*bit[3:2]:ODT bit[1:0]:CKE */ + unsigned char f0rc05; /*bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + unsigned char bc00; + unsigned char bc01; + unsigned char bc02; + unsigned char bc03; + unsigned char bc04; + + unsigned char bc05; + unsigned char f5bc5x; + unsigned char f5bc6x; + /******************* LRDIMM special *****************/ + unsigned char vrefdq_pr0; + unsigned char vrefdq_mdram; + unsigned char rtt_mdram_1866; + unsigned char rtt_mdram_2400; + unsigned char rtt_mdram_3200; + + unsigned char drive_dram; + unsigned char odt_dram_1866; + unsigned char odt_dram_2400; + unsigned char odt_dram_3200; + unsigned char park_dram_1866; + unsigned char park_dram_2400; + unsigned char park_dram_3200; + unsigned char rcd_num; +} __attribute((aligned(4))); + +struct mcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + + unsigned char ch_enable; + unsigned char misc1_enable; + unsigned char misc2_enable; + unsigned char force_spd_enable; + unsigned char misc3_enable; + unsigned char train_debug; + unsigned char train_recover; + unsigned char rev2[9]; + + struct ddr_spd ddr_spd_info[2]; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; + pm->misc1_enable = PARAM_ECC_ENABLE; + pm->force_spd_enable = PARAM_FORCE_SPD_DISABLE; + pm->misc3_enable = PARAM_MCU_MISC_ENABLE; + pm->train_recover = 0x0; +} + +static unsigned char init_dimm_param(unsigned char ch, struct mcu_config *pm) +{ + printf("manual config dimm info...\n"); + pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE; + pm->ddr_spd_info[ch].data_width = DIMM_X8; + pm->ddr_spd_info[ch].mirror_type = NO_MIRROR; + pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info[ch].dram_type = DDR4_TYPE; + pm->ddr_spd_info[ch].rank_num = 1; + pm->ddr_spd_info[ch].row_num = 16; + pm->ddr_spd_info[ch].col_num = 10; + pm->ddr_spd_info[ch].bg_num = 4; + pm->ddr_spd_info[ch].bank_num = 4; + pm->ddr_spd_info[ch].taamin = 13750; + pm->ddr_spd_info[ch].trcdmin = 13750; + + pm->ddr_spd_info[ch].trpmin = 13750; + pm->ddr_spd_info[ch].trasmin = 32000; + pm->ddr_spd_info[ch].trcmin = 45750; + pm->ddr_spd_info[ch].tfawmin = 21000; + + pm->ddr_spd_info[ch].trrd_smin = 3000; + pm->ddr_spd_info[ch].trrd_lmin = 4900; + pm->ddr_spd_info[ch].tccd_lmin = 5000; + pm->ddr_spd_info[ch].twrmin = 15000; + + pm->ddr_spd_info[ch].twtr_smin = 2500; + pm->ddr_spd_info[ch].twtr_lmin = 7500; + + return 0; +} + +void get_default_mcu_info(unsigned char *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(unsigned char *data) +{ + unsigned char ch; + struct mcu_config *mcu_info = (struct mcu_config *)data; + + for (ch = 0; ch < 2; ch++) + init_dimm_param(ch, mcu_info); +} + +void ddr_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + printf("error x0: 0x%lx, x1: 0x%lx\n", res.a0, res.a1); + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c new file mode 100644 index 0000000000..3754d8eb9b --- /dev/null +++ b/board/phytium/pomelo/pcie.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pcu_ctr { + unsigned int base_config[3]; + unsigned int equalization[3]; + unsigned char rev[80]; +} __attribute((aligned(4))); + +struct pcu_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int independent_tree; + unsigned int base_cfg; + unsigned char rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x2, + .size = 0x100, + .independent_tree = CONFIG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))), + .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c new file mode 100644 index 0000000000..1227b7dd80 --- /dev/null +++ b/board/phytium/pomelo/pll.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct pll_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned int core_pll; + unsigned int res1; + unsigned int lmu_pll; + unsigned int res2; + unsigned int res3; + unsigned int res4; + unsigned int res5; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x1, + .size = 0x30, + .core_pll = 2300, /*MHz*/ + .lmu_pll = 667, /*MHz*/ +}; + +unsigned int get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +void pll_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + while (true) + ; + } +} + +void check_reset(void) +{ + unsigned int rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + while (true) + ; + } +} diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c new file mode 100644 index 0000000000..693e891d20 --- /dev/null +++ b/board/phytium/pomelo/pomelo.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->mem_clk = 0; + gd->ram_size = PHYS_SDRAM_1_SIZE; + + printf("Phytium ddr init\n"); + + ddr_init(); + sec_init(); + printf("PBF relocate done\n"); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + printf("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + printf("reset cpu error, %lx\n", res.a0); +} + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +int board_early_init_r(void) +{ + return 0; +} + +static struct mm_region pomelo_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + { + .virt = (u64)PHYS_SDRAM_1, + .phys = (u64)PHYS_SDRAM_1, + .size = (u64)PHYS_SDRAM_1_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NS | + PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pomelo_mem_map; + +int __asm_flush_l3_dcache(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); + for (i = 0; i < HNF_COUNT; i++) { + do { + pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); + + return 0; +} + +int last_stage_init(void) +{ + int ret; + + /* pci e */ + pci_init(); + /* scsi scan */ + ret = scsi_scan(true); + if (ret) { + printf("scsi scan failed\n"); + return CMD_RET_FAILURE; + } + return ret; +} diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c new file mode 100644 index 0000000000..8ec0fa797b --- /dev/null +++ b/board/phytium/pomelo/sec.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include "cpu.h" + +struct common_config { + unsigned int magic; + unsigned int version; + unsigned int size; + unsigned char rev1[4]; + unsigned long long core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + unsigned char buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + + if (res.a0 != 0) { + printf("error ret %lx\n", res.a0); + while (true) + ; + } +} diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig new file mode 100644 index 0000000000..3e6c18196d --- /dev/null +++ b/configs/pomelo_defconfig @@ -0,0 +1,36 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_POMELO=y +CONFIG_SYS_TEXT_BASE=0x180000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +# CONFIG_PSCI_RESET is not set +CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pomelo#" +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_PCI=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DM=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_BLK=y +# CONFIG_MMC is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_PHYTIUM=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h new file mode 100644 index 0000000000..69c4195d86 --- /dev/null +++ b/include/configs/pomelo.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __POMELO_CONFIG_H__ +#define __POMELO_CONFIG_H__ + +/* SDRAM Bank #1 start address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x7B000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000) + +/* SIZE of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) + +/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1 +#define CONFIG_PCI_SCAN_SHOW + +/* SCSI */ +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE 128 +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SATA_MAX_DEVICE 4 + +/*BOOT*/ +#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "load_kernel=ext4load scsi 0:1 0x90100000 uImage_old\0" \ + "load_fdt=ext4load scsi 0:1 0x95000000 ft-d2000.dtb\0"\ + "boot_fdt=bootm 0x90100000 -:- 0x17c000\0" \ + "distro_bootcmd=run load_kernel; run boot_fdt" + +#endif -- 2.17.1

1 0

[PATCH] arm64: zynqmp: Add missing year in Kria dts files
by Michal Simek 21 Jun '21

21 Jun '21

DT files have been added this year but forgot to update it that's why do it in separate patch now. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 +- arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi | 2 +- arch/arm/dts/zynqmp-smk-k26-revA.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index cca009e7c759..59d5751e0634 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -2,7 +2,7 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * SD level shifter: * "A" – A01 board un-modified (NXP) diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index d004ad143954..b5443afff982 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -2,7 +2,7 @@ /* * dts file for KV260 revA Carrier Card * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek(a)xilinx.com> */ diff --git a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi index 3f01233cc5a2..467df9f23a1c 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi +++ b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP K26/KV260 SD wiring * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek(a)xilinx.com> */ diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index b8a2249be426..b613ab234250 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP SM-K26 rev1/B/A * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek(a)xilinx.com> */ diff --git a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi index 8e9106792ff9..34e6328fb66f 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi +++ b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP Z2-VSOM * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek(a)xilinx.com> */ diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts index 300edc880093..c70966c1f344 100644 --- a/arch/arm/dts/zynqmp-smk-k26-revA.dts +++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A * - * (C) Copyright 2020, Xilinx, Inc. + * (C) Copyright 2020 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek(a)xilinx.com> */ -- 2.32.0

2 1

[PATCH] arm64: zynqmp: Add psgtr description to zc1751 dc1 board
by Michal Simek 21 Jun '21

21 Jun '21

Wire psgtr for zc1751 dc1 board. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index f7dc0f7fb6f6..b92a2ee3e60a 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -441,4 +441,7 @@ &zynqmp_dpsub { status = "okay"; + phy-names = "dp-phy0", "dp-phy1"; + phys = <&psgtr 1 PHY_TYPE_DP 0 0>, + <&psgtr 0 PHY_TYPE_DP 1 1>; }; -- 2.32.0

2 1

[PATCH] arm64: zynqmp: Remove gpio from aliases list
by Michal Simek 21 Jun '21

21 Jun '21

It is not recommended to have aliases for gpio. In past it was used in Linux for assigning numbers via sysfs which is deprecated and libgpiod should be used instead. In U-Boot this number is used for seq number but gpio offset are not counted from this number. That's why having these aliases only for seq number is not needed. As is done in Linux it is the best to use full gpio name instead of sequence number which depends on sequence in binding. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- ZynqMP> gpio status -a Bank gpio@ff0a0000: gpio@ff0a00000: input: 0 [ ] gpio@ff0a00001: input: 0 [ ] gpio@ff0a00002: input: 0 [ ] gpio@ff0a00003: input: 0 [ ] gpio@ff0a00004: input: 0 [ ] gpio@ff0a00005: input: 0 [ ] gpio@ff0a00006: input: 0 [ ] gpio@ff0a00007: input: 0 [ ] gpio@ff0a00008: input: 0 [ ] gpio@ff0a00009: input: 0 [ ] gpio@ff0a000010: input: 0 [ ] gpio@ff0a000011: input: 0 [ ] gpio@ff0a000012: input: 0 [ ] gpio@ff0a000013: input: 1 [ ] gpio@ff0a000014: input: 0 [ ] gpio@ff0a000015: input: 0 [ ] gpio@ff0a000016: input: 0 [ ] gpio@ff0a000017: input: 0 [ ] gpio@ff0a000018: input: 0 [ ] gpio@ff0a000019: input: 0 [ ] gpio@ff0a000020: input: 0 [ ] gpio@ff0a000021: input: 0 [ ] gpio@ff0a000022: input: 0 [ ] gpio@ff0a000023: input: 1 [ ] gpio@ff0a000024: input: 0 [ ] gpio@ff0a000025: input: 0 [ ] gpio@ff0a000026: input: 1 [ ] gpio@ff0a000027: input: 0 [ ] gpio@ff0a000028: input: 0 [ ] gpio@ff0a000029: input: 0 [ ] gpio@ff0a000030: input: 0 [ ] gpio@ff0a000031: output: 1 [ ] gpio@ff0a000032: input: 0 [ ] gpio@ff0a000033: input: 0 [ ] gpio@ff0a000034: input: 0 [ ] gpio@ff0a000035: input: 0 [ ] gpio@ff0a000036: input: 0 [ ] gpio@ff0a000037: input: 0 [ ] gpio@ff0a000038: input: 0 [ ] gpio@ff0a000039: input: 0 [ ] gpio@ff0a000040: input: 0 [ ] gpio@ff0a000041: input: 0 [ ] gpio@ff0a000042: input: 0 [ ] gpio@ff0a000043: input: 0 [ ] gpio@ff0a000044: input: 0 [ ] gpio@ff0a000045: input: 0 [ ] gpio@ff0a000046: input: 0 [ ] gpio@ff0a000047: input: 0 [ ] gpio@ff0a000048: input: 0 [ ] gpio@ff0a000049: input: 0 [ ] gpio@ff0a000050: input: 0 [ ] gpio@ff0a000051: input: 0 [ ] gpio@ff0a000052: input: 0 [ ] gpio@ff0a000053: input: 0 [ ] gpio@ff0a000054: input: 0 [ ] gpio@ff0a000055: input: 0 [ ] gpio@ff0a000056: input: 0 [ ] gpio@ff0a000057: input: 0 [ ] gpio@ff0a000058: input: 0 [ ] gpio@ff0a000059: input: 0 [ ] gpio@ff0a000060: input: 0 [ ] gpio@ff0a000061: input: 0 [ ] gpio@ff0a000062: input: 0 [ ] gpio@ff0a000063: input: 0 [ ] gpio@ff0a000064: input: 0 [ ] gpio@ff0a000065: input: 0 [ ] gpio@ff0a000066: input: 0 [ ] gpio@ff0a000067: input: 0 [ ] gpio@ff0a000068: input: 0 [ ] gpio@ff0a000069: input: 0 [ ] gpio@ff0a000070: input: 0 [ ] gpio@ff0a000071: input: 0 [ ] gpio@ff0a000072: input: 0 [ ] gpio@ff0a000073: input: 0 [ ] gpio@ff0a000074: input: 0 [ ] gpio@ff0a000075: input: 0 [ ] gpio@ff0a000076: input: 0 [ ] gpio@ff0a000077: input: 0 [ ] gpio@ff0a000078: input: 0 [ ] gpio@ff0a000079: input: 0 [ ] gpio@ff0a000080: input: 0 [ ] gpio@ff0a000081: input: 0 [ ] gpio@ff0a000082: input: 0 [ ] gpio@ff0a000083: input: 0 [ ] gpio@ff0a000084: input: 0 [ ] gpio@ff0a000085: input: 0 [ ] gpio@ff0a000086: input: 0 [ ] gpio@ff0a000087: input: 0 [ ] gpio@ff0a000088: input: 0 [ ] gpio@ff0a000089: input: 0 [ ] gpio@ff0a000090: input: 0 [ ] gpio@ff0a000091: input: 0 [ ] gpio@ff0a000092: input: 0 [ ] gpio@ff0a000093: input: 0 [ ] gpio@ff0a000094: input: 0 [ ] gpio@ff0a000095: input: 0 [ ] gpio@ff0a000096: input: 0 [ ] gpio@ff0a000097: input: 0 [ ] gpio@ff0a000098: input: 0 [ ] gpio@ff0a000099: input: 0 [ ] gpio@ff0a0000100: input: 0 [ ] gpio@ff0a0000101: input: 0 [ ] gpio@ff0a0000102: input: 0 [ ] gpio@ff0a0000103: input: 0 [ ] gpio@ff0a0000104: input: 0 [ ] gpio@ff0a0000105: input: 0 [ ] gpio@ff0a0000106: input: 0 [ ] gpio@ff0a0000107: input: 0 [ ] gpio@ff0a0000108: input: 0 [ ] gpio@ff0a0000109: input: 0 [ ] gpio@ff0a0000110: input: 0 [ ] gpio@ff0a0000111: input: 0 [ ] gpio@ff0a0000112: input: 0 [ ] gpio@ff0a0000113: input: 0 [ ] gpio@ff0a0000114: input: 0 [ ] gpio@ff0a0000115: input: 0 [ ] gpio@ff0a0000116: input: 0 [ ] gpio@ff0a0000117: input: 0 [ ] gpio@ff0a0000118: input: 0 [ ] gpio@ff0a0000119: input: 0 [ ] gpio@ff0a0000120: input: 0 [ ] gpio@ff0a0000121: input: 0 [ ] gpio@ff0a0000122: input: 0 [ ] gpio@ff0a0000123: input: 0 [ ] gpio@ff0a0000124: input: 0 [ ] gpio@ff0a0000125: input: 0 [ ] gpio@ff0a0000126: input: 0 [ ] gpio@ff0a0000127: input: 0 [ ] gpio@ff0a0000128: input: 0 [ ] gpio@ff0a0000129: input: 0 [ ] gpio@ff0a0000130: input: 0 [ ] gpio@ff0a0000131: input: 0 [ ] gpio@ff0a0000132: input: 0 [ ] gpio@ff0a0000133: input: 0 [ ] gpio@ff0a0000134: input: 0 [ ] gpio@ff0a0000135: input: 0 [ ] gpio@ff0a0000136: input: 0 [ ] gpio@ff0a0000137: input: 0 [ ] gpio@ff0a0000138: input: 0 [ ] gpio@ff0a0000139: input: 0 [ ] gpio@ff0a0000140: input: 0 [ ] gpio@ff0a0000141: input: 0 [ ] gpio@ff0a0000142: input: 0 [ ] gpio@ff0a0000143: input: 0 [ ] gpio@ff0a0000144: input: 0 [ ] gpio@ff0a0000145: input: 0 [ ] gpio@ff0a0000146: input: 0 [ ] gpio@ff0a0000147: input: 0 [ ] gpio@ff0a0000148: input: 0 [ ] gpio@ff0a0000149: input: 0 [ ] gpio@ff0a0000150: input: 0 [ ] gpio@ff0a0000151: input: 0 [ ] gpio@ff0a0000152: input: 0 [ ] gpio@ff0a0000153: input: 0 [ ] gpio@ff0a0000154: input: 0 [ ] gpio@ff0a0000155: input: 0 [ ] gpio@ff0a0000156: input: 0 [ ] gpio@ff0a0000157: input: 0 [ ] gpio@ff0a0000158: input: 0 [ ] gpio@ff0a0000159: input: 0 [ ] gpio@ff0a0000160: input: 0 [ ] gpio@ff0a0000161: input: 0 [ ] gpio@ff0a0000162: input: 0 [ ] gpio@ff0a0000163: input: 0 [ ] gpio@ff0a0000164: input: 0 [ ] gpio@ff0a0000165: input: 0 [ ] gpio@ff0a0000166: input: 0 [ ] gpio@ff0a0000167: input: 0 [ ] gpio@ff0a0000168: input: 0 [ ] gpio@ff0a0000169: input: 0 [ ] gpio@ff0a0000170: input: 0 [ ] gpio@ff0a0000171: input: 0 [ ] gpio@ff0a0000172: input: 0 [ ] gpio@ff0a0000173: input: 0 [ ] Bank gpio@20_: gpio@20_0: output: 0 [x] sel0.gpio-hog gpio@20_1: output: 1 [x] sel1.gpio-hog gpio@20_2: output: 1 [x] sel2.gpio-hog gpio@20_3: output: 1 [x] sel3.gpio-hog gpio@20_4: output: 1 [ ] gpio@20_5: output: 1 [ ] gpio@20_6: output: 1 [ ] gpio@20_7: output: 1 [ ] gpio@20_8: output: 1 [ ] gpio@20_9: output: 1 [ ] gpio@20_10: output: 1 [ ] gpio@20_11: output: 1 [ ] gpio@20_12: output: 1 [ ] gpio@20_13: output: 1 [ ] gpio@20_14: output: 1 [ ] gpio@20_15: output: 1 [ ] Bank gpio@21_: gpio@21_0: output: 1 [ ] gpio@21_1: output: 1 [ ] gpio@21_2: output: 1 [ ] gpio@21_3: output: 1 [ ] gpio@21_4: output: 1 [ ] gpio@21_5: input: 1 [ ] gpio@21_6: input: 1 [ ] gpio@21_7: input: 1 [ ] gpio@21_8: output: 1 [ ] gpio@21_9: output: 1 [ ] gpio@21_10: output: 1 [ ] gpio@21_11: output: 1 [ ] gpio@21_12: output: 1 [ ] gpio@21_13: output: 1 [ ] gpio@21_14: output: 1 [ ] gpio@21_15: output: 1 [ ] ZynqMP> gpio set 23 gpio: pin 23 (gpio 23) value is 1 ZynqMP> gpio status -a Bank gpio@ff0a0000: gpio@ff0a00000: input: 0 [ ] gpio@ff0a00001: input: 0 [ ] gpio@ff0a00002: input: 0 [ ] gpio@ff0a00003: input: 0 [ ] gpio@ff0a00004: input: 0 [ ] gpio@ff0a00005: input: 0 [ ] gpio@ff0a00006: input: 0 [ ] gpio@ff0a00007: input: 0 [ ] gpio@ff0a00008: input: 0 [ ] gpio@ff0a00009: input: 0 [ ] gpio@ff0a000010: input: 0 [ ] gpio@ff0a000011: input: 0 [ ] gpio@ff0a000012: input: 0 [ ] gpio@ff0a000013: input: 1 [ ] gpio@ff0a000014: input: 0 [ ] gpio@ff0a000015: input: 0 [ ] gpio@ff0a000016: input: 0 [ ] gpio@ff0a000017: input: 0 [ ] gpio@ff0a000018: input: 0 [ ] gpio@ff0a000019: input: 0 [ ] gpio@ff0a000020: input: 0 [ ] gpio@ff0a000021: input: 0 [ ] gpio@ff0a000022: input: 0 [ ] gpio@ff0a000023: output: 1 [ ] gpio@ff0a000024: input: 0 [ ] gpio@ff0a000025: input: 0 [ ] gpio@ff0a000026: input: 1 [ ] gpio@ff0a000027: input: 0 [ ] gpio@ff0a000028: input: 0 [ ] gpio@ff0a000029: input: 0 [ ] gpio@ff0a000030: input: 0 [ ] gpio@ff0a000031: output: 1 [ ] gpio@ff0a000032: input: 0 [ ] gpio@ff0a000033: input: 0 [ ] gpio@ff0a000034: input: 0 [ ] gpio@ff0a000035: input: 0 [ ] gpio@ff0a000036: input: 0 [ ] gpio@ff0a000037: input: 0 [ ] gpio@ff0a000038: input: 0 [ ] gpio@ff0a000039: input: 0 [ ] gpio@ff0a000040: input: 0 [ ] gpio@ff0a000041: input: 0 [ ] gpio@ff0a000042: input: 0 [ ] gpio@ff0a000043: input: 0 [ ] gpio@ff0a000044: input: 0 [ ] gpio@ff0a000045: input: 0 [ ] gpio@ff0a000046: input: 0 [ ] gpio@ff0a000047: input: 0 [ ] gpio@ff0a000048: input: 0 [ ] gpio@ff0a000049: input: 0 [ ] gpio@ff0a000050: input: 0 [ ] gpio@ff0a000051: input: 0 [ ] gpio@ff0a000052: input: 0 [ ] gpio@ff0a000053: input: 0 [ ] gpio@ff0a000054: input: 0 [ ] gpio@ff0a000055: input: 0 [ ] gpio@ff0a000056: input: 0 [ ] gpio@ff0a000057: input: 0 [ ] gpio@ff0a000058: input: 0 [ ] gpio@ff0a000059: input: 0 [ ] gpio@ff0a000060: input: 0 [ ] gpio@ff0a000061: input: 0 [ ] gpio@ff0a000062: input: 0 [ ] gpio@ff0a000063: input: 0 [ ] gpio@ff0a000064: input: 0 [ ] gpio@ff0a000065: input: 0 [ ] gpio@ff0a000066: input: 0 [ ] gpio@ff0a000067: input: 0 [ ] gpio@ff0a000068: input: 0 [ ] gpio@ff0a000069: input: 0 [ ] gpio@ff0a000070: input: 0 [ ] gpio@ff0a000071: input: 0 [ ] gpio@ff0a000072: input: 0 [ ] gpio@ff0a000073: input: 0 [ ] gpio@ff0a000074: input: 0 [ ] gpio@ff0a000075: input: 0 [ ] gpio@ff0a000076: input: 0 [ ] gpio@ff0a000077: input: 0 [ ] gpio@ff0a000078: input: 0 [ ] gpio@ff0a000079: input: 0 [ ] gpio@ff0a000080: input: 0 [ ] gpio@ff0a000081: input: 0 [ ] gpio@ff0a000082: input: 0 [ ] gpio@ff0a000083: input: 0 [ ] gpio@ff0a000084: input: 0 [ ] gpio@ff0a000085: input: 0 [ ] gpio@ff0a000086: input: 0 [ ] gpio@ff0a000087: input: 0 [ ] gpio@ff0a000088: input: 0 [ ] gpio@ff0a000089: input: 0 [ ] gpio@ff0a000090: input: 0 [ ] gpio@ff0a000091: input: 0 [ ] gpio@ff0a000092: input: 0 [ ] gpio@ff0a000093: input: 0 [ ] gpio@ff0a000094: input: 0 [ ] gpio@ff0a000095: input: 0 [ ] gpio@ff0a000096: input: 0 [ ] gpio@ff0a000097: input: 0 [ ] gpio@ff0a000098: input: 0 [ ] gpio@ff0a000099: input: 0 [ ] gpio@ff0a0000100: input: 0 [ ] gpio@ff0a0000101: input: 0 [ ] gpio@ff0a0000102: input: 0 [ ] gpio@ff0a0000103: input: 0 [ ] gpio@ff0a0000104: input: 0 [ ] gpio@ff0a0000105: input: 0 [ ] gpio@ff0a0000106: input: 0 [ ] gpio@ff0a0000107: input: 0 [ ] gpio@ff0a0000108: input: 0 [ ] gpio@ff0a0000109: input: 0 [ ] gpio@ff0a0000110: input: 0 [ ] gpio@ff0a0000111: input: 0 [ ] gpio@ff0a0000112: input: 0 [ ] gpio@ff0a0000113: input: 0 [ ] gpio@ff0a0000114: input: 0 [ ] gpio@ff0a0000115: input: 0 [ ] gpio@ff0a0000116: input: 0 [ ] gpio@ff0a0000117: input: 0 [ ] gpio@ff0a0000118: input: 0 [ ] gpio@ff0a0000119: input: 0 [ ] gpio@ff0a0000120: input: 0 [ ] gpio@ff0a0000121: input: 0 [ ] gpio@ff0a0000122: input: 0 [ ] gpio@ff0a0000123: input: 0 [ ] gpio@ff0a0000124: input: 0 [ ] gpio@ff0a0000125: input: 0 [ ] gpio@ff0a0000126: input: 0 [ ] gpio@ff0a0000127: input: 0 [ ] gpio@ff0a0000128: input: 0 [ ] gpio@ff0a0000129: input: 0 [ ] gpio@ff0a0000130: input: 0 [ ] gpio@ff0a0000131: input: 0 [ ] gpio@ff0a0000132: input: 0 [ ] gpio@ff0a0000133: input: 0 [ ] gpio@ff0a0000134: input: 0 [ ] gpio@ff0a0000135: input: 0 [ ] gpio@ff0a0000136: input: 0 [ ] gpio@ff0a0000137: input: 0 [ ] gpio@ff0a0000138: input: 0 [ ] gpio@ff0a0000139: input: 0 [ ] gpio@ff0a0000140: input: 0 [ ] gpio@ff0a0000141: input: 0 [ ] gpio@ff0a0000142: input: 0 [ ] gpio@ff0a0000143: input: 0 [ ] gpio@ff0a0000144: input: 0 [ ] gpio@ff0a0000145: input: 0 [ ] gpio@ff0a0000146: input: 0 [ ] gpio@ff0a0000147: input: 0 [ ] gpio@ff0a0000148: input: 0 [ ] gpio@ff0a0000149: input: 0 [ ] gpio@ff0a0000150: input: 0 [ ] gpio@ff0a0000151: input: 0 [ ] gpio@ff0a0000152: input: 0 [ ] gpio@ff0a0000153: input: 0 [ ] gpio@ff0a0000154: input: 0 [ ] gpio@ff0a0000155: input: 0 [ ] gpio@ff0a0000156: input: 0 [ ] gpio@ff0a0000157: input: 0 [ ] gpio@ff0a0000158: input: 0 [ ] gpio@ff0a0000159: input: 0 [ ] gpio@ff0a0000160: input: 0 [ ] gpio@ff0a0000161: input: 0 [ ] gpio@ff0a0000162: input: 0 [ ] gpio@ff0a0000163: input: 0 [ ] gpio@ff0a0000164: input: 0 [ ] gpio@ff0a0000165: input: 0 [ ] gpio@ff0a0000166: input: 0 [ ] gpio@ff0a0000167: input: 0 [ ] gpio@ff0a0000168: input: 0 [ ] gpio@ff0a0000169: input: 0 [ ] gpio@ff0a0000170: input: 0 [ ] gpio@ff0a0000171: input: 0 [ ] gpio@ff0a0000172: input: 0 [ ] gpio@ff0a0000173: input: 0 [ ] Bank gpio@20_: gpio@20_0: output: 0 [x] sel0.gpio-hog gpio@20_1: output: 1 [x] sel1.gpio-hog gpio@20_2: output: 1 [x] sel2.gpio-hog gpio@20_3: output: 1 [x] sel3.gpio-hog gpio@20_4: output: 1 [ ] gpio@20_5: output: 1 [ ] gpio@20_6: output: 1 [ ] gpio@20_7: output: 1 [ ] gpio@20_8: output: 1 [ ] gpio@20_9: output: 1 [ ] gpio@20_10: output: 1 [ ] gpio@20_11: output: 1 [ ] gpio@20_12: output: 1 [ ] gpio@20_13: output: 1 [ ] gpio@20_14: output: 1 [ ] gpio@20_15: output: 1 [ ] Bank gpio@21_: gpio@21_0: output: 1 [ ] gpio@21_1: output: 1 [ ] gpio@21_2: output: 1 [ ] gpio@21_3: output: 1 [ ] gpio@21_4: output: 1 [ ] gpio@21_5: input: 1 [ ] gpio@21_6: input: 1 [ ] gpio@21_7: input: 1 [ ] gpio@21_8: output: 1 [ ] gpio@21_9: output: 1 [ ] gpio@21_10: output: 1 [ ] gpio@21_11: output: 1 [ ] gpio@21_12: output: 1 [ ] gpio@21_13: output: 1 [ ] gpio@21_14: output: 1 [ ] gpio@21_15: output: 1 [ ] ZynqMP> ZynqMP> gpio clear gpio@ff0a000023 gpio: pin gpio@ff0a000023 (gpio 23) value is 0 ZynqMP> gpio status -a Bank gpio@ff0a0000: gpio@ff0a00000: input: 0 [ ] gpio@ff0a00001: input: 0 [ ] gpio@ff0a00002: input: 0 [ ] gpio@ff0a00003: input: 0 [ ] gpio@ff0a00004: input: 0 [ ] gpio@ff0a00005: input: 0 [ ] gpio@ff0a00006: input: 0 [ ] gpio@ff0a00007: input: 0 [ ] gpio@ff0a00008: input: 0 [ ] gpio@ff0a00009: input: 0 [ ] gpio@ff0a000010: input: 0 [ ] gpio@ff0a000011: input: 0 [ ] gpio@ff0a000012: input: 0 [ ] gpio@ff0a000013: input: 1 [ ] gpio@ff0a000014: input: 0 [ ] gpio@ff0a000015: input: 0 [ ] gpio@ff0a000016: input: 0 [ ] gpio@ff0a000017: input: 0 [ ] gpio@ff0a000018: input: 0 [ ] gpio@ff0a000019: input: 0 [ ] gpio@ff0a000020: input: 0 [ ] gpio@ff0a000021: input: 0 [ ] gpio@ff0a000022: input: 0 [ ] gpio@ff0a000023: output: 0 [ ] gpio@ff0a000024: input: 0 [ ] gpio@ff0a000025: input: 0 [ ] gpio@ff0a000026: input: 1 [ ] gpio@ff0a000027: input: 0 [ ] gpio@ff0a000028: input: 0 [ ] gpio@ff0a000029: input: 0 [ ] gpio@ff0a000030: input: 0 [ ] gpio@ff0a000031: output: 1 [ ] gpio@ff0a000032: input: 0 [ ] gpio@ff0a000033: input: 0 [ ] gpio@ff0a000034: input: 0 [ ] gpio@ff0a000035: input: 0 [ ] gpio@ff0a000036: input: 0 [ ] gpio@ff0a000037: input: 0 [ ] gpio@ff0a000038: input: 0 [ ] gpio@ff0a000039: input: 0 [ ] gpio@ff0a000040: input: 0 [ ] gpio@ff0a000041: input: 0 [ ] gpio@ff0a000042: input: 0 [ ] gpio@ff0a000043: input: 0 [ ] gpio@ff0a000044: input: 0 [ ] gpio@ff0a000045: input: 0 [ ] gpio@ff0a000046: input: 0 [ ] gpio@ff0a000047: input: 0 [ ] gpio@ff0a000048: input: 0 [ ] gpio@ff0a000049: input: 0 [ ] gpio@ff0a000050: input: 0 [ ] gpio@ff0a000051: input: 0 [ ] gpio@ff0a000052: input: 0 [ ] gpio@ff0a000053: input: 0 [ ] gpio@ff0a000054: input: 0 [ ] gpio@ff0a000055: input: 0 [ ] gpio@ff0a000056: input: 0 [ ] gpio@ff0a000057: input: 0 [ ] gpio@ff0a000058: input: 0 [ ] gpio@ff0a000059: input: 0 [ ] gpio@ff0a000060: input: 0 [ ] gpio@ff0a000061: input: 0 [ ] gpio@ff0a000062: input: 0 [ ] gpio@ff0a000063: input: 0 [ ] gpio@ff0a000064: input: 0 [ ] gpio@ff0a000065: input: 0 [ ] gpio@ff0a000066: input: 0 [ ] gpio@ff0a000067: input: 0 [ ] gpio@ff0a000068: input: 0 [ ] gpio@ff0a000069: input: 0 [ ] gpio@ff0a000070: input: 0 [ ] gpio@ff0a000071: input: 0 [ ] gpio@ff0a000072: input: 0 [ ] gpio@ff0a000073: input: 0 [ ] gpio@ff0a000074: input: 0 [ ] gpio@ff0a000075: input: 0 [ ] gpio@ff0a000076: input: 0 [ ] gpio@ff0a000077: input: 0 [ ] gpio@ff0a000078: input: 0 [ ] gpio@ff0a000079: input: 0 [ ] gpio@ff0a000080: input: 0 [ ] gpio@ff0a000081: input: 0 [ ] gpio@ff0a000082: input: 0 [ ] gpio@ff0a000083: input: 0 [ ] gpio@ff0a000084: input: 0 [ ] gpio@ff0a000085: input: 0 [ ] gpio@ff0a000086: input: 0 [ ] gpio@ff0a000087: input: 0 [ ] gpio@ff0a000088: input: 0 [ ] gpio@ff0a000089: input: 0 [ ] gpio@ff0a000090: input: 0 [ ] gpio@ff0a000091: input: 0 [ ] gpio@ff0a000092: input: 0 [ ] gpio@ff0a000093: input: 0 [ ] gpio@ff0a000094: input: 0 [ ] gpio@ff0a000095: input: 0 [ ] gpio@ff0a000096: input: 0 [ ] gpio@ff0a000097: input: 0 [ ] gpio@ff0a000098: input: 0 [ ] gpio@ff0a000099: input: 0 [ ] gpio@ff0a0000100: input: 0 [ ] gpio@ff0a0000101: input: 0 [ ] gpio@ff0a0000102: input: 0 [ ] gpio@ff0a0000103: input: 0 [ ] gpio@ff0a0000104: input: 0 [ ] gpio@ff0a0000105: input: 0 [ ] gpio@ff0a0000106: input: 0 [ ] gpio@ff0a0000107: input: 0 [ ] gpio@ff0a0000108: input: 0 [ ] gpio@ff0a0000109: input: 0 [ ] gpio@ff0a0000110: input: 0 [ ] gpio@ff0a0000111: input: 0 [ ] gpio@ff0a0000112: input: 0 [ ] gpio@ff0a0000113: input: 0 [ ] gpio@ff0a0000114: input: 0 [ ] gpio@ff0a0000115: input: 0 [ ] gpio@ff0a0000116: input: 0 [ ] gpio@ff0a0000117: input: 0 [ ] gpio@ff0a0000118: input: 0 [ ] gpio@ff0a0000119: input: 0 [ ] gpio@ff0a0000120: input: 0 [ ] gpio@ff0a0000121: input: 0 [ ] gpio@ff0a0000122: input: 0 [ ] gpio@ff0a0000123: input: 0 [ ] gpio@ff0a0000124: input: 0 [ ] gpio@ff0a0000125: input: 0 [ ] gpio@ff0a0000126: input: 0 [ ] gpio@ff0a0000127: input: 0 [ ] gpio@ff0a0000128: input: 0 [ ] gpio@ff0a0000129: input: 0 [ ] gpio@ff0a0000130: input: 0 [ ] gpio@ff0a0000131: input: 0 [ ] gpio@ff0a0000132: input: 0 [ ] gpio@ff0a0000133: input: 0 [ ] gpio@ff0a0000134: input: 0 [ ] gpio@ff0a0000135: input: 0 [ ] gpio@ff0a0000136: input: 0 [ ] gpio@ff0a0000137: input: 0 [ ] gpio@ff0a0000138: input: 0 [ ] gpio@ff0a0000139: input: 0 [ ] gpio@ff0a0000140: input: 0 [ ] gpio@ff0a0000141: input: 0 [ ] gpio@ff0a0000142: input: 0 [ ] gpio@ff0a0000143: input: 0 [ ] gpio@ff0a0000144: input: 0 [ ] gpio@ff0a0000145: input: 0 [ ] gpio@ff0a0000146: input: 0 [ ] gpio@ff0a0000147: input: 0 [ ] gpio@ff0a0000148: input: 0 [ ] gpio@ff0a0000149: input: 0 [ ] gpio@ff0a0000150: input: 0 [ ] gpio@ff0a0000151: input: 0 [ ] gpio@ff0a0000152: input: 0 [ ] gpio@ff0a0000153: input: 0 [ ] gpio@ff0a0000154: input: 0 [ ] gpio@ff0a0000155: input: 0 [ ] gpio@ff0a0000156: input: 0 [ ] gpio@ff0a0000157: input: 0 [ ] gpio@ff0a0000158: input: 0 [ ] gpio@ff0a0000159: input: 0 [ ] gpio@ff0a0000160: input: 0 [ ] gpio@ff0a0000161: input: 0 [ ] gpio@ff0a0000162: input: 0 [ ] gpio@ff0a0000163: input: 0 [ ] gpio@ff0a0000164: input: 0 [ ] gpio@ff0a0000165: input: 0 [ ] gpio@ff0a0000166: input: 0 [ ] gpio@ff0a0000167: input: 0 [ ] gpio@ff0a0000168: input: 0 [ ] gpio@ff0a0000169: input: 0 [ ] gpio@ff0a0000170: input: 0 [ ] gpio@ff0a0000171: input: 0 [ ] gpio@ff0a0000172: input: 0 [ ] gpio@ff0a0000173: input: 0 [ ] Bank gpio@20_: gpio@20_0: output: 0 [x] sel0.gpio-hog gpio@20_1: output: 1 [x] sel1.gpio-hog gpio@20_2: output: 1 [x] sel2.gpio-hog gpio@20_3: output: 1 [x] sel3.gpio-hog gpio@20_4: output: 1 [ ] gpio@20_5: output: 1 [ ] gpio@20_6: output: 1 [ ] gpio@20_7: output: 1 [ ] gpio@20_8: output: 1 [ ] gpio@20_9: output: 1 [ ] gpio@20_10: output: 1 [ ] gpio@20_11: output: 1 [ ] gpio@20_12: output: 1 [ ] gpio@20_13: output: 1 [ ] gpio@20_14: output: 1 [ ] gpio@20_15: output: 1 [ ] Bank gpio@21_: gpio@21_0: output: 1 [ ] gpio@21_1: output: 1 [ ] gpio@21_2: output: 1 [ ] gpio@21_3: output: 1 [ ] gpio@21_4: output: 1 [ ] gpio@21_5: input: 1 [ ] gpio@21_6: input: 1 [ ] gpio@21_7: input: 1 [ ] gpio@21_8: output: 1 [ ] gpio@21_9: output: 1 [ ] gpio@21_10: output: 1 [ ] gpio@21_11: output: 1 [ ] gpio@21_12: output: 1 [ ] gpio@21_13: output: 1 [ ] gpio@21_14: output: 1 [ ] gpio@21_15: output: 1 [ ] ZynqMP> --- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 1 - arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 1 - arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 1 - arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 1 - arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 1 - arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 1 - arch/arm/dts/zynqmp-sm-k26-revA.dts | 1 - arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 3 +-- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 1 - arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 1 - arch/arm/dts/zynqmp-zcu100-revC.dts | 1 - arch/arm/dts/zynqmp-zcu102-revA.dts | 1 - arch/arm/dts/zynqmp-zcu104-revA.dts | 1 - arch/arm/dts/zynqmp-zcu104-revC.dts | 1 - arch/arm/dts/zynqmp-zcu106-revA.dts | 1 - arch/arm/dts/zynqmp-zcu111-revA.dts | 1 - arch/arm/dts/zynqmp-zcu208-revA.dts | 1 - arch/arm/dts/zynqmp-zcu216-revA.dts | 1 - 21 files changed, 1 insertion(+), 22 deletions(-) diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index 7bcdbdfdbb06..32982020ff48 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -20,7 +20,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 69a3901ccf6c..004c4cb784d9 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -19,7 +19,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; mmc0 = &sdhci0; rtc0 = &rtc; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index a5db599c9497..0645ce931a23 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -19,7 +19,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 58df328c987f..93bda86636bc 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -19,7 +19,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 25d87532be77..39962eb0cdcb 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -19,7 +19,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index 82d5ef83f764..244662dab62c 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -20,7 +20,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index e4cf382a4975..ec0569452acf 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -22,7 +22,6 @@ "xlnx,zynqmp"; aliases { - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index a377f27c50d4..6ec96e0e8c96 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -19,7 +19,6 @@ "topic,miamimp", "xlnx,zynqmp"; aliases { - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 8f361e47bda1..e59342361397 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -21,7 +21,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c1; mmc0 = &sdhci0; mmc1 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 1a8cfdeb7f45..e9924674ab45 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -22,7 +22,6 @@ can0 = &can0; can1 = &can1; ethernet0 = &gem2; - gpio0 = &gpio; i2c0 = &i2c0; rtc0 = &rtc; serial0 = &uart0; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index c7de59e1e986..35fb33f12b6b 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm017-dc3 * - * (C) Copyright 2016 - 2020, Xilinx, Inc. + * (C) Copyright 2016 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek(a)xilinx.com> */ @@ -18,7 +18,6 @@ aliases { ethernet0 = &gem0; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 48acea62c888..d31582a979be 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -23,7 +23,6 @@ ethernet1 = &gem1; ethernet2 = &gem2; ethernet3 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; rtc0 = &rtc; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 41ab20c3895f..ae2d03d98322 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -21,7 +21,6 @@ aliases { ethernet0 = &gem1; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci0; diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 45dd7da7179b..2d615774782f 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -23,7 +23,6 @@ compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp"; aliases { - gpio0 = &gpio; i2c0 = &i2c1; rtc0 = &rtc; serial0 = &uart1; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 7190e876d8dd..cad0c62d084e 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -22,7 +22,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 76c635f0d460..9663ee8b49a6 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -21,7 +21,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index f9eb4caaf8c0..fd015fdef1af 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -21,7 +21,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c1; mmc0 = &sdhci1; rtc0 = &rtc; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 2b1255dc5f32..aa45470a7aef 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -22,7 +22,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 223bb8a61462..d020ed9e9130 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -22,7 +22,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 7607098ac077..bd04f902b7c9 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -22,7 +22,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 7ba60da131f1..d7513cd20eb0 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -22,7 +22,6 @@ aliases { ethernet0 = &gem3; - gpio0 = &gpio; i2c0 = &i2c0; i2c1 = &i2c1; mmc0 = &sdhci1; -- 2.32.0

2 1