June 2021 - U-Boot

[PATCH v2 0/1] sunxi: h3: Add initial ZeroPi support
by Yu-Tung Chang 19 Jun '21

19 Jun '21

This commit add support to FriendlyARM ZeroPi board. Board Schematic: http://wiki.friendlyarm.com/wiki/images/7/71/ZeroPi_20190731_Schematic.pdf - v1 . fix trailing whitespace - v2 . direct Copy Kernel DTs Yu-Tung Chang (1): sunxi: h3: Add initial ZeroPi support arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun8i-h3-zeropi.dts | 85 ++++++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 6 +++ configs/zeropi_defconfig | 13 +++++ 4 files changed, 106 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/sun8i-h3-zeropi.dts create mode 100644 configs/zeropi_defconfig -- 2.32.0

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[PULL] Pull request for u-boot next / v2021.10 = u-boot-stm32-20210618
by Patrice CHOTARD 18 Jun '21

18 Jun '21

Hi Tom, Please pull the STM32 related patches for u-boot/next, v2021.10: u-boot-stm32-20210618 CI status: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/7886 Thanks Patrice The following changes since commit a94b2aad05d52cbd49012ccd900bcbcf29f9bc22: Merge tag 'u-boot-atmel-2021.10-a' of https://source.denx.de/u-boot/custodians/u-boot-atmel into next (2021-06-17 11:46:44 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-stm.git tags/u-boot-stm32-20210618 for you to fetch changes up to c262522fd4ed453c079b09eb738ec4cbe4812478: clk: cosmetic change in uclass (2021-06-18 10:09:41 +0200) ---------------------------------------------------------------- - stm32mp157c-odyssey-som DT fixes - stm32_qspi: Fix short data write operation - dfu: set max_buf_size to erasesize also for NOR devices - Fixes ethernet clock property name for STM32MP1 board - STM32CubeProgrammer: various fixes - clk: cosmetic update for clk-uclass ---------------------------------------------------------------- Daniil Stas (1): spi: stm32_qspi: Fix short data write operation Grzegorz Szymaszek (5): arm: dts: stm32mp157c-odyssey-som: fix the basic SDMMC2 properties arm: dts: stm32mp157c-odyssey-som: enable all SDMMC2 data lanes arm: dts: stm32mp157c-odyssey-som: set the SDMMC2 VQMMC supply arm: dts: stm32mp157c-odyssey-som: enable the SDMMC2 eMMC HS DDR mode arm: dts: stm32mp157c-odyssey-som: enable SDMMC2 in SPL Patrick Delaunay (13): dfu: dfu_mtd: set max_buf_size to erasesize also for NOR devices board: stm32mp1: correct the property name for eth stm32mp: stm32prog: remove all the header check for UART download stm32mp: stm32prog: add timeout in stm32prog_serial_get_buffer stm32mp: stm32prog: add support of initrd in flashlayout stm32mp: stm32prog: solve compilation with CONFIG_FIT_SIGNATURE stm32mp: stm32prog: handle the next phase after USB re-enumeration stm32mp: stm32prog: correctly handle DM_PMIC stm32mp: stm32prog: use get_cpu_dev for GetID command stm32mp: stm32prog: change one message level to debug dfu: add error callback stm32mp: stm32prog: handle dfu error clk: cosmetic change in uclass arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 21 +++ arch/arm/dts/stm32mp157c-odyssey-som.dtsi | 15 +- .../arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c | 26 +++- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 43 +++-- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h | 7 +- .../mach-stm32mp/cmd_stm32prog/stm32prog_serial.c | 173 ++++----------------- .../arm/mach-stm32mp/cmd_stm32prog/stm32prog_usb.c | 7 +- board/dhelectronics/dh_stm32mp1/board.c | 4 +- board/st/stm32mp1/stm32mp1.c | 4 +- drivers/clk/clk-uclass.c | 2 +- drivers/dfu/dfu.c | 12 ++ drivers/dfu/dfu_mtd.c | 5 +- drivers/spi/stm32_qspi.c | 29 ++-- include/dfu.h | 11 ++ 14 files changed, 159 insertions(+), 200 deletions(-)

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Multi-Soc binary support for i.MX8M Mini/Nano/Plus/? in single boot firmware binary
by Tim Harvey 18 Jun '21

18 Jun '21

Greetings, I support various iMX8M PCB's via board/gateworks/venice that are SOM based and we are starting to add SOM's that have different IMX8M variant SoC's on them which for various reasons are not binary compatible. I'm very interested in coming up with a way to make them binary compatible to reduce the number of disk images and boot firmware binaries our users work with (along with the confusion of which one they need to use). >From what I see in working thus far with the IMX8M Mini, Nano, and Plus boot firmware differs in the following ways: - different primary image offsets - different dram config (phy training blob, phy cfg, cfg; which total about 3KiB for each config which varies based on dram type, soc variant, dram topology and bit-mapping) - different OCRAM sizes (compat binary would have to use the minimum size ie 256K) - different ATF binaries - different ATF load address - different pinmux/padconf/inputsel registers - different clk config The primary image offsets should be able to be dealt with by placing jumps at the various offsets and I believe the rest could be dealt with via runtime code if the SPL could load soc-specific blobs including dram config, ATF, binary firmware blobs from a nice indexed image such as FIT or binman. Currently imx8m SPL's use FIT images that are loaded entirely into OCRAM which becomes an issue when you have enough dram configs that they no longer fit in the OCRAM. Does anyone agree this is doable or is there something they see that would be a show-stopper? I'm not all that familiar with the merits of binman fs FIT images... I think they were developed for different things. I'm not sure if either/both are suited for what I'm talking about regarding having the SPL raw load binary blobs vs having them tacked onto a FIT image. I'm not sure if the imx8mq has enough in common to be able to do this with either, in fact I'm not even clear with SoC that is (is it what NXP calls i.MX 8M?) Best regards, Tim

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i.MX6UL: U-boot 2018.03 instability issue
by Rosario Borsellino 18 Jun '21

18 Jun '21

Hello everyone, This is the first time that I request help on a mailing list so tell me if I make anything wrong. I'm having hard time trying to debug an issue on U-boot 2018.03, built for a custom i.MX6UL platform. During the porting from U-boot 2015.04, as I need to display a splashcreen, I enabled the CONFIG_VIDEO property (alongside with the required initializations on my board sources). This made the work (I can see the default DENX splash on video) but made the U-boot unstable. As an example, if I run any fdt command from the shell, U-boot hangs with a data abort. Here the printout: ... => setenv loadfdt tftpboot ${fdtaddr} ${serverip}:${fdtfile} => setenv fdtaddr 0x83000000 => setenv fdtfile rb/imx6ul-dave-devel.dtb => setenv serverip 192.168.0.13 => setenv ipaddr 192.168.0.83 => run loadfdt Using FEC0 device TFTP from server 192.168.0.13; our IP address is 192.168.0.83 Filename 'rb/imx6ul-dave-devel.dtb'. Load address: 0x88000000 Loading: ######## 1.2 MiB/s done Bytes transferred = 38141 (94fd hex) => fdt addr ${fdtaddr} => fdt print /cb data abort pc : [<8ff460c0>] lr : [<8ff4c2c9>] reloc pc : [<878000c0>] lr : [<878062c9>] sp : 8df45cf8 ip : 00000000 fp : 00000003 r10: 8df50cd8 r9 : 8df45eb0 r8 : 00000003 r7 : fffffff5 r6 : 00000020 r5 : 00000000 r4 : 8ffbf514 r3 : 00000001 r2 : 0000894c r1 : 000000d8 r0 : fffffff5 Flags: nzcv IRQs on FIQs on Mode SVC_32 Resetting CPU ... resetting ... U-Boot SPL 2018.03-munich-2.0.0-rc4 (Jun 18 2021 - 09:16:52 +0200) ... But the instability is not only related to these commands (I use this as a PASS/FAIL test), so I don't either know where to check. Debugging via JTAG, with Trace32 tool, I can make the command print the requested node, but only if I run step-by-step. I found that CONFIG_VIDEO property enables by default the CONFIG_CONSOLE_MUX property, disabling the latter the fdt test pass. Has anyone ever seen this behaviour and can address me to find the root cause? I'm working on top of NXP stable branches, so I don't know if I can find help here. I also enbled the SPL build which is not officially supported by NXP. Let me know what printouts, code snippet or test to perform I need to share to help in the identification of the problem. Best regards, -- Rosario BORSELLINO DAVE Embedded Systems via Talponedo 29/A 33080 Porcia (PN) - Italy Telephone: +39.0434.921215 web: www.dave.eu

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[PATCH v4 0/5] rockchip_sfc: add support for Rockchip SFC
by Chris Morgan 18 Jun '21

18 Jun '21

From: Chris Morgan <macromorgan(a)hotmail.com> Changes from v3: - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux driver to fix potential issue on hardware. Note I never noticed this issue while testing, so I cannot test if it fixed any specific issue for me. - Updated of-compatible string back to "rockchip,sfc" to match what is currently proposed for upstream driver. The hardware itself has multiple versions but a register is present in the hardware that is read by the driver to set version specific functionality. - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that sfc nodes match what is in upstream. Changes from v2: - Resending due to glitch with patch file truncating final two lines on patch 1/5 and incorrect patch version number on patch 5/5. Changes from v1: - Reworked code to utilize spi-mem framework, and based it closely off of work in progress code for mainline Linux. - Removed DMA, as it didn't offer much performance benefit for booting (in my test cases), added complexity to the code, and interfered with A-TF. - Updated the names of the bindings to match the work in progress Linux code. - Moved alias to u-boot specific device-tree for Odroid Go Advance. Alias is updated with the spi0 node pointing to the SFC to help the sf command as well as facilitate booting from the SFC. - Note 2 below no longer applies, as rebasing this off of upstream code should allow the device to work for NAND, and by utilizing the spi-mem framework it no longer has to extract the parameters from the dm_spi_ops.xfer. Known Issues Remaining with this Patch Series: 1) I don't know the best way to upstream the XTX25F128B flash chip. This chip should use a continuation code for the manufacturer ID, however I cannot seem to find any way to actually read the continuation code as one may not be present. There is a risk of this driver, used as-is, to collide with another chip which has the same manufacturer ID with a different continuation code. Additionally, it might be worth mentioning but I noticed the Rockchip BROM will only boot the TPL/SPL off of the SFC if I write it to address 0x10000. This is not documented and different than the address looked at for SD card booting (512 * 64 = 0x8000 for SD Card booting). Also, like the SD card driver I can confirm that if DMA is enabled at the SPL stage A-TF seems to fail silently, then when Linux loads it hangs. FIFO mode was removed from the driver to simplify it and for this reason. Tested: Read (works) Write (works) Erase (works) SPL Read (works if you edit the u-boot,spl-boot-order) Chris Morgan (5): spi: rockchip_sfc: add support for Rockchip SFC rockchip: px30: Add support for using SFC rockchip: px30: add the serial flash controller mtd: spi-nor-ids: Add XTX XT25F128B rockchip: px30: add support for SFC for Odroid Go Advance arch/arm/dts/px30.dtsi | 38 ++ arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 18 + arch/arm/dts/rk3326-odroid-go2.dts | 16 + arch/arm/mach-rockchip/px30/px30.c | 64 +++ drivers/mtd/spi/Kconfig | 6 + drivers/mtd/spi/spi-nor-ids.c | 4 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/rockchip_sfc.c | 513 +++++++++++++++++++++ 9 files changed, 668 insertions(+) create mode 100644 drivers/spi/rockchip_sfc.c -- 2.25.1

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[PATCH v2] net: octeontx: smi: use dt live tree API
by Tim Harvey 18 Jun '21

18 Jun '21

clean up octeontx_smi_probe by using the live-tree API. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> Reviewed-by: Stefan Roese <sr(a)denx.de> --- v2: added reviewed-by tag --- drivers/net/octeontx/smi.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/net/octeontx/smi.c b/drivers/net/octeontx/smi.c index 27f4423c6a..d70fa820c7 100644 --- a/drivers/net/octeontx/smi.c +++ b/drivers/net/octeontx/smi.c @@ -314,10 +314,12 @@ read_error: int octeontx_smi_probe(struct udevice *dev) { - int ret, subnode, cnt = 0, node = dev_ofnode(dev).of_offset; - struct mii_dev *bus; - struct octeontx_smi_priv *priv; pci_dev_t bdf = dm_pci_get_bdf(dev); + struct octeontx_smi_priv *priv; + struct mii_dev *bus; + int ret, cnt = 0; + ofnode subnode; + u64 baseaddr; debug("SMI PCI device: %x\n", bdf); if (!dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM)) { @@ -325,14 +327,12 @@ int octeontx_smi_probe(struct udevice *dev) return -1; } - node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, - "cavium,thunder-8890-mdio-nexus"); - fdt_for_each_subnode(subnode, gd->fdt_blob, node) { - ret = fdt_node_check_compatible(gd->fdt_blob, subnode, - "cavium,thunder-8890-mdio"); - if (ret) + dev_for_each_subnode(subnode, dev) { + if (!ofnode_device_is_compatible(subnode, + "cavium,thunder-8890-mdio")) + continue; + if (ofnode_read_u64(subnode, "reg", &baseaddr)) continue; - bus = mdio_alloc(); priv = malloc(sizeof(*priv)); if (!bus || !priv) { @@ -347,9 +347,7 @@ int octeontx_smi_probe(struct udevice *dev) bus->priv = priv; priv->mode = CLAUSE22; - priv->baseaddr = (void __iomem *)fdtdec_get_addr(gd->fdt_blob, - subnode, - "reg"); + priv->baseaddr = (void __iomem *)baseaddr; debug("mdio base addr %p\n", priv->baseaddr); /* use given name or generate its own unique name */ -- 2.17.1

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[PATCH] cmd: pxe_utils: sysboot: fix crash if either board or soc are not set.
by Dimitri John Ledkov 18 Jun '21

18 Jun '21

If the environment does not have "soc" or "board" set, and fdtdir option is specified in extlinux.conf, the bootloader will crash whilst dereferencing a null pointer. Add a guard against null soc or board. Fixes a crash of qemu-riscv64_smode configuration, which does not have CONFIG_SYS_SOC defined. Signed-off-by: Dimitri John Ledkov <xnox(a)ubuntu.com> --- cmd/pxe_utils.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/cmd/pxe_utils.c b/cmd/pxe_utils.c index 71c5af4c25..9a30629e26 100644 --- a/cmd/pxe_utils.c +++ b/cmd/pxe_utils.c @@ -587,6 +587,14 @@ static int label_boot(struct cmd_tbl *cmdtp, struct pxe_label *label) f2 = "-"; f3 = env_get("board"); f4 = ".dtb"; + if (!f1) { + f1 = ""; + f2 = ""; + } + if (!f3) { + f2 = ""; + f3 = ""; + } } len = strlen(label->fdtdir); -- 2.27.0

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[PATCH] dfu: dfu_mtd: set max_buf_size to erasesize also for NOR devices
by Patrick Delaunay 18 Jun '21

18 Jun '21

For NOR devices the logical DFU buffer size is the sector_size, as it is done in dfu_sf.c or in spi/sf_mtd.c (sf_mtd_info.erasesize = flash->sector_size) For NAND the DFU size was already limited to erasesize as has_pages = true. So the mtd dfu backend can use this erasesize for all the MTD devices, NOR and NAND with dfu->max_buf_size = mtd->erasesize This difference was initially copied from MTD command, where data is fully available in RAM without size limitation. This patch avoids to have many sector write in dfu_mtd.c at the end of the DFU transfer and avoids issues with USB timeout or WATCHDOG. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/dfu/dfu_mtd.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c index ca67585a7e..7efb3cbd79 100644 --- a/drivers/dfu/dfu_mtd.c +++ b/drivers/dfu/dfu_mtd.c @@ -252,7 +252,6 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char *s) { char *st; struct mtd_info *mtd; - bool has_pages; int ret, part; mtd = get_mtd_device_nm(devstr); @@ -262,9 +261,7 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char *s) dfu->dev_type = DFU_DEV_MTD; dfu->data.mtd.info = mtd; - - has_pages = mtd->type == MTD_NANDFLASH || mtd->type == MTD_MLCNANDFLASH; - dfu->max_buf_size = has_pages ? mtd->erasesize : 0; + dfu->max_buf_size = mtd->erasesize; st = strsep(&s, " "); if (!strcmp(st, "raw")) { -- 2.17.1

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[PATCH] net: dwc_eth_qos: Fix needless phy auto-negotiation restarts
by Daniil Stas 18 Jun '21

18 Jun '21

Disabling clk_ck clock leads to link up status loss in phy, which leads to auto-negotiation restart before each network command execution. This issue is especially big for PXE boot protocol because of auto-negotiation restarts before each configuration filename trial. To avoid this issue don't disable clk_ck clock after it was enabled. Signed-off-by: Daniil Stas <daniil.stas(a)posteo.net> Cc: Ramon Fried <rfried.dev(a)gmail.com> Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> --- drivers/net/dwc_eth_qos.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index e8242ca4e1..2f088c758f 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -321,6 +321,7 @@ struct eqos_priv { void *rx_pkt; bool started; bool reg_access_ok; + bool clk_ck_enabled; }; /* @@ -591,12 +592,13 @@ static int eqos_start_clks_stm32(struct udevice *dev) goto err_disable_clk_rx; } - if (clk_valid(&eqos->clk_ck)) { + if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) { ret = clk_enable(&eqos->clk_ck); if (ret < 0) { pr_err("clk_enable(clk_ck) failed: %d", ret); goto err_disable_clk_tx; } + eqos->clk_ck_enabled = true; } #endif @@ -648,8 +650,6 @@ static void eqos_stop_clks_stm32(struct udevice *dev) clk_disable(&eqos->clk_tx); clk_disable(&eqos->clk_rx); clk_disable(&eqos->clk_master_bus); - if (clk_valid(&eqos->clk_ck)) - clk_disable(&eqos->clk_ck); #endif debug("%s: OK\n", __func__); -- 2.31.0

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[PATCH v2 0/5] arm: dts: stm32mp157c-odyssey-som: sync SDMMC2 with Linux and TF‑A
by Grzegorz Szymaszek 18 Jun '21

18 Jun '21

This patchset updates the properties of the SDMMC2 device tree node so that they match their Linux kernel and Trusted Firmware A counterparts. Two differences will remain: — in the Linux kernel device tree, the VQMMC supply is incorrectly set to v3v3 (buck4) instead of vdd (buck3); — in the TF‑A device tree, only the “default” pinctrl is configured. Additionally, this patchset enables SDMMC2 in SPL. Changes for v2: — rebased on current master (no code changes); — added Patrice Chotard’s Reviewed-by (thanks!); — added missing commit message bodies. Grzegorz Szymaszek (5): arm: dts: stm32mp157c-odyssey-som: fix the basic SDMMC2 properties arm: dts: stm32mp157c-odyssey-som: enable all SDMMC2 data lanes arm: dts: stm32mp157c-odyssey-som: set the SDMMC2 VQMMC supply arm: dts: stm32mp157c-odyssey-som: enable the SDMMC2 eMMC HS DDR mode arm: dts: stm32mp157c-odyssey-som: enable SDMMC2 in SPL .../dts/stm32mp157c-odyssey-som-u-boot.dtsi | 21 +++++++++++++++++++ arch/arm/dts/stm32mp157c-odyssey-som.dtsi | 15 +++++++------ 2 files changed, 30 insertions(+), 6 deletions(-) -- 2.30.2

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