April 2021 - U-Boot

[PATCH 0/5] Synology DS414 integration mini-review
by Phil Sutter 08 Apr '21

08 Apr '21

Board-specific code lacked a Kconfig file defining CONFIG_SYS_BOARD, CONFIG_SYS_VENDOR, etc - patch 1 fixes that. I was very pleased to notice the recent changes in PCI/USB code fixed xhci-pci functionality on DS414, so patch 2 enables XHCI support in defconfig. Adjusting DS109 atags code for DS414 allowed to successfully boot vendor Linux, so I went ahead and generalized the code to support both boards in patch 3. Patch 4 introduces a misc_init_r() routine populating environment from Synology's special flash partition if appropriate - less manual work for users and no need for random MAC address fallback anymore. Patch 6 extends the default environment by a command to update u-boot via tftp. Phil Sutter (5): ds414: Add a Kconfig defining some strings configs: ds414: Enable XHCI_PCI by default board/Synology: Unify legacy kernel support ds414: Auto-populate env if appropriate ds414: Add sample u-boot update command board/Synology/common/Makefile | 5 +++ board/Synology/common/legacy.c | 75 +++++++++++++++++++++++++++++++++ board/Synology/common/legacy.h | 33 +++++++++++++++ board/Synology/ds109/ds109.c | 32 -------------- board/Synology/ds109/ds109.h | 17 -------- board/Synology/ds414/Kconfig | 12 ++++++ board/Synology/ds414/cmd_syno.c | 2 +- board/Synology/ds414/ds414.c | 13 ++++++ configs/ds414_defconfig | 7 ++- include/configs/ds109.h | 3 +- include/configs/ds414.h | 20 ++++++++- 11 files changed, 163 insertions(+), 56 deletions(-) create mode 100644 board/Synology/common/Makefile create mode 100644 board/Synology/common/legacy.c create mode 100644 board/Synology/common/legacy.h create mode 100644 board/Synology/ds414/Kconfig -- 2.30.1

2 29

[PATCH u-boot-marvell v2 1/4] rtc: add armada38x driver
by Marek Behún 08 Apr '21

08 Apr '21

Add RTC driver for Armada 38x, based on Linux' driver. For now implement only `marvell,armada-380-rtc` compatible. Signed-off-by: Marek Behún <marek.behun(a)nic.cz> Reviewed-by: Stefan Roese <sr(a)denx.de> Cc: Pali Rohár <pali(a)kernel.org> Cc: Baruch Siach <baruch(a)tkos.co.il> Cc: Chris Packham <judge.packham(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> --- drivers/rtc/Kconfig | 7 ++ drivers/rtc/Makefile | 1 + drivers/rtc/armada38x.c | 184 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+) create mode 100644 drivers/rtc/armada38x.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index aa6d90158c..dafba35279 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -38,6 +38,13 @@ config RTC_ENABLE_32KHZ_OUTPUT Some real-time clocks support the output of 32kHz square waves (such as ds3231), the config symbol choose Real Time Clock device 32Khz output feature. +config RTC_ARMADA38X + bool "Enable Armada 38x Marvell SoC RTC" + depends on DM_RTC && ARCH_MVEBU + help + This adds support for the in-chip RTC that can be found in the + Armada 38x Marvell's SoC devices. + config RTC_PCF2127 bool "Enable PCF2127 driver" depends on DM_RTC diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 6a45a9c874..15609e7b18 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM_RTC) += rtc-uclass.o obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o obj-y += rtc-lib.o +obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o obj-$(CONFIG_RTC_DAVINCI) += davinci.o obj-$(CONFIG_RTC_DS1302) += ds1302.o obj-$(CONFIG_RTC_DS1306) += ds1306.o diff --git a/drivers/rtc/armada38x.c b/drivers/rtc/armada38x.c new file mode 100644 index 0000000000..2d264acf77 --- /dev/null +++ b/drivers/rtc/armada38x.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RTC driver for the Armada 38x Marvell SoCs + * + * Copyright (C) 2021 Marek Behun <marek.behun(a)nic.cz> + * + * Based on Linux' driver by Gregory Clement and Marvell + */ + +#include <asm/io.h> +#include <dm.h> +#include <linux/delay.h> +#include <rtc.h> + +#define RTC_STATUS 0x0 +#define RTC_TIME 0xC +#define RTC_CONF_TEST 0x1C + +/* Armada38x SoC registers */ +#define RTC_38X_BRIDGE_TIMING_CTL 0x0 +#define RTC_38X_PERIOD_OFFS 0 +#define RTC_38X_PERIOD_MASK (0x3FF << RTC_38X_PERIOD_OFFS) +#define RTC_38X_READ_DELAY_OFFS 26 +#define RTC_38X_READ_DELAY_MASK (0x1F << RTC_38X_READ_DELAY_OFFS) + +#define SAMPLE_NR 100 + +struct armada38x_rtc { + void __iomem *regs; + void __iomem *regs_soc; +}; + +/* + * According to Erratum RES-3124064 we have to do some configuration in MBUS. + * To read an RTC register we need to read it 100 times and return the most + * frequent value. + * To write an RTC register we need to write 2x zero into STATUS register, + * followed by the proper write. Linux adds an 5 us delay after this, so we do + * it here as well. + */ +static void update_38x_mbus_timing_params(struct armada38x_rtc *rtc) +{ + u32 reg; + + reg = readl(rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); + reg &= ~RTC_38X_PERIOD_MASK; + reg |= 0x3FF << RTC_38X_PERIOD_OFFS; /* Maximum value */ + reg &= ~RTC_38X_READ_DELAY_MASK; + reg |= 0x1F << RTC_38X_READ_DELAY_OFFS; /* Maximum value */ + writel(reg, rtc->regs_soc + RTC_38X_BRIDGE_TIMING_CTL); +} + +static void armada38x_rtc_write(u32 val, struct armada38x_rtc *rtc, u8 reg) +{ + writel(0, rtc->regs + RTC_STATUS); + writel(0, rtc->regs + RTC_STATUS); + writel(val, rtc->regs + reg); + udelay(5); +} + +static u32 armada38x_rtc_read(struct armada38x_rtc *rtc, u8 reg) +{ + u8 counts[SAMPLE_NR], max_idx; + u32 samples[SAMPLE_NR], max; + int i, j, last; + + for (i = 0, last = 0; i < SAMPLE_NR; ++i) { + u32 sample = readl(rtc->regs + reg); + + /* find if this value was already read */ + for (j = 0; j < last; ++j) { + if (samples[j] == sample) + break; + } + + if (j < last) { + /* if yes, increment count */ + ++counts[j]; + } else { + /* if not, add */ + samples[last] = sample; + counts[last] = 1; + ++last; + } + } + + /* finally find the sample that was read the most */ + max = 0; + max_idx = 0; + + for (i = 0; i < last; ++i) { + if (counts[i] > max) { + max = counts[i]; + max_idx = i; + } + } + + return samples[max_idx]; +} + +static int armada38x_rtc_get(struct udevice *dev, struct rtc_time *tm) +{ + struct armada38x_rtc *rtc = dev_get_priv(dev); + u32 time; + + time = armada38x_rtc_read(rtc, RTC_TIME); + + rtc_to_tm(time, tm); + + return 0; +} + +static int armada38x_rtc_reset(struct udevice *dev) +{ + struct armada38x_rtc *rtc = dev_get_priv(dev); + u32 reg; + + reg = armada38x_rtc_read(rtc, RTC_CONF_TEST); + + if (reg & 0xff) { + armada38x_rtc_write(0, rtc, RTC_CONF_TEST); + mdelay(500); + armada38x_rtc_write(0, rtc, RTC_TIME); + armada38x_rtc_write(BIT(0) | BIT(1), 0, RTC_STATUS); + } + + return 0; +} + +static int armada38x_rtc_set(struct udevice *dev, const struct rtc_time *tm) +{ + struct armada38x_rtc *rtc = dev_get_priv(dev); + unsigned long time; + + time = rtc_mktime(tm); + + if (time > U32_MAX) + printf("%s: requested time to set will overflow\n", dev->name); + + armada38x_rtc_reset(dev); + armada38x_rtc_write(time, rtc, RTC_TIME); + + return 0; +} + +static int armada38x_probe(struct udevice *dev) +{ + struct armada38x_rtc *rtc = dev_get_priv(dev); + + rtc->regs = dev_remap_addr_name(dev, "rtc"); + if (!rtc->regs) + goto err; + + rtc->regs_soc = dev_remap_addr_name(dev, "rtc-soc"); + if (!rtc->regs_soc) + goto err; + + update_38x_mbus_timing_params(rtc); + + return 0; +err: + printf("%s: io address missing\n", dev->name); + return -ENODEV; +} + +static const struct rtc_ops armada38x_rtc_ops = { + .get = armada38x_rtc_get, + .set = armada38x_rtc_set, + .reset = armada38x_rtc_reset, +}; + +static const struct udevice_id armada38x_rtc_ids[] = { + { .compatible = "marvell,armada-380-rtc", .data = 0 }, + { } +}; + +U_BOOT_DRIVER(rtc_armada38x) = { + .name = "rtc-armada38x", + .id = UCLASS_RTC, + .of_match = armada38x_rtc_ids, + .probe = armada38x_probe, + .priv_auto = sizeof(struct armada38x_rtc), + .ops = &armada38x_rtc_ops, +}; -- 2.26.2

3 8

[PATCH v4 0/7] Add FU740 chip and HiFive Unmatched board support
by Green Wan 08 Apr '21

08 Apr '21

This patch set is to add SiFive fu740 chip and HiFive Unmatched board support. Patches are split into several parts: - [PATCH 1/7] dts for fu740 - [PATCH 2/7] support for fu740 cpu - [PATCH 3/7- 4/7] support for fu740 clk and ram - [PATCH 5/7] add pcie driver - [PATCH 6/7] add unmatched board - [PATCH 7/7] add fu740 support to macb driver Description - For fu740 cpu support, reuse most of fu540 cpu. - For prci driver, add one abstract layer to separate fu540 and fu740. Move orignal fu540 code to separate files. - For pcie driver, it depends on gpio, prci, clk and reset drivers to do init&reset works. - Align with Linux DT file. Tests and patch checks - Able to boot both unmatched and unleashed boards. - PCIe tests . M.2 NVMe SSD . e1000 compatibale ethernet adapter (ping&tftpboot) . pci-to-usb adapter(usb mass storage) - checkpatch is performed. To keep code derived from other boards the same, ignore some warnings/errors in [PATCH 7/8]. Changlogs - V4 . fixed incorrect file name in ./board/sifive/unmatched/Makefile . fixed link in doc/board/sifive/index.rst, passed 'make htmldocs' - V3 . Rebase to unleashed rename v2 patch . Rename doc/board/sifive/unmatched.rst board/sifive/unmatched/unmatched.c . Fix tail whitespace . Add 'git mv' info to ram driver and merge patch back to one . Add comment to macb driver for PLL hardware quirk . Add reviewed-by to patch [6/7] . Add 'gpio-poweroff' node for upcoming opensbi integration - V2 . Rebase to unleashed rename patch . remove unnessaary fu540 changes . split ram driver patch into 2 to keep 'git mv' info . use a shorter name for unmatched support . Remove redundant&incorrect temperature-sensor in DT . Remove unnecessary USB EHCI & OHCI from defconfig . Revised fu740 doc . Fixed year of copyright . Add reviewed-by received in v1 patch David Abdurachmanov (1): drivers: net: macb: add fu740 support Green Wan (6): riscv: dts: add fu740 support riscv: cpu: fu740: Add support for cpu fu740 drivers: clk: add fu740 support drivers: ram: sifive: rename fu540_ddr and add fu740 support drivers: pci: add pcie support for fu740 board: sifive: add HiFive Unmatched board support arch/riscv/Kconfig | 5 + arch/riscv/cpu/fu740/Kconfig | 37 + arch/riscv/cpu/fu740/Makefile | 12 + arch/riscv/cpu/fu740/cache.c | 55 + arch/riscv/cpu/fu740/cpu.c | 22 + arch/riscv/cpu/fu740/dram.c | 38 + arch/riscv/cpu/fu740/spl.c | 23 + arch/riscv/dts/Makefile | 1 + arch/riscv/dts/fu740-c000-u-boot.dtsi | 105 ++ arch/riscv/dts/fu740-c000.dtsi | 329 ++++ .../dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 +++++++++++++++++ .../dts/hifive-unmatched-a00-u-boot.dtsi | 40 + arch/riscv/dts/hifive-unmatched-a00.dts | 259 +++ arch/riscv/include/asm/arch-fu740/cache.h | 14 + arch/riscv/include/asm/arch-fu740/clk.h | 14 + arch/riscv/include/asm/arch-fu740/gpio.h | 38 + arch/riscv/include/asm/arch-fu740/reset.h | 13 + arch/riscv/include/asm/arch-fu740/spl.h | 14 + arch/riscv/lib/sifive_clint.c | 1 - board/sifive/unmatched/Kconfig | 50 + board/sifive/unmatched/MAINTAINERS | 9 + board/sifive/unmatched/Makefile | 9 + board/sifive/unmatched/spl.c | 85 + board/sifive/unmatched/unmatched.c | 24 + common/spl/Kconfig | 4 +- configs/sifive_unmatched_defconfig | 53 + doc/board/sifive/index.rst | 1 + doc/board/sifive/unmatched.rst | 536 ++++++ drivers/clk/sifive/Kconfig | 8 +- drivers/clk/sifive/Makefile | 4 +- drivers/clk/sifive/fu540-prci.c | 769 +-------- drivers/clk/sifive/fu540-prci.h | 22 + drivers/clk/sifive/fu740-prci.c | 158 ++ drivers/clk/sifive/fu740-prci.h | 22 + drivers/clk/sifive/sifive-prci.c | 733 ++++++++ drivers/clk/sifive/sifive-prci.h | 323 ++++ drivers/net/macb.c | 13 +- drivers/pci/Kconfig | 9 + drivers/pci/Makefile | 1 + drivers/pci/pcie_sifive.c | 797 +++++++++ drivers/pci/pcie_sifive.h | 374 +++++ drivers/ram/sifive/Kconfig | 8 +- drivers/ram/sifive/Makefile | 2 +- .../ram/sifive/{fu540_ddr.c => sifive_ddr.c} | 90 +- drivers/reset/Kconfig | 2 +- include/configs/sifive-unmatched.h | 85 + include/dt-bindings/clock/sifive-fu740-prci.h | 25 + include/dt-bindings/reset/sifive-fu740-prci.h | 19 + 48 files changed, 5936 insertions(+), 808 deletions(-) create mode 100644 arch/riscv/cpu/fu740/Kconfig create mode 100644 arch/riscv/cpu/fu740/Makefile create mode 100644 arch/riscv/cpu/fu740/cache.c create mode 100644 arch/riscv/cpu/fu740/cpu.c create mode 100644 arch/riscv/cpu/fu740/dram.c create mode 100644 arch/riscv/cpu/fu740/spl.c create mode 100644 arch/riscv/dts/fu740-c000-u-boot.dtsi create mode 100644 arch/riscv/dts/fu740-c000.dtsi create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h create mode 100644 arch/riscv/include/asm/arch-fu740/spl.h create mode 100644 board/sifive/unmatched/Kconfig create mode 100644 board/sifive/unmatched/MAINTAINERS create mode 100644 board/sifive/unmatched/Makefile create mode 100644 board/sifive/unmatched/spl.c create mode 100644 board/sifive/unmatched/unmatched.c create mode 100644 configs/sifive_unmatched_defconfig create mode 100644 doc/board/sifive/unmatched.rst create mode 100644 drivers/clk/sifive/fu540-prci.h create mode 100644 drivers/clk/sifive/fu740-prci.c create mode 100644 drivers/clk/sifive/fu740-prci.h create mode 100644 drivers/clk/sifive/sifive-prci.c create mode 100644 drivers/clk/sifive/sifive-prci.h create mode 100644 drivers/pci/pcie_sifive.c create mode 100644 drivers/pci/pcie_sifive.h rename drivers/ram/sifive/{fu540_ddr.c => sifive_ddr.c} (81%) create mode 100644 include/configs/sifive-unmatched.h create mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h create mode 100644 include/dt-bindings/reset/sifive-fu740-prci.h -- 2.31.0

3 13

[PATCH v2 02/23] phy: marvell: rename comphy related definitions to COMPHY_XX
by Stefan Roese 08 Apr '21

08 Apr '21

From: Igal Liberman <igall(a)marvell.com> Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions. This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX This improves readability, no functional change. Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by: Igal Liberman <igall(a)marvell.com> Signed-off-by: Konstantin Porotchkin <kostap(a)marvell.com> Cc: Pali Rohár <pali(a)kernel.org> Cc: Marek Behun <marek.behun(a)nic.cz> Cc: Konstantin Porotchkin <kostap(a)marvell.com> --- v2: - 3720-db & 3720-espressobin: Fix PHY0 & PHY1 to use USB on PHY0 and PEX on PHY1 arch/arm/dts/armada-3720-db.dts | 8 +- arch/arm/dts/armada-3720-espressobin.dts | 12 +- arch/arm/dts/armada-3720-turris-mox.dts | 12 +- arch/arm/dts/armada-3720-uDPU.dts | 23 ++-- arch/arm/dts/armada-7040-db-nand.dts | 24 ++-- arch/arm/dts/armada-7040-db.dts | 22 ++-- arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 30 ++--- arch/arm/dts/armada-8040-db.dts | 24 ++-- arch/arm/dts/armada-8040-mcbin.dts | 27 +++-- arch/arm/dts/armada-8040-puzzle-m801.dts | 32 ++--- arch/arm/dts/cn9130-crb-A.dts | 16 +-- arch/arm/dts/cn9130-crb-B.dts | 16 +-- board/CZ.NIC/turris_mox/turris_mox.c | 8 +- drivers/phy/marvell/comphy_a3700.c | 70 +++++------ drivers/phy/marvell/comphy_core.c | 14 +-- drivers/phy/marvell/comphy_cp110.c | 124 +++++++++++--------- drivers/phy/marvell/comphy_mux.c | 10 +- include/dt-bindings/comphy/comphy_data.h | 90 +++++++------- 18 files changed, 288 insertions(+), 274 deletions(-) diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts index 1b1b66b94de6..42e7ddd25c55 100644 --- a/arch/arm/dts/armada-3720-db.dts +++ b/arch/arm/dts/armada-3720-db.dts @@ -70,13 +70,13 @@ &comphy { phy0 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_2_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_2_5G>; }; }; diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts index 96a4b3d95b88..d86d8f0b63cf 100644 --- a/arch/arm/dts/armada-3720-espressobin.dts +++ b/arch/arm/dts/armada-3720-espressobin.dts @@ -83,18 +83,18 @@ &comphy { max-lanes = <3>; phy0 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_2_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_2_5G>; }; phy2 { - phy-type = <PHY_TYPE_SATA0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA0>; + phy-speed = <COMPHY_SPEED_5G>; }; }; diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index 974270cc8c68..8e0ebf508d44 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -73,18 +73,18 @@ &comphy { max-lanes = <3>; phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_3_125G>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX0>; + phy-speed = <COMPHY_SPEED_5G>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; }; diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts index 7f4b8222f4af..4b30f3cea8c7 100644 --- a/arch/arm/dts/armada-3720-uDPU.dts +++ b/arch/arm/dts/armada-3720-uDPU.dts @@ -108,18 +108,19 @@ &comphy { phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; + }; + + phy1 { + phy-type = <COMPHY_TYPE_SGMII0>; + phy-speed = <COMPHY_SPEED_1_25G>; + }; + + phy2 { + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; }; - phy1 { - phy-type = <PHY_TYPE_SGMII0>; - phy-speed = <PHY_SPEED_3_125G>; - }; - - phy2 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; - }; }; &eth0 { diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts index f249c71f6561..ccf470b317f1 100644 --- a/arch/arm/dts/armada-7040-db-nand.dts +++ b/arch/arm/dts/armada-7040-db-nand.dts @@ -129,33 +129,33 @@ &cp0_comphy { phy0 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; phy2 { - phy-type = <PHY_TYPE_SGMII0>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII0>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-speed = <COMPHY_SPEED_5G>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX2>; + phy-speed = <COMPHY_SPEED_5G>; }; }; diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index 6037f12f0e9f..f475fb361071 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -122,32 +122,32 @@ &cp0_comphy { phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; + phy-speed = <COMPHY_SPEED_5G>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-speed = <COMPHY_SPEED_5G>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; + phy-speed = <COMPHY_SPEED_5G>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; - phy-speed = <PHY_SPEED_5G>; + phy-type = <COMPHY_TYPE_PEX2>; + phy-speed = <COMPHY_SPEED_5G>; }; }; diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index 86df6ac0b202..ce5832c2fbd7 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -160,22 +160,22 @@ * Lane 5: Not connected */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy3 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; }; phy5 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; }; @@ -272,25 +272,25 @@ * Lane 5: SGMII2 - Connected to Topaz switch */ phy0 { - phy-type = <PHY_TYPE_SATA1>; - phy-invert = <PHY_POLARITY_RXD_INVERT>; + phy-type = <COMPHY_TYPE_SATA1>; + phy-invert = <COMPHY_POLARITY_RXD_INVERT>; }; phy1 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_UNCONNECTED>; + phy-type = <COMPHY_TYPE_UNCONNECTED>; }; phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; }; diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index a2b7c992a406..1edfaab682eb 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -89,22 +89,22 @@ * Lane 5: PCIe2 (x1) */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_USB3_HOST1>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; + phy-type = <COMPHY_TYPE_PEX2>; }; }; @@ -188,22 +188,22 @@ * Lane 5: PCIe2 (x1) */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_PEX1>; + phy-type = <COMPHY_TYPE_PEX1>; }; phy5 { - phy-type = <PHY_TYPE_PEX2>; + phy-type = <COMPHY_TYPE_PEX2>; }; }; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index b0a36e328bc9..98a582df26fe 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -171,22 +171,22 @@ * Lane 5: SATA1 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy2 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy3 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; }; @@ -286,22 +286,23 @@ * Lane 5: SGMII3 */ phy0 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy1 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SGMII3>; + phy-type = <COMPHY_TYPE_SGMII3>; + phy-speed = <COMPHY_SPEED_3_125G>; }; }; diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts index ff46ce50cbc7..0becc4ff0d34 100644 --- a/arch/arm/dts/armada-8040-puzzle-m801.dts +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -220,24 +220,24 @@ * Lane 5: SATA1 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy2 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SATA1>; + phy-type = <COMPHY_TYPE_SATA1>; }; }; @@ -367,23 +367,23 @@ * Lane 5: SGMII2 */ phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy2 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy3 { - phy-type = <PHY_TYPE_SGMII1>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII1>; + phy-speed = <COMPHY_SPEED_1_25G>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; + phy-type = <COMPHY_TYPE_SFI>; }; phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_1_25G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_1_25G>; }; }; diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts index fa21ef314cba..5c5e0fb2eb1e 100644 --- a/arch/arm/dts/cn9130-crb-A.dts +++ b/arch/arm/dts/cn9130-crb-A.dts @@ -15,29 +15,29 @@ &cp0_comphy { phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy2 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy3 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; - phy-speed = <PHY_SPEED_10_3125G>; + phy-type = <COMPHY_TYPE_SFI>; + phy-speed = <COMPHY_SPEED_10_3125G>; }; phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; }; diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts index 7cb587ada826..6041084a2c87 100644 --- a/arch/arm/dts/cn9130-crb-B.dts +++ b/arch/arm/dts/cn9130-crb-B.dts @@ -15,29 +15,29 @@ &cp0_comphy { phy0 { - phy-type = <PHY_TYPE_PEX0>; + phy-type = <COMPHY_TYPE_PEX0>; }; phy1 { - phy-type = <PHY_TYPE_USB3_HOST0>; + phy-type = <COMPHY_TYPE_USB3_HOST0>; }; phy2 { - phy-type = <PHY_TYPE_SATA0>; + phy-type = <COMPHY_TYPE_SATA0>; }; phy3 { - phy-type = <PHY_TYPE_USB3_HOST1>; + phy-type = <COMPHY_TYPE_USB3_HOST1>; }; phy4 { - phy-type = <PHY_TYPE_SFI>; - phy-speed = <PHY_SPEED_10_3125G>; + phy-type = <COMPHY_TYPE_SFI>; + phy-speed = <COMPHY_SPEED_10_3125G>; }; phy5 { - phy-type = <PHY_TYPE_SGMII2>; - phy-speed = <PHY_SPEED_3_125G>; + phy-type = <COMPHY_TYPE_SGMII2>; + phy-speed = <COMPHY_SPEED_3_125G>; }; }; diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 486680a49e88..15cbf92550e6 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -216,13 +216,13 @@ int comphy_update_map(struct comphy_map *serdes_map, int count) if (sfpindex >= 0 && swindex >= 0) { if (sfpindex < swindex) - serdes_map[0].speed = PHY_SPEED_1_25G; + serdes_map[0].speed = COMPHY_SPEED_1_25G; else - serdes_map[0].speed = PHY_SPEED_3_125G; + serdes_map[0].speed = COMPHY_SPEED_3_125G; } else if (sfpindex >= 0) { - serdes_map[0].speed = PHY_SPEED_1_25G; + serdes_map[0].speed = COMPHY_SPEED_1_25G; } else if (swindex >= 0) { - serdes_map[0].speed = PHY_SPEED_3_125G; + serdes_map[0].speed = COMPHY_SPEED_3_125G; } return 0; diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 12523d18a805..06822d1d12e0 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -17,33 +17,33 @@ DECLARE_GLOBAL_DATA_PTR; struct comphy_mux_data a3700_comphy_mux_data[] = { -/* Lane 0 */ + /* Lane 0 */ { 4, { - { PHY_TYPE_UNCONNECTED, 0x0 }, - { PHY_TYPE_SGMII1, 0x0 }, - { PHY_TYPE_USB3_HOST0, 0x1 }, - { PHY_TYPE_USB3_DEVICE, 0x1 } + { COMPHY_TYPE_UNCONNECTED, 0x0 }, + { COMPHY_TYPE_SGMII1, 0x0 }, + { COMPHY_TYPE_USB3_HOST0, 0x1 }, + { COMPHY_TYPE_USB3_DEVICE, 0x1 } } }, -/* Lane 1 */ + /* Lane 1 */ { 3, { - { PHY_TYPE_UNCONNECTED, 0x0}, - { PHY_TYPE_SGMII0, 0x0}, - { PHY_TYPE_PEX0, 0x1} + { COMPHY_TYPE_UNCONNECTED, 0x0}, + { COMPHY_TYPE_SGMII0, 0x0}, + { COMPHY_TYPE_PEX0, 0x1} } }, -/* Lane 2 */ + /* Lane 2 */ { 4, { - { PHY_TYPE_UNCONNECTED, 0x0}, - { PHY_TYPE_SATA0, 0x0}, - { PHY_TYPE_USB3_HOST0, 0x1}, - { PHY_TYPE_USB3_DEVICE, 0x1} + { COMPHY_TYPE_UNCONNECTED, 0x0}, + { COMPHY_TYPE_SATA0, 0x0}, + { COMPHY_TYPE_USB3_HOST0, 0x1}, + { COMPHY_TYPE_USB3_DEVICE, 0x1} } }, }; @@ -228,10 +228,10 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) /* * 10. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); /* @@ -284,10 +284,10 @@ static int comphy_sata_power_up(u32 invert) /* * 0. Check the Polarity invert bits */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) data |= bs_txd_inv; - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) data |= bs_rxd_inv; reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv); @@ -465,10 +465,10 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) /* * 9. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane); - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane); /* @@ -513,7 +513,7 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) * Set Soft ID for Host mode (Device mode works with Hard ID * detection) */ - if (type == PHY_TYPE_USB3_HOST0) { + if (type == COMPHY_TYPE_USB3_HOST0) { /* * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1) * clear BIT1: set SOFT_ID = Host @@ -685,8 +685,8 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed) * comparison to 3.125 Gbps values. These register values are * stored in "sgmii_phy_init_fix" array. */ - if ((speed != PHY_SPEED_1_25G) && - (sgmii_phy_init_fix[fix_idx].addr == addr)) { + if (speed != COMPHY_SPEED_1_25G && + sgmii_phy_init_fix[fix_idx].addr == addr) { /* Use new value */ val = sgmii_phy_init_fix[fix_idx].value; if (fix_idx < fix_arr_sz) @@ -737,13 +737,13 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide * COMPHY bit rate */ - if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */ + if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */ reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x8 << rf_gen_rx_sel_shift) | (0x8 << rf_gen_tx_sel_shift), rf_gen_rx_select | rf_gen_tx_select); - } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */ + } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */ reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x6 << rf_gen_rx_sel_shift) | (0x6 << rf_gen_tx_sel_shift), @@ -819,7 +819,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * registers are OK. */ debug("Running C-DPI phy init %s mode\n", - speed == PHY_SPEED_3_125G ? "2G5" : "1G"); + speed == COMPHY_SPEED_3_125G ? "2G5" : "1G"); if (get_ref_clk() == 40) comphy_sgmii_phy_init(lane, speed); @@ -837,10 +837,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) /* * 18. Check the PHY Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0); - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0); /* @@ -976,30 +976,30 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, comphy_map->type, comphy_map->invert); switch (comphy_map->type) { - case PHY_TYPE_UNCONNECTED: + case COMPHY_TYPE_UNCONNECTED: continue; break; - case PHY_TYPE_PEX0: + case COMPHY_TYPE_PEX0: ret = comphy_pcie_power_up(comphy_map->speed, comphy_map->invert); break; - case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_DEVICE: + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_DEVICE: ret = comphy_usb3_power_up(lane, comphy_map->type, comphy_map->speed, comphy_map->invert); break; - case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: ret = comphy_sgmii_power_up(lane, comphy_map->speed, comphy_map->invert); break; - case PHY_TYPE_SATA0: + case COMPHY_TYPE_SATA0: ret = comphy_sata_power_up(comphy_map->invert); break; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index cffceb1395bb..f1f061d7c116 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -29,7 +29,7 @@ static const char *get_speed_string(u32 speed) "6.25 Gbps", "10.31 Gbps" }; - if (speed < 0 || speed > PHY_SPEED_MAX) + if (speed < 0 || speed > COMPHY_SPEED_MAX) return "invalid"; return speed_strings[speed]; @@ -46,7 +46,7 @@ static const char *get_type_string(u32 type) "RXAUI0", "RXAUI1", "SFI", "IGNORE" }; - if (type < 0 || type > PHY_TYPE_MAX) + if (type < 0 || type > COMPHY_TYPE_MAX) return "invalid"; return type_strings[type]; @@ -59,7 +59,7 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg, for (lane = 0; lane < chip_cfg->comphy_lanes_count; lane++, comphy_map_data++) { - if (comphy_map_data->speed == PHY_SPEED_INVALID) { + if (comphy_map_data->speed == COMPHY_SPEED_INVALID) { printf("Comphy-%d: %-13s\n", lane, get_type_string(comphy_map_data->type)); } else { @@ -136,16 +136,16 @@ static int comphy_probe(struct udevice *dev) continue; comphy_map_data[lane].speed = fdtdec_get_int( - blob, subnode, "phy-speed", PHY_TYPE_INVALID); + blob, subnode, "phy-speed", COMPHY_TYPE_INVALID); comphy_map_data[lane].type = fdtdec_get_int( - blob, subnode, "phy-type", PHY_SPEED_INVALID); + blob, subnode, "phy-type", COMPHY_SPEED_INVALID); comphy_map_data[lane].invert = fdtdec_get_int( - blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT); + blob, subnode, "phy-invert", COMPHY_POLARITY_NO_INVERT); comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode, "clk-src"); comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode, "end_point"); - if (comphy_map_data[lane].type == PHY_TYPE_INVALID) { + if (comphy_map_data[lane].type == COMPHY_TYPE_INVALID) { printf("no phy type for lane %d, setting lane as unconnected\n", lane + 1); } diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index a323de7c76d0..e4ab90121c74 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -74,35 +74,47 @@ struct utmi_phy_data { * Eth_port_0 that include (SGMII0, RXAUI0, SFI) */ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ - {PHY_TYPE_SATA1, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ - {PHY_TYPE_SATA0, 0x4} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ - {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, - {PHY_TYPE_SATA0, 0x4} } }, - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ - {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, - {PHY_TYPE_SGMII1, 0x1} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ - {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, + /* Lane 0 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, + {COMPHY_TYPE_SATA1, 0x4} } }, + /* Lane 1 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, + {COMPHY_TYPE_SATA0, 0x4} } }, + /* Lane 2 */ + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, + {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1}, + {COMPHY_TYPE_SATA0, 0x4} } }, + /* Lane 3 */ + {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, + {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } }, + /* Lane 4 */ + {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, + {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2}, + {COMPHY_TYPE_SGMII1, 0x1} } }, + /* Lane 5 */ + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, + {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } }, }; struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ - {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, - {PHY_TYPE_PEX0, 0x4} } }, - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ - {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ - {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ - {PHY_TYPE_USB3_HOST1, 0x1}, - {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ + /* Lane 0 */ + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 1 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_USB3_DEVICE, 0x2}, + {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 2 */ + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 3 */ + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST1, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 4 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST1, 0x1}, + {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PEX1, 0x4} } }, + /* Lane 5 */ + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX2, 0x4} } }, }; static u32 polling_with_timeout(void __iomem *addr, u32 val, @@ -868,9 +880,9 @@ static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); /* Fix the type after check the PHY and PIPE configuration */ for (lane = 0; lane < comphy_max_count; lane++) { - if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && - (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) - serdes_map[lane].type = PHY_TYPE_UNCONNECTED; + if ((comphy_map_pipe_data[lane].type == COMPHY_TYPE_UNCONNECTED) && + (comphy_map_phy_data[lane].type == COMPHY_TYPE_UNCONNECTED)) + serdes_map[lane].type = COMPHY_TYPE_UNCONNECTED; } } @@ -895,7 +907,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, /* Check if the first 4 lanes configured as By-4 */ for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; lane++, ptr_comphy_map++) { - if (ptr_comphy_map->type != PHY_TYPE_PEX0) + if (ptr_comphy_map->type != COMPHY_TYPE_PEX0) break; pcie_width++; } @@ -912,14 +924,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, pcie_width = 1; } switch (ptr_comphy_map->type) { - case PHY_TYPE_UNCONNECTED: - case PHY_TYPE_IGNORE: + case COMPHY_TYPE_UNCONNECTED: + case COMPHY_TYPE_IGNORE: continue; break; - case PHY_TYPE_PEX0: - case PHY_TYPE_PEX1: - case PHY_TYPE_PEX2: - case PHY_TYPE_PEX3: + case COMPHY_TYPE_PEX0: + case COMPHY_TYPE_PEX1: + case COMPHY_TYPE_PEX2: + case COMPHY_TYPE_PEX3: mode = COMPHY_FW_PCIE_FORMAT(pcie_width, ptr_comphy_map->clk_src, COMPHY_PCIE_MODE, @@ -928,30 +940,30 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SATA0: - case PHY_TYPE_SATA1: - case PHY_TYPE_SATA2: - case PHY_TYPE_SATA3: + case COMPHY_TYPE_SATA0: + case COMPHY_TYPE_SATA1: + case COMPHY_TYPE_SATA2: + case COMPHY_TYPE_SATA3: mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); ret = comphy_sata_power_up(lane, hpipe_base_addr, comphy_base_addr, ptr_chip_cfg->cp_index, mode); break; - case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_HOST1: - case PHY_TYPE_USB3_DEVICE: + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_HOST1: + case COMPHY_TYPE_USB3_DEVICE: ret = comphy_usb3_power_up(lane, hpipe_base_addr, comphy_base_addr); break; - case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: - if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: + if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: "); debug("SGMII PHY speed in lane %d is invalid,", lane); debug(" set PHY speed to 1.25G\n"); - ptr_comphy_map->speed = PHY_SPEED_1_25G; + ptr_comphy_map->speed = COMPHY_SPEED_1_25G; } /* @@ -965,12 +977,12 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SGMII2: - case PHY_TYPE_SGMII3: - if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { + case COMPHY_TYPE_SGMII2: + case COMPHY_TYPE_SGMII3: + if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", lane); - ptr_comphy_map->speed = PHY_SPEED_1_25G; + ptr_comphy_map->speed = COMPHY_SPEED_1_25G; } mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, @@ -980,7 +992,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SFI: + case COMPHY_TYPE_SFI: mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, COMPHY_UNIT_ID0, ptr_comphy_map->speed); @@ -988,8 +1000,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_RXAUI0: - case PHY_TYPE_RXAUI1: + case COMPHY_TYPE_RXAUI0: + case COMPHY_TYPE_RXAUI1: ret = comphy_rxauii_power_up(lane, hpipe_base_addr, comphy_base_addr); break; @@ -1001,9 +1013,9 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, if (ret == 0) { /* * If interface wans't initialized, set the lane to - * PHY_TYPE_UNCONNECTED state. + * COMPHY_TYPE_UNCONNECTED state. */ - ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; + ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED; pr_err("PLL is not locked - Failed to initialize lane %d\n", lane); } diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index 98327557a899..aaef736b75dd 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -15,7 +15,7 @@ * description: this function passes over the COMPHY lanes and check if the type * is valid for specific lane. If the type is not valid, * the function update the struct and set the type of the lane as - * PHY_TYPE_UNCONNECTED + * COMPHY_TYPE_UNCONNECTED */ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, struct comphy_map *comphy_map_data, int comphy_max_lanes) @@ -28,7 +28,7 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { /* Don't check ignored COMPHYs */ - if (comphy_map_data->type == PHY_TYPE_IGNORE) + if (comphy_map_data->type == COMPHY_TYPE_IGNORE) continue; mux_opt = mux_data->mux_values; @@ -43,8 +43,8 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, debug("lane number %d, had invalid type %d\n", lane, comphy_map_data->type); debug("set lane %d as type %d\n", lane, - PHY_TYPE_UNCONNECTED); - comphy_map_data->type = PHY_TYPE_UNCONNECTED; + COMPHY_TYPE_UNCONNECTED); + comphy_map_data->type = COMPHY_TYPE_UNCONNECTED; } else { debug("lane number %d, has type %d\n", lane, comphy_map_data->type); @@ -88,7 +88,7 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { - if (comphy_map_data->type == PHY_TYPE_IGNORE) + if (comphy_map_data->type == COMPHY_TYPE_IGNORE) continue; /* diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 08544fa758bf..7d62dcf7fa51 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -6,53 +6,53 @@ #ifndef _COMPHY_DATA_H_ #define _COMPHY_DATA_H_ -#define PHY_SPEED_1_25G 0 -#define PHY_SPEED_1_5G 1 -#define PHY_SPEED_2_5G 2 -#define PHY_SPEED_3G 3 -#define PHY_SPEED_3_125G 4 -#define PHY_SPEED_5G 5 -#define PHY_SPEED_5_15625G 6 -#define PHY_SPEED_6G 7 -#define PHY_SPEED_6_25G 8 -#define PHY_SPEED_10_3125G 9 -#define PHY_SPEED_MAX 10 -#define PHY_SPEED_INVALID 0xff +#define COMPHY_SPEED_1_25G 0 +#define COMPHY_SPEED_1_5G 1 +#define COMPHY_SPEED_2_5G 2 +#define COMPHY_SPEED_3G 3 +#define COMPHY_SPEED_3_125G 4 +#define COMPHY_SPEED_5G 5 +#define COMPHY_SPEED_5_15625G 6 +#define COMPHY_SPEED_6G 7 +#define COMPHY_SPEED_6_25G 8 +#define COMPHY_SPEED_10_3125G 9 +#define COMPHY_SPEED_MAX 10 +#define COMPHY_SPEED_INVALID 0xff -#define PHY_TYPE_UNCONNECTED 0 -#define PHY_TYPE_PEX0 1 -#define PHY_TYPE_PEX1 2 -#define PHY_TYPE_PEX2 3 -#define PHY_TYPE_PEX3 4 -#define PHY_TYPE_SATA0 5 -#define PHY_TYPE_SATA1 6 -#define PHY_TYPE_SATA2 7 -#define PHY_TYPE_SATA3 8 -#define PHY_TYPE_SGMII0 9 -#define PHY_TYPE_SGMII1 10 -#define PHY_TYPE_SGMII2 11 -#define PHY_TYPE_SGMII3 12 -#define PHY_TYPE_QSGMII 13 -#define PHY_TYPE_USB3 14 -#define PHY_TYPE_USB3_HOST0 15 -#define PHY_TYPE_USB3_HOST1 16 -#define PHY_TYPE_USB3_DEVICE 17 -#define PHY_TYPE_XAUI0 18 -#define PHY_TYPE_XAUI1 19 -#define PHY_TYPE_XAUI2 20 -#define PHY_TYPE_XAUI3 21 -#define PHY_TYPE_RXAUI0 22 -#define PHY_TYPE_RXAUI1 23 -#define PHY_TYPE_SFI 24 -#define PHY_TYPE_IGNORE 25 -#define PHY_TYPE_MAX 26 -#define PHY_TYPE_INVALID 0xff +#define COMPHY_TYPE_UNCONNECTED 0 +#define COMPHY_TYPE_PEX0 1 +#define COMPHY_TYPE_PEX1 2 +#define COMPHY_TYPE_PEX2 3 +#define COMPHY_TYPE_PEX3 4 +#define COMPHY_TYPE_SATA0 5 +#define COMPHY_TYPE_SATA1 6 +#define COMPHY_TYPE_SATA2 7 +#define COMPHY_TYPE_SATA3 8 +#define COMPHY_TYPE_SGMII0 9 +#define COMPHY_TYPE_SGMII1 10 +#define COMPHY_TYPE_SGMII2 11 +#define COMPHY_TYPE_SGMII3 12 +#define COMPHY_TYPE_QSGMII 13 +#define COMPHY_TYPE_USB3 14 +#define COMPHY_TYPE_USB3_HOST0 15 +#define COMPHY_TYPE_USB3_HOST1 16 +#define COMPHY_TYPE_USB3_DEVICE 17 +#define COMPHY_TYPE_XAUI0 18 +#define COMPHY_TYPE_XAUI1 19 +#define COMPHY_TYPE_XAUI2 20 +#define COMPHY_TYPE_XAUI3 21 +#define COMPHY_TYPE_RXAUI0 22 +#define COMPHY_TYPE_RXAUI1 23 +#define COMPHY_TYPE_SFI 24 +#define COMPHY_TYPE_IGNORE 25 +#define COMPHY_TYPE_MAX 26 +#define COMPHY_TYPE_INVALID 0xff -#define PHY_POLARITY_NO_INVERT 0 -#define PHY_POLARITY_TXD_INVERT 1 -#define PHY_POLARITY_RXD_INVERT 2 -#define PHY_POLARITY_ALL_INVERT \ - (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT) +#define COMPHY_POLARITY_NO_INVERT 0 +#define COMPHY_POLARITY_TXD_INVERT 1 +#define COMPHY_POLARITY_RXD_INVERT 2 +#define COMPHY_POLARITY_ALL_INVERT \ + (COMPHY_POLARITY_TXD_INVERT | COMPHY_POLARITY_RXD_INVERT) #define UTMI_PHY_TO_USB3_HOST0 0 #define UTMI_PHY_TO_USB3_HOST1 1 -- 2.31.1

1 0

[PATCH] efi_loader: efi_esrt: Fix the build warning for 32 bit systems
by Sughosh Ganu 08 Apr '21

08 Apr '21

Fix the build warning when building for 32 bit systems by using the length modifier for size_t. lib/efi_loader/efi_esrt.c: In function ‘efi_esrt_populate’: include/efi_loader.h:126:8: warning: format ‘%ld’ expects argument of type ‘long int’, but argument 8 has type ‘size_t’ {aka ‘unsigned int’} [-Wformat=] Signed-off-by: Sughosh Ganu <sughosh.ganu(a)linaro.org> --- lib/efi_loader/efi_esrt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/efi_esrt.c b/lib/efi_loader/efi_esrt.c index 947bdb5e95..8815e56e15 100644 --- a/lib/efi_loader/efi_esrt.c +++ b/lib/efi_loader/efi_esrt.c @@ -341,7 +341,7 @@ efi_status_t efi_esrt_populate(void) return EFI_SUCCESS; } - EFI_PRINT("ESRT populate esrt from (%ld) available FMP handles\n", + EFI_PRINT("ESRT populate esrt from (%zd) available FMP handles\n", no_handles); /* -- 2.17.1

2 1

[PATCH] atcspi200: Add timeout mechanism in spi_xfer()
by Dylan Jhong 08 Apr '21

08 Apr '21

Adding timeout mechanism to avoid spi driver from stucking in the while loop in __atcspi200_spi_xfer(). Signed-off-by: Dylan Jhong <dylan(a)andestech.com> --- drivers/spi/atcspi200_spi.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c index 634cd56561..775b9ffc25 100644 --- a/drivers/spi/atcspi200_spi.c +++ b/drivers/spi/atcspi200_spi.c @@ -201,7 +201,7 @@ static int __atcspi200_spi_xfer(struct nds_spi_slave *ns, size_t cmd_len = ns->cmd_len; unsigned long data_len = bitlen / 8; int rf_cnt; - int ret = 0; + int ret = 0, timeout = 0; max_tran_len = ns->max_transfer_length; switch (flags) { @@ -243,11 +243,12 @@ static int __atcspi200_spi_xfer(struct nds_spi_slave *ns, ns->tran_len = tran_len; num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE); num_bytes = (tran_len) % CHUNK_SIZE; + timeout = SPI_TIMEOUT; if(num_bytes == 0) num_bytes = CHUNK_SIZE; __atcspi200_spi_start(ns); - while (num_blks) { + while (num_blks && (timeout--)) { event = in_le32(&ns->regs->status); if ((event & TXEPTY) && (data_out)) { __nspi_espi_tx(ns, dout); @@ -269,6 +270,11 @@ static int __atcspi200_spi_xfer(struct nds_spi_slave *ns, din = (unsigned char *)din + rx_bytes; } } + + if (!timeout) { + debug("spi_xfer: %s() timeout\n", __func__); + break; + } } data_len -= tran_len; -- 2.17.0

2 1

[PATCH] x86: mtrr: Fix function descriptions
by Wolfgang Wallner 08 Apr '21

08 Apr '21

Fix copy/paste errors in the descriptions of mtrr_close () and mtrr_set(). Signed-off-by: Wolfgang Wallner <wolfgang.wallner(a)br-automation.com> --- arch/x86/include/asm/mtrr.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 3a98aacdef..384672e93f 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -103,7 +103,7 @@ struct mtrr_info { void mtrr_open(struct mtrr_state *state, bool do_caches); /** - * mtrr_open() - Clean up after adjusting MTRRs, and enable them + * mtrr_close() - Clean up after adjusting MTRRs, and enable them * * This uses the structure containing information returned from mtrr_open(). * @@ -170,7 +170,7 @@ void mtrr_read_all(struct mtrr_info *info); int mtrr_set_valid(int cpu_select, int reg, bool valid); /** - * mtrr_set() - Set the valid flag for a selected MTRR and CPU(s) + * mtrr_set() - Set the base address and mask for a selected MTRR and CPU(s) * * @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...) * @reg: MTRR register to write (0-7) -- 2.30.2

3 3

[PATCH] dt-bindings: fsp: Fix Apollo Lake FSP-S devicetree bindings
by Wolfgang Wallner 08 Apr '21

08 Apr '21

An entry is missing in the FSP-S devicetree bindings, and as a result the description for the next few following entries is off by one line. Signed-off-by: Wolfgang Wallner <wolfgang.wallner(a)br-automation.com> --- .../fsp/fsp2/apollolake/fsp-s.txt | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt index b605ed0056..dc8e3251a3 100644 --- a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt +++ b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt @@ -258,19 +258,20 @@ Optional properties: - fsps,pcie-rp-clk-req-detect: CLKREQ# Detection - fsps,advanced-error-reportingt: Advanced Error Reporting - fsps,pme-interrupt: PME Interrupt -- fsps,fatal-error-report: URR -- fsps,no-fatal-error-report: FER -- fsps,correctable-error-report: NFER -- fsps,system-error-on-fatal-error: CER -- fsps,system-error-on-non-fatal-error: SEFE -- fsps,system-error-on-correctable-error: SENFE -- fsps,pcie-rp-speed: SECE -- fsps,physical-slot-number: PCIe Speed +- fsps,unsupported-request-report: URR +- fsps,fatal-error-report: FER +- fsps,no-fatal-error-report: NFER +- fsps,correctable-error-report: CER +- fsps,system-error-on-fatal-error: SEFE +- fsps,system-error-on-non-fatal-error: SENFE +- fsps,system-error-on-correctable-error: SECE +- fsps,pcie-rp-speed: PCIe Speed +- fsps,physical-slot-number: Physical Slot Number 0: Auto (default) 1: Gen1 2: Gen2 3: Gen3 -- fsps,pcie-rp-completion-timeout: Physical Slot Number +- fsps,pcie-rp-completion-timeout: CTO 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 (default) - fsps,enable-ptm: PTM Support - fsps,pcie-rp-aspm: ASPM -- 2.30.2

3 3

[NXP-IMX V2] please pull nxp-imx-2021-4-6
by Peng Fan (OSS) 08 Apr '21

08 Apr '21

Hi Stefano, Please pull nxp-imx-2021-4-6. This PR is based on Tom's master branch. If you need me rebase on imx/master, I could redo this PR. This is quite a large PR, since lots stuff in downstream tree. CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/7046 ------------------------------------------ convert to use binman for i.MX8MN/M/P EVK board i.MX8M caam/dek support hab update/fix for i.MX8M/7ULP env/distro cleanup for i.MX8M i.MX8M ddr script/driver update ------------------------------------------ Thanks, Peng. The following changes since commit 90eba245a66aa20589404ba537215faf2012c1a3: Merge branch 'next' (2021-04-05 11:29:57 -0400) are available in the Git repository at: https://github.com/MrVan/u-boot.git tags/nxp-imx-2021-4-6 for you to fetch changes up to cf0202c231815ed41e580f0b81e3abc7493671fc: doc: imx8mp-evk: update after using binman (2021-04-07 10:51:49 +0800) ---------------------------------------------------------------- Aymen Sghaier (6): crypto: caam: Add CAAM support to i.MX8M platforms crypto: caam: Fix build warnings pointer casting crypto: Add blob command support for i.MX8M platforms crypto: caam: Fix pointer size to 32bit for i.MX8M crypto: caam: Add secure memory vid 3 support crypto: caam: RNG4 TRNG errata Breno Lima (13): imx: imx7 Support for Manufacturing Protection imx: Avoid hardcoded output ring size register offset (ORSR) imx: Ensure CAAM clock is enabled prior getting out_jr_size imx: Avoid hardcoded Job Ring Max size imx: hab: Enable hab.c to authenticate additional images in open configuration imx: hab: Check if IVT header is HABv4 mx7ulp: hab: Add hab_status command for HABv4 M4 boot imx: hab: Fix build warnings in 32-bit targets crypto: fsl: blob: Flush dcache range for destination address mx6dq: hab: Fix chip version in hab.h code cmd: blob: Add IMX_HAB and CAAM supported SoCs as dependency cmd: blob: Instantiate RNG before running CMD_BLOB fsl_mfgprot: Fix typo in sign_mppubk() Clement Faure (2): imx8m: Add DEK blob encapsulation for imx8m imx8: Add DEK blob encapsulation Clement Le Marquis (1): imx: caam: new u-boot command to set PRIBLOB bitfield from CAAM SCFGR register to 0x3 Franck LENORMAND (3): crypto: caam: change JR running loop caam: enable support for iMX7ULP imx7ulp: Enable support for cmd blob Jacky Bai (1): imx8mn: Update the DDR4 timing script on imx8mn ddr4 evk Peng (1): imx8mn: evk: update MAINTAINERS Peng Fan (20): tools: imx image: fix write warning imx8mm/p: remove boot.cmd imx8mm_evk: add/cleanup variable for distro imx8mp_evk: add/cleanup variable for distro imx8mp_evk: spl: clean up including headers imx8mp_evk: Increase VDD_ARM to 0.95v Overdrive voltage power: pca9450: add a new parameter for power_pca9450_init imx8mn_evk: drop duplicated code imx8mn: Add LPDDR4 EVK board support imx8m: soc: update fuse path arch: mach-imx: imx8m: fix unique_id read error for imx8mp imx8m: add regs used by CAAM imx: HAB: Update hab codes to support ARM64 and i.MX8M imx8mm_evk: switch to use binman to pack images doc: imx8mm_evk: update doc after using binman imx8mn-ddr4-evk: switch to use binman imx8mn-evk: switch to use binman doc: imx8mn_evk: update doc after using binman imx8mp-evk: switch to use binman doc: imx8mp-evk: update after using binman Sherry Sun (1): imx8mp: ddr: Add inline ECC feature support Utkarsh Gupta (2): imx: HAB: Validate IVT before authenticating image imx: hab: Display All HAB events via hab_status command Ye Li (18): imx8mm_evk: Update to latest LPDDR4 script imx8mm_evk: Switch to new imx8mm evk board imx8mp_evk: Update LPDDR4 timing for new FW 202006 imx8mp_evk: Update LPDDR4 refresh time imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK imx8mn: Add support for 11x11 UltraLite part number imx8m: Update thermal and PMU kernel nodes for dual/single cores imx8m: ddr: Disable CA VREF Training for LPDDR4 iMX8MQ: Recognize the B2 revision misc: ocotp: Update OCOTP driver for iMX8MQ B2 imx8mq_evk: Applying default LPDDR4 script for B2 imx: hab: Add function to authenticate kernel image hab: Change calling to ROM API failsafe imx: HAB: Add support for iMX8MM iMX8M: Add support to enable CONFIG_IMX_HAB imx: cmd_dek: Enable DEK only for chips supporting CAAM crypto: caam: Add fsl caam driver crypto: fsl: refactor for 32 bit version CAAM support on ARM64 haidong.zheng (1): imx8mp: refine power on imx8mp board arch/arm/Kconfig | 6 + arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mm-evk-u-boot.dtsi | 117 ++++++++- arch/arm/dts/imx8mm-evk.dtsi | 127 +++++----- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 115 +++++++++ arch/arm/dts/imx8mn-evk-u-boot.dtsi | 128 ++++++++++ arch/arm/dts/imx8mn-evk.dts | 128 ++++++++++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 112 +++++++++ arch/arm/include/asm/arch-imx/cpu.h | 13 +- arch/arm/include/asm/arch-imx8/image.h | 11 + arch/arm/include/asm/arch-imx8m/clock.h | 1 + arch/arm/include/asm/arch-imx8m/imx-regs.h | 21 ++ arch/arm/include/asm/arch-mx7/crm_regs.h | 8 + arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 12 + arch/arm/include/asm/mach-imx/hab.h | 37 ++- arch/arm/include/asm/mach-imx/sys_proto.h | 6 +- arch/arm/mach-imx/Kconfig | 44 +++- arch/arm/mach-imx/Makefile | 3 + arch/arm/mach-imx/cmd_dek.c | 262 ++++++++++++++++++-- arch/arm/mach-imx/cmd_mfgprot.c | 150 ++++++++++++ arch/arm/mach-imx/cpu.c | 8 +- arch/arm/mach-imx/hab.c | 417 ++++++++++++++++++++++++++++---- arch/arm/mach-imx/imx8/Kconfig | 1 + arch/arm/mach-imx/imx8m/Kconfig | 11 + arch/arm/mach-imx/imx8m/clock_imx8mm.c | 8 + arch/arm/mach-imx/imx8m/clock_imx8mq.c | 7 + arch/arm/mach-imx/imx8m/soc.c | 183 ++++++++++++-- arch/arm/mach-imx/mx7ulp/Kconfig | 1 + arch/arm/mach-imx/priblob.c | 33 +++ board/freescale/imx8mm_evk/boot.cmd | 35 --- board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg | 9 + board/freescale/imx8mm_evk/lpddr4_timing.c | 692 +++++++++++++++++++++------------------------------- board/freescale/imx8mm_evk/spl.c | 33 +-- board/freescale/imx8mn_evk/Kconfig | 6 +- board/freescale/imx8mn_evk/MAINTAINERS | 3 +- board/freescale/imx8mn_evk/Makefile | 6 + board/freescale/imx8mn_evk/ddr4_timing.c | 1057 ++++++++++++++++++++++++++++++++++---------------------------------------------- board/freescale/imx8mn_evk/ddr4_timing_ld.c | 1057 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg | 10 + board/freescale/imx8mn_evk/lpddr4_timing.c | 1587 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/freescale/imx8mn_evk/lpddr4_timing_ld.c | 1440 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/freescale/imx8mn_evk/spl.c | 50 +++- board/freescale/imx8mp_evk/boot.cmd | 25 -- board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg | 10 + board/freescale/imx8mp_evk/lpddr4_timing.c | 372 +++++++++++++++++++++------- board/freescale/imx8mp_evk/spl.c | 38 +-- board/freescale/imx8mq_evk/spl.c | 2 +- board/phytec/phycore_imx8mp/spl.c | 2 +- cmd/Kconfig | 8 + cmd/Makefile | 1 + cmd/blob.c | 16 ++ cmd/cmd_fsl_caam.c | 88 +++++++ configs/imx8mm_evk_defconfig | 6 +- configs/imx8mn_ddr4_evk_defconfig | 4 +- configs/imx8mn_evk_defconfig | 93 +++++++ configs/imx8mp_evk_defconfig | 4 +- doc/board/freescale/imx8mm_evk.rst | 3 +- doc/board/freescale/imx8mn_evk.rst | 3 +- doc/board/freescale/imx8mp_evk.rst | 11 +- doc/imx/habv4/guides/mx6_mx7_secure_boot.txt | 25 ++ drivers/crypto/Makefile | 1 + drivers/crypto/fsl/Kconfig | 6 + drivers/crypto/fsl/Makefile | 4 +- drivers/crypto/fsl/desc.h | 49 ++-- drivers/crypto/fsl/desc_constr.h | 28 +-- drivers/crypto/fsl/fsl_blob.c | 6 + drivers/crypto/fsl/fsl_hash.c | 6 +- drivers/crypto/fsl/fsl_mfgprot.c | 160 ++++++++++++ drivers/crypto/fsl/jobdesc.c | 16 +- drivers/crypto/fsl/jr.c | 53 ++-- drivers/crypto/fsl/jr.h | 11 +- drivers/crypto/fsl/type.h | 16 ++ drivers/crypto/fsl_caam.c | 720 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/crypto/fsl_caam_internal.h | 230 ++++++++++++++++++ drivers/ddr/imx/imx8m/Kconfig | 8 + drivers/misc/mxc_ocotp.c | 2 +- drivers/power/pmic/pmic_pca9450.c | 4 +- include/configs/imx8mm_evk.h | 8 +- include/configs/imx8mp_evk.h | 8 +- include/fsl_caam.h | 24 ++ include/fsl_sec.h | 54 +++-- include/power/pca9450.h | 2 +- tools/imx8image.c | 2 +- tools/imx8mimage.c | 2 +- 84 files changed, 8602 insertions(+), 1485 deletions(-) create mode 100644 arch/arm/dts/imx8mn-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-evk.dts create mode 100644 arch/arm/mach-imx/cmd_mfgprot.c create mode 100644 arch/arm/mach-imx/priblob.c delete mode 100644 board/freescale/imx8mm_evk/boot.cmd create mode 100644 board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg create mode 100644 board/freescale/imx8mn_evk/ddr4_timing_ld.c create mode 100644 board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg create mode 100644 board/freescale/imx8mn_evk/lpddr4_timing.c create mode 100644 board/freescale/imx8mn_evk/lpddr4_timing_ld.c delete mode 100644 board/freescale/imx8mp_evk/boot.cmd create mode 100644 board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg mode change 100644 => 100755 board/freescale/imx8mp_evk/lpddr4_timing.c create mode 100644 cmd/cmd_fsl_caam.c create mode 100644 configs/imx8mn_evk_defconfig create mode 100644 drivers/crypto/fsl/fsl_mfgprot.c create mode 100644 drivers/crypto/fsl/type.h create mode 100644 drivers/crypto/fsl_caam.c create mode 100644 drivers/crypto/fsl_caam_internal.h create mode 100644 include/fsl_caam.h

2 1

[PATCH 1/1] Azure/GitLab: bump OpenSBI version to 0.9
by Heinrich Schuchardt 08 Apr '21

08 Apr '21

Version 0.9 of OpenSBI provides the system reset extension which allows us to reset and power off boards without board specific code. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- .azure-pipelines.yml | 8 ++++---- .gitlab-ci.yml | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index f358e468de..6254a458ed 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -304,12 +304,12 @@ jobs: grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.… | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.… | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.… | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.… | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi # the below corresponds to .gitlab-ci.yml "script" cd ${WORK_DIR} diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 64e341c262..22ec4929a0 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -21,12 +21,12 @@ stages: - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.… | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.… | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.8/opensbi-0.8-rv-bin.… | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.8-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.… | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi after_script: -- 2.30.2

3 2