This patch enables u-boot support for Openpiton SoC
of RISC-V architecture
Signed-off-by: Tianrui Wei <tianrui-wei(a)outlook.com>
Acked-by: Jonathan Balkind <jbalkind(a)ucsb.edu>
---
arch/riscv/Kconfig | 4 +
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/openpiton-riscv64.dts | 149 +++++++++++++++++++
board/openpiton/riscv/Kconfig | 42 ++++++
board/openpiton/riscv/MAINTAINERS | 6 +
board/openpiton/riscv/Makefile | 5 +
board/openpiton/riscv/openpiton-riscv.c | 39 +++++
configs/openpiton_riscv64_defconfig | 132 +++++++++++++++++
drivers/mmc/Kconfig | 6 +
drivers/mmc/Makefile | 1 +
drivers/mmc/piton_mmc.c | 182 ++++++++++++++++++++++++
include/configs/openpiton-riscv.h | 58 ++++++++
12 files changed, 625 insertions(+)
create mode 100644 arch/riscv/dts/openpiton-riscv64.dts
create mode 100644 board/openpiton/riscv/Kconfig
create mode 100644 board/openpiton/riscv/MAINTAINERS
create mode 100644 board/openpiton/riscv/Makefile
create mode 100644 board/openpiton/riscv/openpiton-riscv.c
create mode 100644 configs/openpiton_riscv64_defconfig
create mode 100644 drivers/mmc/piton_mmc.c
create mode 100644 include/configs/openpiton-riscv.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 30b05408..79f2b0b9 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -23,6 +23,9 @@ config TARGET_SIFIVE_FU540
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
+config TARGET_OPENPITON_RISCV
+ bool "Support RISC-V cores on OpenPiton SoC"
+
endchoice
config SYS_ICACHE_OFF
@@ -57,6 +60,7 @@ source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/fu540/Kconfig"
source "board/sipeed/maix/Kconfig"
+source "board/openpiton/riscv/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3a6f96c6..0eb8014b 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_OPENPITON_RISCV) += openpiton-riscv64.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/openpiton-riscv64.dts b/arch/riscv/dts/openpiton-riscv64.dts
new file mode 100644
index 00000000..91c000c3
--- /dev/null
+++ b/arch/riscv/dts/openpiton-riscv64.dts
@@ -0,0 +1,149 @@
+// This dts is for a dual core instance of OpenPiton+Ariane built
+// to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files
+// are automatically generated by the OpenPiton build system and
+// this configuration may not be what you need if your configuration
+// is different from the below.
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ compatible = "openpiton,ariane";
+
+ chosen {
+ u-boot,dm-pre-reloc;
+ bootargs = "debug loglevel=9";
+ stdout-path = "uart0:115200";
+ };
+
+ aliases {
+ u-boot,dm-pre-reloc;
+ console = &uart0;
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+ timebase-frequency = <520835>;
+
+ CPU0: cpu@0 {
+ clock-frequency = <66667000>;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ reg = <0>;
+ status = "okay";
+ compatible = "eth, ariane", "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ tlb-split;
+ // HLIC - hart local interrupt controller
+ CPU0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+
+ CPU1: cpu@1 {
+ clock-frequency = <66667000>;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ reg = <1>;
+ status = "okay";
+ compatible = "eth, ariane", "riscv";
+ riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
+ tlb-split;
+ // HLIC - hart local interrupt controller
+ CPU1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+
+ };
+
+ memory@80000000 {
+ u-boot,dm-pre-reloc;
+ device_type = "memory";
+ reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >;
+ };
+
+ uart0: uart@fff0c2c000 {
+ u-boot,dm-pre-reloc;
+ compatible = "ns16550";
+ reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >;
+ clock-frequency = <66667000>;
+ current-speed = <115200>;
+ interrupt-parent = <&PLIC0>;
+ interrupts = <1>;
+ reg-shift = <0>; // regs are spaced on 8 bit boundary (modified from Xilinx UART16550 to be ns16550 compatible)
+ };
+
+ eth: ethernet@fff0d00000 {
+ compatible = "xlnx,xps-ethernetlite-1.00.a";
+ device_type = "network";
+ reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >;
+ interrupt-parent = <&PLIC0>;
+ interrupts = <2>;
+ local-mac-address = [ 00 18 3E 02 E3 E5 ];
+ phy-handle = <&phy0>;
+ xlnx,duplex = <0x1>;
+ xlnx,include-global-buffers = <0x1>;
+ xlnx,include-internal-loopback = <0x0>;
+ xlnx,include-mdio = <0x1>;
+ xlnx,rx-ping-pong = <0x1>;
+ xlnx,s-axi-id-width = <0x1>;
+ xlnx,tx-ping-pong = <0x1>;
+ xlnx,use-internal = <0x0>;
+ axi_ethernetlite_0_mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: phy@1 {
+ compatible = "ethernet-phy-id001C.C915";
+ device_type = "ethernet-phy";
+ reg = <1>;
+ };
+ };
+ };
+
+ debug-controller@fff1000000 {
+ compatible = "riscv,debug-013";
+ interrupts-extended = <&CPU0_intc 65535 &CPU1_intc 65535 >;
+ reg = < 0x000000ff 0xf1000000 0x00000000 0x00001000 >;
+ reg-names = "control";
+ };
+
+ sdhci_0: sdhci@0xf000000000 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+ compatible = "openpiton,piton-mmc";
+ reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >;
+ };
+ clint@fff1020000 {
+ u-boot,dm-pre-reloc;
+ compatible = "riscv,clint0";
+ interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 &CPU1_intc 3 &CPU1_intc 7 >;
+ reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >;
+ reg-names = "control";
+ };
+
+ PLIC0: plic@fff1100000 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ compatible = "riscv,plic0";
+ interrupt-controller;
+ interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 &CPU1_intc 11 &CPU1_intc 9 >;
+ reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >;
+ riscv,max-priority = <7>;
+ riscv,ndev = <2>;
+ };
+
+};
+
diff --git a/board/openpiton/riscv/Kconfig b/board/openpiton/riscv/Kconfig
new file mode 100644
index 00000000..31ae44d5
--- /dev/null
+++ b/board/openpiton/riscv/Kconfig
@@ -0,0 +1,42 @@
+if TARGET_OPENPITON_RISCV
+
+config SYS_BOARD
+ default "riscv"
+
+config SYS_VENDOR
+ default "openpiton"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "openpiton-riscv"
+
+config SYS_TEXT_BASE
+ default 0x81000000 if SPL
+ default 0x80000000 if !RISCV_SMODE
+ default 0x81000000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+ default 0x80000000
+
+config SPL_OPENSBI_LOAD_ADDR
+ default 0x81000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_EARLY_INIT_R
+ select SUPPORT_SPL
+ imply CPU_RISCV
+ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply CMD_CPU
+ imply SPL_CPU_SUPPORT
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
+ imply SPL_SMP
+ imply SPL_MMC
+ imply SMP
+ imply SPL_RISCV_MMODE
+
+endif
diff --git a/board/openpiton/riscv/MAINTAINERS b/board/openpiton/riscv/MAINTAINERS
new file mode 100644
index 00000000..1db6fb60
--- /dev/null
+++ b/board/openpiton/riscv/MAINTAINERS
@@ -0,0 +1,6 @@
+Openpiton Riscv Bootloader
+M: Tianrui Wei<tianrui-wei(a)outlook.com>
+S: Maintained
+F: board/openpiton/riscv/
+F: include/configs/openpiton-riscv.h
+F: configs/openpiton_riscv_defconfig
diff --git a/board/openpiton/riscv/Makefile b/board/openpiton/riscv/Makefile
new file mode 100644
index 00000000..8cc20e7c
--- /dev/null
+++ b/board/openpiton/riscv/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 Tianrui Wei
+# Tianrui Wei <tianrui-wei(a)outlook.com>
+obj-y += openpiton-riscv.o
diff --git a/board/openpiton/riscv/openpiton-riscv.c b/board/openpiton/riscv/openpiton-riscv.c
new file mode 100644
index 00000000..7cc621bc
--- /dev/null
+++ b/board/openpiton/riscv/openpiton-riscv.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 SiFive, Inc
+ * Copyright (c) 2021 Tianrui Wei
+ *
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel(a)sifive.com>
+ * Tianrui Wei <tianrui-wei(a)outlook.com>
+ */
+#include <common.h>
+#include <init.h>
+#include <configs/openpiton-riscv.h>
+#include <dm.h>
+#include <spl.h>
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list) {
+ u8 i;
+ u32 boot_devices[] = {
+ BOOT_DEVICE_MMC1,
+ };
+
+ for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+ spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name) {
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
+
+int board_init()
+{
+ return 0;
+}
diff --git a/configs/openpiton_riscv64_defconfig b/configs/openpiton_riscv64_defconfig
new file mode 100644
index 00000000..37aa3c80
--- /dev/null
+++ b/configs/openpiton_riscv64_defconfig
@@ -0,0 +1,132 @@
+CONFIG_RISCV=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
+CONFIG_TARGET_OPENPITON_RISCV=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_MISC_INIT_R=n
+CONFIG_SYS_MALLOC_F_LEN=0x1000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
+CONFIG_SPL_PAYLOAD=""
+CONFIG_LIBDISK_SUPPORT=y
+CONFIG_NR_CPUS=32
+CONFIG_CMODEL_MEDANY=y
+CONFIG_EXPORT=n
+CONFIG_HASH=n
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_BANNER_PRINT=n
+CONFIG_SPL_CRC32_SUPPORT=n
+CONFIG_GENERATE_SMBIOS_TABLE=n
+CONFIG_EFI_LOADER=n
+CONFIG_LIB_DATA=y
+CONFIG_SPL_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_FS_EXT4=y
+CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPL_OPENSBI=n
+CONFIG_SPL_RTC_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=n
+CONFIG_CMD_NET=n
+CONFIG_EFI_PARTITION=y
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=128
+CONFIG_EFI_PARTITION_ENTRIES_OFF=0
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_OF_EMBED=y
+CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_CPU=y
+CONFIG_CPU_RISCV=y
+CONFIG_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_SPL_DM_MMC=y
+CONFIG_MMC_PITON=y
+CONFIG_MMC_QUIRKS=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_NS16550=y
+CONFIG_DEBUG_UART_SHIFT=0
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_DEBUG_UART_BASE=0xfff0c2c000
+CONFIG_DEBUG_UART_CLOCK=66667000
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_MMC_VERBOSE=n
+CONFIG_MMC_WRITE=n
+CONFIG_MMC_HW_PARTITIONING=n
+CONFIG_SYS_RELOC_GD_ENV_ADDR=n
+CONFIG_SAVEENV=n
+CONFIG_NET=n
+CONFIG_SPL_PARTITION_UUIDS=n
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_EXPERT=n
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_LEGACY_IMAGE_FORMAT=n
+CONFIG_ARCH_FIXUP_FDT_MEMORY=n
+CONFIG_MENU=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_PART=y
+CONFIG_SHOW_REGS=y
+CONFIG_LOG=y
+CONFIG_LOGLEVEL=9
+CONFIG_SPL_LOGLEVEL=9
+CONFIG_TPL_LOGLEVEL=9
+CONFIG_SPL_LOG=y
+CONFIG_SPL_LOG_MAX_LEVEL=9
+CONFIG_SPL_LOG_CONSOLE=y
+CONFIG_LOG_ERROR_RETURN=y
+CONFIG_CMD_CPU=n
+CONFIG_BOOTM_NETBSD=n
+CONFIG_BOOTM_PLAN9=n
+CONFIG_BOOTM_RTEMS=n
+CONFIG_BOOTM_VXWORKS=n
+CONFIG_CMD_RUN=n
+CONFIG_CMD_IMI=n
+CONFIG_CMD_XIMG=n
+CONFIG_CMD_EXPORTENV=n
+CONFIG_CMD_IMPORTENV=n
+CONFIG_CMD_EDITENV=n
+CONFIG_CMD_SAVEENV=n
+CONFIG_CMD_CRC32=n
+CONFIG_CMD_RANDOM=n
+CONFIG_CMD_LZMADEC=n
+CONFIG_CMD_UNLZ4=n
+CONFIG_CMD_UNZIP=n
+CONFIG_CMD_FLASH=n
+CONFIG_RANDOM_UUID=n
+CONFIG_CMD_LOADB=n
+CONFIG_CMD_LOADS=n
+CONFIG_CMD_ECHO=n
+CONFIG_CMD_ITEST=n
+CONFIG_CMD_SOURCE=n
+CONFIG_CMD_SETEXPR=n
+CONFIG_CMD_BLOCK_CACHE=n
+CONFIG_CMD_DATE=n
+CONFIG_CMD_SLEEP=n
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_FAT=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ISO_PARTITION=y
+CONFIG_DM_ETH=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=65536
+CONFIG_FS_SQUASHFS=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_MD5=y
+CONFIG_ZLIB_UNCOMPRESS=y
+CONFIG_SPL_GZIP=y
+CONFIG_SPL_ZLIB=y
+CONFIG_GETOPT=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_RAM_SIFIVE=n
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 14d79139..a3650211 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -707,6 +707,12 @@ config MMC_SUNXI_HAS_MODE_SWITCH
bool
depends on MMC_SUNXI
+config MMC_PITON
+ bool "MMC support for OpenPiton SoC"
+ default y
+ help
+ This driver enables mmc controller support in uboot port for OpenPiton
+
config GENERIC_ATMEL_MCI
bool "Atmel Multimedia Card Interface support"
depends on DM_MMC && BLK && ARCH_AT91
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 1c849cba..698dfe05 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_MMC_SDHCI_XENON) += xenon_sdhci.o
obj-$(CONFIG_MMC_SDHCI_ZYNQ) += zynq_sdhci.o
obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
+obj-$(CONFIG_MMC_PITON) += piton_mmc.o
obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o
obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o
obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o
diff --git a/drivers/mmc/piton_mmc.c b/drivers/mmc/piton_mmc.c
new file mode 100644
index 00000000..e54be447
--- /dev/null
+++ b/drivers/mmc/piton_mmc.c
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang(a)samsung.com>
+ * Jaehoon Chung <jh80.chung(a)samsung.com>
+ * Portions Copyright 2011-2019 NVIDIA Corporation
+ * Portions Copyright 2021 Tianrui Wei
+ * Tianrui Wei <tianrui-wei(a)outlook.com>
+ */
+
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <log.h>
+#include <div64.h>
+#include <mmc.h>
+
+struct piton_mmc_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct piton_mmc_priv {
+ uint64_t piton_mmc_base_addr; /* peripheral id */
+};
+
+// see mmc_read_blocks to see how it is used.
+// start block is hidden at cmd->arg
+// also, initialize the block size at init
+static int piton_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+ struct mmc_data *data) {
+ // check first if this is a pure command
+ if (data == NULL) {
+ return 0;
+ }
+
+ // byte count counts all the bytes required for this command
+ uint64_t byte_cnt = data->blocks * data->blocksize;
+ // get which block in mmc card to start from
+ uint64_t start_block = cmd->cmdarg;
+ // buff points to the address we store the data stored at mmc card
+ unsigned *buff = (unsigned int *) data->dest;
+
+ struct piton_mmc_priv *priv = dev_get_priv(dev);
+ // start address denotes the absolute address where the transmission start
+ uint64_t start_addr = priv->piton_mmc_base_addr + (start_block);
+
+ /* if data is not empty*/
+ if (data) {
+
+ /* if there is a read */
+ if (data->flags & MMC_DATA_READ) {
+ for (uint64_t i = 0; i < byte_cnt; i += 4) {
+ *(buff) = readl((void *)(start_addr + i));
+ buff++;
+ }
+ } else {
+ /* else there is a write
+ * we don't handle write, so error right away
+ */
+ return -ENODEV;
+ }
+ }
+
+ return 0;
+}
+
+static int piton_mmc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct piton_mmc_priv *priv = dev_get_priv(dev);
+ struct piton_mmc_plat *plat = dev_get_platdata(dev);
+ struct mmc_config *cfg;
+ struct mmc *mmc;
+
+ priv->piton_mmc_base_addr = dev_read_addr(dev);
+ cfg = &plat->cfg;
+ cfg->name = "PITON MMC";
+ cfg->host_caps = MMC_MODE_8BIT;
+ cfg->f_max = 100000;
+ cfg->f_min = 400000;
+ cfg->voltages = MMC_VDD_21_22;
+
+ mmc = &plat->mmc;
+ mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
+ mmc->capacity_user = 0x100000000ULL;
+ mmc->capacity_user *= mmc->read_bl_len;
+ mmc->capacity_boot = 0;
+ mmc->capacity_rpmb = 0;
+ for (int i = 0; i < 4; i++)
+ mmc->capacity_gp[i] = 0;
+ mmc->capacity = 0x800000000ULL;
+ mmc->has_init = 1;
+
+ /* fill in device description */
+ struct blk_desc *bdesc;
+
+ bdesc = mmc_get_blk_desc(mmc);
+ bdesc->lun = 0;
+ bdesc->hwpart = 0;
+ bdesc->type = 0;
+ bdesc->blksz = mmc->read_bl_len;
+ bdesc->log2blksz = LOG2(bdesc->blksz);
+ bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
+
+ return 0;
+}
+/*
+ * currently, this is ignored. we only use fixed speed
+ */
+static int piton_mmc_set_ios(struct udevice *dev) { return 0; }
+
+/* test if piton has the micro mmc card present
+ * always return 1, which means present
+ */
+static int piton_mmc_getcd(struct udevice *dev) {
+
+ return 1;
+}
+
+/* dummy function, piton_mmc don't need initialization in hw*/
+static int piton_mmc_init(struct udevice *dev) {
+
+ return 0;
+}
+
+static const struct dm_mmc_ops piton_mmc_ops = {
+ // send a command to mmc device
+ .send_cmd = piton_mmc_send_cmd,
+ // set iospeed
+ .set_ios = piton_mmc_set_ios,
+ // detect if card is present
+ .get_cd = piton_mmc_getcd,
+};
+
+static int piton_mmc_probe(struct udevice *dev) {
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct piton_mmc_plat *plat = dev_get_platdata(dev);
+ struct mmc_config *cfg = &plat->cfg;
+
+ cfg->name = dev->name;
+ upriv->mmc = &plat->mmc;
+ upriv->mmc->has_init = 1;
+ upriv->mmc->capacity = 0x2000000000ULL;
+ upriv->mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
+
+ return piton_mmc_init(dev);
+}
+
+static int piton_mmc_bind(struct udevice *dev) {
+ struct piton_mmc_plat *plat = dev_get_platdata(dev);
+ struct mmc_config *cfg = &plat->cfg;
+
+ cfg->name = dev->name;
+ cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT;
+ cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
+ cfg->f_min = 1000000;
+ cfg->f_max = 52000000;
+ cfg->b_max = U32_MAX;
+
+ return mmc_bind(dev, &plat->mmc, cfg);
+}
+
+static const struct udevice_id piton_mmc_ids[] = {
+ {.compatible = "openpiton,piton-mmc"}, {}};
+
+U_BOOT_DRIVER(piton_mmc_drv) = {
+ .name = "piton_mmc",
+ .id = UCLASS_MMC,
+ .of_match = piton_mmc_ids,
+ .ofdata_to_platdata = piton_mmc_ofdata_to_platdata,
+ .bind = piton_mmc_bind,
+ .probe = piton_mmc_probe,
+ .ops = &piton_mmc_ops,
+ .platdata_auto_alloc_size = sizeof(struct piton_mmc_plat),
+ .priv_auto_alloc_size = sizeof(struct piton_mmc_priv),
+};
diff --git a/include/configs/openpiton-riscv.h b/include/configs/openpiton-riscv.h
new file mode 100644
index 00000000..514edbc6
--- /dev/null
+++ b/include/configs/openpiton-riscv.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2021 Tianrui Wei
+ *
+ * Authors:
+ * Anup Patel <anup.patel(a)wdc.com>
+ * Tianrui Wei <tianrui-wei(a)outlook.com>
+ */
+
+#ifndef __OPENPITON_RISCV_CONFIG_H
+#define __OPENPITON_RISCV_CONFIG_H
+
+#include <linux/sizes.h>
+#define DEBUG
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_MAX_SIZE 0x00100000
+#define CONFIG_SPL_BSS_START_ADDR 0x82000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0100000
+#define CONFIG_SPL_STACK (0x80000000 + 0x04000000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin"
+#define CONFIG_SPL_GD_ADDR 0x85000000
+#endif
+
+/* Environment options */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
+#define CONFIG_SYS_MALLOC_LEN SZ_256M
+#define CONFIG_SYS_BOOTM_LEN SZ_256M
+
+/* -------------------------------------------------
+ * Environment
+ */
+//Disable persistent environment variable storage
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/* ---------------------------------------------------------------------
+ * Board boot configuration
+ */
+
+#define CONFIG_EXTRA_ENV_SETTINGS "\0"
+
+#define CONFIG_USE_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+ "fdt addr ${fdtcontroladdr}; " \
+ "fdt move ${fdtcontroladdr} 0x86000000; " \
+ "ext4load mmc 0:1 0x80200000 boot/Image; " \
+ "booti 0x80200000 - 0x86000000; "
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+#endif/* __CONFIG_H */
--
2.17.1
