April 2021 - U-Boot

[PATCH] stm32mp: stm32prog: add FIP header support
by Patrick Delaunay 09 Apr '21

09 Apr '21

Add support of TF-A FIP header in command stm32prog for all the boot partition and not only the STM32IMAGE. This patch is a preliminary patch to support FIP as second boot stage after TF-A BL2 when CONFIG_TFABOOT is activated for trusted boot chain. The FIP is archive binary loaded by TF-A BL2, which contains the secure OS = OP-TEE and the non secure firmware and device tree = U-Boot. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- .../cmd_stm32prog/cmd_stm32prog.c | 19 +++--- .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 59 +++++++++++++------ .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 12 +++- .../cmd_stm32prog/stm32prog_serial.c | 11 ++-- 4 files changed, 64 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index a7e2861764..e36501a86b 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -73,15 +73,16 @@ static int do_stm32prog(struct cmd_tbl *cmdtp, int flag, int argc, size = simple_strtoul(argv[4], NULL, 16); /* check STM32IMAGE presence */ - if (size == 0 && - !stm32prog_header_check((struct raw_header_s *)addr, &header)) { - size = header.image_length + BL_HEADER_SIZE; - - /* uImage detected in STM32IMAGE, execute the script */ - if (IMAGE_FORMAT_LEGACY == - genimg_get_format((void *)(addr + BL_HEADER_SIZE))) - return image_source_script(addr + BL_HEADER_SIZE, - "script@1"); + if (size == 0) { + stm32prog_header_check((struct raw_header_s *)addr, &header); + if (header.type == HEADER_STM32IMAGE) { + size = header.image_length + BL_HEADER_SIZE; + + /* uImage detected in STM32IMAGE, execute the script */ + if (IMAGE_FORMAT_LEGACY == + genimg_get_format((void *)(addr + BL_HEADER_SIZE))) + return image_source_script(addr + BL_HEADER_SIZE, "script@1"); + } } if (IS_ENABLED(CONFIG_DM_VIDEO)) diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index d0518d1223..4c4d8a7a69 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -60,8 +60,6 @@ static const efi_guid_t uuid_mmc[3] = { ROOTFS_MMC2_UUID }; -DECLARE_GLOBAL_DATA_PTR; - /* order of column in flash layout file */ enum stm32prog_col_t { COL_OPTION, @@ -73,6 +71,16 @@ enum stm32prog_col_t { COL_NB_STM32 }; +#define FIP_TOC_HEADER_NAME 0xAA640001 + +struct fip_toc_header { + u32 name; + u32 serial_number; + u64 flags; +}; + +DECLARE_GLOBAL_DATA_PTR; + /* partition handling routines : CONFIG_CMD_MTDPARTS */ int mtdparts_init(void); int find_dev_and_part(const char *id, struct mtd_device **dev, @@ -88,46 +96,57 @@ char *stm32prog_get_error(struct stm32prog_data *data) return data->error; } -u8 stm32prog_header_check(struct raw_header_s *raw_header, - struct image_header_s *header) +static bool stm32prog_is_fip_header(struct fip_toc_header *header) +{ + return (header->name == FIP_TOC_HEADER_NAME) && header->serial_number; +} + +void stm32prog_header_check(struct raw_header_s *raw_header, + struct image_header_s *header) { unsigned int i; - header->present = 0; + if (!raw_header || !header) { + log_debug("%s:no header data\n", __func__); + return; + } + + header->type = HEADER_NONE; header->image_checksum = 0x0; header->image_length = 0x0; - if (!raw_header || !header) { - log_debug("%s:no header data\n", __func__); - return -1; + if (stm32prog_is_fip_header((struct fip_toc_header *)raw_header)) { + header->type = HEADER_FIP; + return; } + if (raw_header->magic_number != (('S' << 0) | ('T' << 8) | ('M' << 16) | (0x32 << 24))) { log_debug("%s:invalid magic number : 0x%x\n", __func__, raw_header->magic_number); - return -2; + return; } /* only header v1.0 supported */ if (raw_header->header_version != 0x00010000) { log_debug("%s:invalid header version : 0x%x\n", __func__, raw_header->header_version); - return -3; + return; } if (raw_header->reserved1 != 0x0 || raw_header->reserved2) { log_debug("%s:invalid reserved field\n", __func__); - return -4; + return; } for (i = 0; i < (sizeof(raw_header->padding) / 4); i++) { if (raw_header->padding[i] != 0) { log_debug("%s:invalid padding field\n", __func__); - return -5; + return; } } - header->present = 1; + header->type = HEADER_STM32IMAGE; header->image_checksum = le32_to_cpu(raw_header->image_checksum); header->image_length = le32_to_cpu(raw_header->image_length); - return 0; + return; } static u32 stm32prog_header_checksum(u32 addr, struct image_header_s *header) @@ -356,8 +375,8 @@ static int parse_flash_layout(struct stm32prog_data *data, data->part_nb = 0; /* check if STM32image is detected */ - if (!stm32prog_header_check((struct raw_header_s *)addr, - &data->header)) { + stm32prog_header_check((struct raw_header_s *)addr, &data->header); + if (data->header.type == HEADER_STM32IMAGE) { u32 checksum; addr = addr + BL_HEADER_SIZE; @@ -1410,7 +1429,7 @@ static int stm32prog_copy_fsbl(struct stm32prog_part_t *part) if (part->target != STM32PROG_NAND && part->target != STM32PROG_SPI_NAND) - return -1; + return -EINVAL; dfu = dfu_get_entity(part->alt_id); @@ -1420,8 +1439,10 @@ static int stm32prog_copy_fsbl(struct stm32prog_part_t *part) ret = dfu->read_medium(dfu, 0, (void *)&raw_header, &size); if (ret) return ret; - if (stm32prog_header_check(&raw_header, &header)) - return -1; + + stm32prog_header_check(&raw_header, &header); + if (header.type != HEADER_STM32IMAGE) + return -ENOENT; /* read header + payload */ size = header.image_length + BL_HEADER_SIZE; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index 18af99c78b..581b10d0ac 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -37,8 +37,14 @@ enum stm32prog_link_t { LINK_UNDEFINED, }; +enum stm32prog_header_t { + HEADER_NONE, + HEADER_STM32IMAGE, + HEADER_FIP, +}; + struct image_header_s { - bool present; + enum stm32prog_header_t type; u32 image_checksum; u32 image_length; }; @@ -160,8 +166,8 @@ int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, int stm32prog_pmic_start(struct stm32prog_data *data); /* generic part*/ -u8 stm32prog_header_check(struct raw_header_s *raw_header, - struct image_header_s *header); +void stm32prog_header_check(struct raw_header_s *raw_header, + struct image_header_s *header); int stm32prog_dfu_init(struct stm32prog_data *data); void stm32prog_next_phase(struct stm32prog_data *data); void stm32prog_do_reset(struct stm32prog_data *data); diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c index a51e5e3ec8..2b92e3b149 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c @@ -309,11 +309,10 @@ static u8 stm32prog_header(struct stm32prog_data *data) /* force cleanup to avoid issue with previous read */ dfu_transaction_cleanup(dfu_entity); - ret = stm32prog_header_check(data->header_data, - &data->header); + stm32prog_header_check(data->header_data, &data->header); - /* no header : max size is partition size */ - if (ret) { + /* no stm32 image header : max size is partition size */ + if (data->header.type != HEADER_STM32IMAGE) { dfu_entity->get_medium_size(dfu_entity, &size); data->header.image_length = size; } @@ -389,7 +388,7 @@ static u8 stm32prog_start(struct stm32prog_data *data, u32 address) data->dfu_seq = 0; printf("\n received length = 0x%x\n", data->cursor); - if (data->header.present) { + if (data->header.type == HEADER_STM32IMAGE) { if (data->cursor != (data->header.image_length + BL_HEADER_SIZE)) { stm32prog_err("transmission interrupted (length=0x%x expected=0x%x)", @@ -789,7 +788,7 @@ static void download_command(struct stm32prog_data *data) } } - if (image_header->present) { + if (data->header.type == HEADER_STM32IMAGE) { if (data->cursor <= BL_HEADER_SIZE) goto end; /* compute checksum on payload */ -- 2.17.1

2 2

[PATCH 1/3] configs: stm32mp1: stm32mp1: Increase SPL malloc() size
by Alexandru Gagniuc 09 Apr '21

09 Apr '21

Since commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for loading images"), FIT images must be malloc()'d before being loaded. The old size of 1 MiB is suitable for FIT images with u-boot and an FDT, but something containing a linux kernel is almost sure to fail. It's safe to extend malloc all the way to 0xc2000000, but no further. Linux likes to be loaded at 0xc2000000, so we use that as our cutoff point. This gives us 29 MiB of malloc() space, which suited for more complex FIT images including several DTBs, kernel, and OP-TEE images. Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- include/configs/stm32mp1.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index db2117a3d7..7fdb3ffce4 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -53,7 +53,7 @@ #define CONFIG_SPL_BSS_START_ADDR 0xC0200000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0xC0300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x01D00000 /* limit SYSRAM usage to first 128 KB */ #define CONFIG_SPL_MAX_SIZE 0x00020000 -- 2.26.2

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[PATCH v3 0/8] stm32: Add Engicam STM32MP1 SoM
by Jagan Teki 09 Apr '21

09 Apr '21

Patch series for Engicam i.Core and MicroGEA SoM and it's associated carrier board dts(i) support. Changes for v3: - collect Patrick Delaunay r-b - fixed comments from Patrick Delaunay Changes for v2: - add Linux dts commit ids in commit messages - drop CONFIG_BOARD_EARLY_INIT_F - order dts files in Makefile - collect Patrice r-b Any inputs? Jagan. Jagan Teki (8): ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM ARM: dts: stm32: Add Engicam i.Core STM32MP1 1X4Gb DDR3 ARM: stm32: Imply SPL_SPI_LOAD board: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit board: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 Micro SoM board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board board: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF arch/arm/dts/Makefile | 4 + .../stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi | 119 +++++++++++ ...2mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi | 51 +++++ .../stm32mp157a-icore-stm32mp1-ctouch2.dts | 47 +++++ ...mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi | 51 +++++ .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 47 +++++ .../stm32mp157a-icore-stm32mp1-u-boot.dtsi | 146 +++++++++++++ arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi | 196 ++++++++++++++++++ ...rogea-stm32mp1-microdev2.0-of7-u-boot.dtsi | 51 +++++ ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 154 ++++++++++++++ ...-microgea-stm32mp1-microdev2.0-u-boot.dtsi | 51 +++++ ...32mp157a-microgea-stm32mp1-microdev2.0.dts | 55 +++++ .../stm32mp157a-microgea-stm32mp1-u-boot.dtsi | 118 +++++++++++ .../dts/stm32mp157a-microgea-stm32mp1.dtsi | 148 +++++++++++++ arch/arm/mach-stm32mp/Kconfig | 54 ++++- board/engicam/stm32mp1/Kconfig | 12 ++ board/engicam/stm32mp1/MAINTAINERS | 26 +++ board/engicam/stm32mp1/Makefile | 10 + board/engicam/stm32mp1/spl.c | 48 +++++ board/engicam/stm32mp1/stm32mp1.c | 125 +++++++++++ ...stm32mp15-icore-stm32mp1-ctouch2_defconfig | 79 +++++++ ...tm32mp15-icore-stm32mp1-edimm2.2_defconfig | 79 +++++++ ...-microgea-stm32mp1-microdev2-of7_defconfig | 79 +++++++ ...mp15-microgea-stm32mp1-microdev2_defconfig | 79 +++++++ 24 files changed, 1828 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/stm32mp15-ddr3-icore-1x4Gb-1066-binG.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-icore-stm32mp1.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-microgea-stm32mp1.dtsi create mode 100644 board/engicam/stm32mp1/Kconfig create mode 100644 board/engicam/stm32mp1/MAINTAINERS create mode 100644 board/engicam/stm32mp1/Makefile create mode 100644 board/engicam/stm32mp1/spl.c create mode 100644 board/engicam/stm32mp1/stm32mp1.c create mode 100644 configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig create mode 100644 configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig create mode 100644 configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig -- 2.25.1

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[PATCH v5 0/7] Add rt-thread art-pi board support
by dillon.minfei＠gmail.com 09 Apr '21

09 Apr '21

From: dillon min <dillon.minfei(a)gmail.com> These patches aim to adds u-boot support on art-pi board. the board resources: - stm32h750xbh6 128k flash, 1024k sram - 32MiB sdram - 16MiB spi flash - 8MiB qspi flash - onboard wifi, bt, fm the detail board information can be found at: https://art-pi.gitee.io/website/ --- changes in v5: - remove "for STMicroelectronics." from Author(s) description changes in v4: - sync with kernel side device tree submit - use strlcpy in stm32_sdram.c - update CONFIG_BOOTARGS, remove rdinit=/linuxrc, to use kernel's devtmpfs - remove unused st,stm32h750-pinctrl from patch v3 changes in v3: two mirror changes in [PATCH v3 2/6], others same to version 2 - remove "for STMicroelectronics." from arch/arm/dts/stm32h750-pinctrl.dtsi - correct misspelling parameters you can found detail patch v2 information at link: https://patchwork.ozlabs.org/project/uboot/list/?series=236009 changes in v2: - fix wrong author/date in previous submit - sync with kernel device tree files - add st,stm32h750-pinctrl in doc and pinctrl driver *** BLURB HERE *** dillon min (7): ARM: dts: stm32: split sdram pin & timing parameter into specific board dts ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750 ARM: dts: stm32: add new instances for stm32h743 MCU ARM: dts: stm32: fix i2c node typo in stm32h743, update dmamux1 register ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6 ram: stm32: fix strsep failed on read only memory board: Add rt-thread art-pi board support arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32h7-pinctrl.dtsi | 274 ++++++++++++++++++++++++ arch/arm/dts/stm32h7-u-boot.dtsi | 100 +-------- arch/arm/dts/stm32h743-pinctrl.dtsi | 306 --------------------------- arch/arm/dts/stm32h743.dtsi | 178 +++++++++++++++- arch/arm/dts/stm32h743i-disco-u-boot.dtsi | 98 +++++++++ arch/arm/dts/stm32h743i-disco.dts | 2 +- arch/arm/dts/stm32h743i-eval-u-boot.dtsi | 98 +++++++++ arch/arm/dts/stm32h743i-eval.dts | 2 +- arch/arm/dts/stm32h750.dtsi | 5 + arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi | 81 +++++++ arch/arm/dts/stm32h750i-art-pi.dts | 188 ++++++++++++++++ arch/arm/mach-stm32/stm32h7/Kconfig | 4 + board/st/stm32h750-art-pi/Kconfig | 19 ++ board/st/stm32h750-art-pi/MAINTAINERS | 7 + board/st/stm32h750-art-pi/Makefile | 6 + board/st/stm32h750-art-pi/stm32h750-art-pi.c | 58 +++++ configs/stm32h750-art-pi_defconfig | 51 +++++ drivers/ram/stm32_sdram.c | 3 + include/configs/stm32h750-art-pi.h | 48 +++++ include/dt-bindings/memory/stm32-sdram.h | 2 + 21 files changed, 1126 insertions(+), 407 deletions(-) create mode 100644 arch/arm/dts/stm32h7-pinctrl.dtsi delete mode 100644 arch/arm/dts/stm32h743-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32h750.dtsi create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts create mode 100644 board/st/stm32h750-art-pi/Kconfig create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS create mode 100644 board/st/stm32h750-art-pi/Makefile create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c create mode 100644 configs/stm32h750-art-pi_defconfig create mode 100644 include/configs/stm32h750-art-pi.h -- 2.7.4

2 14

[PATCH 0/2] Add Xilinx clock wizard driver support
by zhengxunli 09 Apr '21

09 Apr '21

Hi, This series add support to enable clock wizard for zynq platform. Thanks, Zhengxun zhengxunli (2): clk: zynq: Add clock wizard driver board: Add Zynq Mxic picozed development board support arch/arm/dts/Makefile | 3 +- arch/arm/dts/zynq-mxic-picozed.dts | 66 ++++++++++++++ drivers/clk/Kconfig | 7 ++ drivers/clk/Makefile | 1 + drivers/clk/clk_wizard.c | 180 +++++++++++++++++++++++++++++++++++++ 5 files changed, 256 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/zynq-mxic-picozed.dts create mode 100644 drivers/clk/clk_wizard.c -- 1.9.1

3 6

[PATCH v3 00/11] riscv: k210: Enable use of AI ram bank
by Sean Anderson 09 Apr '21

09 Apr '21

This ram bank was previously unusable because PLL1 was not started correctly. This series fixes that bug, and allows U-Boot to relocate into the AI ram. This provides an extra 2M of space in which to load payloads. I've also added some minor patches to bring the device tree and clock driver closer to what Linux has (or will have). The bypass clock turned out to be still necessary after all; I had neglected to test with CLK_K210_SET_RATE enabled, and I didn't notice that the clock rate wasn't actually getting set (oops). I've added a warning which will hopefully make it more difficult to make such mistakes in the future. Changes in v3: - Add a warning if we can't assign rates - Split off patchs for fdtdec_setup_mem_size_base_* into another series - Eliminated separate RAM driver - Rebased onto u-boot/next Changes in v2: - Don't re-enable the PLL - Simplify PLL instantiation - Modify clock tree so clint is a child of aclk - Sync memory dts node with Linux - Use correct aisram clock Sean Anderson (11): clk: Warn on failure to assign rate clk: k210: Fix PLLs not being enabled clk: k210: Fix PLL enable always getting taken clk: k210: Remove k210_register_pll clk: k210: Move the clint clock to under aclk clk: Add support for the k210 clock driver pre-relocation riscv: Enable some devices pre-relocation riscv: Enable AI ram on K210 riscv: k210: Rename airam to aisram riscv: k210: Use AI as the parent clock of aisram, not PLL1 riscv: Don't reserve AI ram in k210 dts arch/riscv/dts/k210.dtsi | 22 +++++++--------------- board/sipeed/maix/maix.c | 14 ++++++++++++-- configs/sipeed_maix_bitm_defconfig | 2 ++ drivers/clk/clk-uclass.c | 11 +++++++---- drivers/clk/kendryte/clk.c | 26 ++++++++++++++------------ drivers/clk/kendryte/pll.c | 26 ++++---------------------- include/configs/sipeed-maix.h | 3 +-- include/kendryte/pll.h | 4 ---- 8 files changed, 47 insertions(+), 61 deletions(-) -- 2.31.0

2 17

[PATCH v4 0/7] Add rt-thread art-pi board support
by dillon.minfei＠gmail.com 09 Apr '21

09 Apr '21

From: dillon min <dillon.minfei(a)gmail.com> These patches aim to adds u-boot support on art-pi board. the board resources: - stm32h750xbh6 128k flash, 1024k sram - 32MiB sdram - 16MiB spi flash - 8MiB qspi flash - onboard wifi, bt, fm the detail board information can be found at: https://art-pi.gitee.io/website/ --- changes in v4: - sync with kernel side device tree submit - use strlcpy in stm32_sdram.c - update CONFIG_BOOTARGS, remove rdinit=/linuxrc, to use kernel's devtmpfs - remove unused st,stm32h750-pinctrl from patch v3 changes in v3: two mirror changes in [PATCH v3 2/6], others same to version 2 - remove "for STMicroelectronics." from arch/arm/dts/stm32h750-pinctrl.dtsi - correct misspelling parameters you can found detail patch v2 information at link: https://patchwork.ozlabs.org/project/uboot/list/?series=236009 changes in v2: - fix wrong author/date in previous submit - sync with kernel device tree files - add st,stm32h750-pinctrl in doc and pinctrl driver *** BLURB HERE *** dillon min (7): ARM: dts: stm32: split sdram pin & timing parameter into specific board dts ARM: dts: stm32: introduce stm32h7-pinctrl.dtsi to support stm32h750 ARM: dts: stm32: add new instances for stm32h743 MCU ARM: dts: stm32: fix i2c node typo in stm32h743, update dmamux1 register ARM: dts: stm32: add support for art-pi board based on stm32h750xbh6 ram: stm32: fix strsep failed on read only memory board: Add rt-thread art-pi board support arch/arm/dts/Makefile | 3 +- arch/arm/dts/stm32h7-pinctrl.dtsi | 274 ++++++++++++++++++++++++ arch/arm/dts/stm32h7-u-boot.dtsi | 100 +-------- arch/arm/dts/stm32h743-pinctrl.dtsi | 306 --------------------------- arch/arm/dts/stm32h743.dtsi | 178 +++++++++++++++- arch/arm/dts/stm32h743i-disco-u-boot.dtsi | 98 +++++++++ arch/arm/dts/stm32h743i-disco.dts | 2 +- arch/arm/dts/stm32h743i-eval-u-boot.dtsi | 98 +++++++++ arch/arm/dts/stm32h743i-eval.dts | 2 +- arch/arm/dts/stm32h750.dtsi | 5 + arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi | 81 +++++++ arch/arm/dts/stm32h750i-art-pi.dts | 188 ++++++++++++++++ arch/arm/mach-stm32/stm32h7/Kconfig | 4 + board/st/stm32h750-art-pi/Kconfig | 19 ++ board/st/stm32h750-art-pi/MAINTAINERS | 7 + board/st/stm32h750-art-pi/Makefile | 6 + board/st/stm32h750-art-pi/stm32h750-art-pi.c | 58 +++++ configs/stm32h750-art-pi_defconfig | 51 +++++ drivers/ram/stm32_sdram.c | 3 + include/configs/stm32h750-art-pi.h | 48 +++++ include/dt-bindings/memory/stm32-sdram.h | 2 + 21 files changed, 1126 insertions(+), 407 deletions(-) create mode 100644 arch/arm/dts/stm32h7-pinctrl.dtsi delete mode 100644 arch/arm/dts/stm32h743-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32h750.dtsi create mode 100644 arch/arm/dts/stm32h750i-art-pi-u-boot.dtsi create mode 100644 arch/arm/dts/stm32h750i-art-pi.dts create mode 100644 board/st/stm32h750-art-pi/Kconfig create mode 100644 board/st/stm32h750-art-pi/MAINTAINERS create mode 100644 board/st/stm32h750-art-pi/Makefile create mode 100644 board/st/stm32h750-art-pi/stm32h750-art-pi.c create mode 100644 configs/stm32h750-art-pi_defconfig create mode 100644 include/configs/stm32h750-art-pi.h -- 2.7.4

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[PATCH] stm32mp1: remove the board_check_usb_power function when ADC is not activated
by Patrick Delaunay 09 Apr '21

09 Apr '21

Simplify the code of the function board_check_usb_power based in CONFIG_ADC and adc_measurement; the function is removed by the linker when the CONFIG_ADC is not activated. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- board/st/stm32mp1/stm32mp1.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 759181fb5d..261ec15e1b 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -347,6 +347,9 @@ static int board_check_usb_power(void) u32 nb_blink; u8 i; + if (!IS_ENABLED(CONFIG_ADC)) + return -ENODEV; + node = ofnode_path("/config"); if (!ofnode_valid(node)) { log_debug("no /config node?\n"); @@ -370,11 +373,7 @@ static int board_check_usb_power(void) /* perform maximum of 2 ADC measurements to detect power supply current */ for (i = 0; i < 2; i++) { - if (IS_ENABLED(CONFIG_ADC)) - ret = adc_measurement(node, adc_count, &min_uV, &max_uV); - else - ret = -ENODEV; - + ret = adc_measurement(node, adc_count, &min_uV, &max_uV); if (ret) return ret; -- 2.17.1

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[PATCH] ARM: imx: imx8mn-ddr4-evk: Add ethernet support
by Marek Vasut 08 Apr '21

08 Apr '21

Add support for ethernet on the imx8mn-ddr4-evk. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/dts/imx8mn-evk.dtsi | 1 + board/freescale/imx8mn_evk/imx8mn_evk.c | 41 +++++++++++++++++++++++-- configs/imx8mn_ddr4_evk_defconfig | 8 +++++ 3 files changed, 47 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi index 76d042a4cf0..416fadb22b1 100644 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -53,6 +53,7 @@ pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <&ethphy0>; + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; fsl,magic-packet; status = "okay"; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c index 9a0a0488bf4..8c4bb6c5b8e 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c @@ -6,18 +6,53 @@ #include <common.h> #include <env.h> #include <init.h> +#include <miiphy.h> +#include <netdev.h> #include <asm/global_data.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; -int board_init(void) +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +static int setup_fec(void) { + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); + return 0; } -int board_mmc_get_env_dev(int devno) +int board_phy_config(struct phy_device *phydev) { - return devno; + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return 0; } int board_late_init(void) diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index f7ea65886d5..c9a00bf2c2f 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -43,6 +43,9 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y @@ -71,7 +74,12 @@ CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -- 2.30.0

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[PATCH 1/5] ARM: board: udoo: Import UDOO dts files
by Peter Robinson 08 Apr '21

08 Apr '21

Import the i.MX6 based UDOO dts files from Linux 5.12-rc1. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/dts/Makefile | 2 + arch/arm/dts/imx6dl-udoo.dts | 14 ++ arch/arm/dts/imx6q-udoo.dts | 18 ++ arch/arm/dts/imx6qdl-udoo.dtsi | 324 +++++++++++++++++++++++++++++++++ 4 files changed, 358 insertions(+) create mode 100644 arch/arm/dts/imx6dl-udoo.dts create mode 100644 arch/arm/dts/imx6q-udoo.dts create mode 100644 arch/arm/dts/imx6qdl-udoo.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 88cf85596f..116f75192f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -686,6 +686,7 @@ dtb-y += \ imx6dl-mamoj.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-pico.dtb \ + imx6dl-udoo.dtb \ imx6dl-riotboard.dtb \ imx6dl-sabreauto.dtb \ imx6dl-sabresd.dtb \ @@ -721,6 +722,7 @@ dtb-y += \ imx6q-novena.dtb \ imx6q-pico.dtb \ imx6q-phytec-mira-rdk-nand.dtb \ + imx6q-udoo.dtb \ imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ diff --git a/arch/arm/dts/imx6dl-udoo.dts b/arch/arm/dts/imx6dl-udoo.dts new file mode 100644 index 0000000000..d871cac171 --- /dev/null +++ b/arch/arm/dts/imx6dl-udoo.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam(a)freescale.com> + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-udoo.dtsi" + +/ { + model = "Udoo i.MX6 Dual-lite Board"; + compatible = "udoo,imx6dl-udoo", "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6q-udoo.dts b/arch/arm/dts/imx6q-udoo.dts new file mode 100644 index 0000000000..52e9f4a211 --- /dev/null +++ b/arch/arm/dts/imx6q-udoo.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam(a)freescale.com> + */ +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-udoo.dtsi" + +/ { + model = "Udoo i.MX6 Quad Board"; + compatible = "udoo,imx6q-udoo", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qdl-udoo.dtsi b/arch/arm/dts/imx6qdl-udoo.dtsi new file mode 100644 index 0000000000..d07d8f8345 --- /dev/null +++ b/arch/arm/dts/imx6qdl-udoo.dtsi @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam(a)freescale.com> + */ + +/ { + aliases { + backlight = &backlight; + panelchan = &panelchan; + panel7 = &panel7; + touchscreenp7 = &touchscreenp7; + }; + + chosen { + stdout-path = &uart2; + }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpio1 4 0>; + default-on; + status = "disabled"; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio2 4 0>; + pinctrl-0 = <&pinctrl_power_off>; + pinctrl-names = "default"; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + panel7: panel7 { + /* + * in reality it is a -20t (parallel) model, + * but with LVDS bridge chip attached, + * so it is equivalent to -19t model in drive + * characteristics + */ + compatible = "urt,umsh-8596md-19t"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + power-supply = <&reg_panel>; + backlight = <&backlight>; + status = "disabled"; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_h1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ + gpio = <&gpio7 12 0>; + }; + + reg_panel: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "lcd_panel"; + enable-active-high; + gpio = <&gpio1 2 0>; + }; + }; + + sound { + compatible = "fsl,imx6q-udoo-ac97", + "fsl,imx-audio-ac97"; + model = "fsl,imx6q-udoo-ac97"; + audio-cpu = <&ssi1>; + audio-routing = + "RX", "Mic Jack", + "Headphone Jack", "TX"; + mux-int-port = <1>; + mux-ext-port = <6>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreenp7: touchscreenp7@55 { + compatible = "sitronix,st1232"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreenp7>; + reg = <0x55>; + interrupt-parent = <&gpio1>; + interrupts = <13 8>; + gpios = <&gpio1 15 0>; + status = "disabled"; + }; +}; + +&iomuxc { + imx6q-udoo { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70 + >; + }; + + pinctrl_power_off: poweroffgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30 + >; + }; + + pinctrl_touchscreenp7: touchscreenp7grp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbh: usbhgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 + MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 + >; + }; + + pinctrl_usbotg: usbotg { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x17059 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_ac97_running: ac97running { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 + MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_ac97_warm_reset: ac97warmreset { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x1b0b0 + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + + pinctrl_ac97_reset: ac97reset { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x13080 + MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x13080 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + panelchan: lvds-channel@0 { + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh>; + vbus-supply = <&reg_usb_h1_vbus>; + clocks = <&clks IMX6QDL_CLK_CKO>; + status = "okay"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + non-removable; + status = "okay"; +}; + +&audmux { + status = "okay"; +}; + +&ssi1 { + cell-index = <0>; + fsl,mode = "ac97-slave"; + pinctrl-names = "ac97-running", "ac97-reset", "ac97-warm-reset"; + pinctrl-0 = <&pinctrl_ac97_running>; + pinctrl-1 = <&pinctrl_ac97_reset>; + pinctrl-2 = <&pinctrl_ac97_warm_reset>; + ac97-gpios = <&gpio4 19 0 &gpio4 18 0 &gpio2 30 0>; + status = "okay"; +}; -- 2.31.1

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