April 2021 - U-Boot

[PATCH] imx: imx6ull: fix pinmux sel_input value for uart5 pins
by Yuichiro Goto 09 Apr '21

09 Apr '21

sel_input value for the following uart5 pins is different between i.MX6UL and i.MX6ULL: MX6_PAD_UART5_TX_DATA__UART5_DTE_RX MX6_PAD_UART5_RX_DATA__UART5_DCE_RX MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS MX6_PAD_CSI_DATA02__UART5_DCE_RTS As sel_input value for the second one is fixed by the previous commit, fix the rest. Signed-off-by: Yuichiro Goto <goto(a)k-tech.co.jp> --- arch/arm/include/asm/arch-mx6/mx6ull_pins.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h index de4a1abc..842d0caa 100644 --- a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h @@ -326,7 +326,7 @@ enum { MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0), - MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0), + MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 6, 0), MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0), MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0), MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0), @@ -363,7 +363,7 @@ enum { MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), - MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0), + MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 5, 0), MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), @@ -373,7 +373,7 @@ enum { MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), - MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 6, 0), MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), @@ -1012,7 +1012,7 @@ enum { MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0), MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0), MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0), - MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0), + MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 7, 0), MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0), MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0), -- 2.17.1

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[PATCH 1/1] imx6: icorem6: chmod 644 enigcam.bmp
by Heinrich Schuchardt 09 Apr '21

09 Apr '21

Bitmap files should not be executable. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- tools/logos/engicam.bmp | Bin 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 tools/logos/engicam.bmp diff --git a/tools/logos/engicam.bmp b/tools/logos/engicam.bmp old mode 100755 new mode 100644 -- 2.30.2

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[PATCH] doc: imx: psb: Document usage of SRC_GPR10 PERSIST_SECONDARY_BOOT for A/B switching
by Marek Vasut 09 Apr '21

09 Apr '21

Document SRC_GPR10 PERSIST_SECONDARY_BOOT functionality. This is useful for reliable bootloader A/B updates, as it permits switching between two copies of bootloader at different offsets of the same storage. The switch happens in case one copy is corrupted OR can be enforced by user. This functionality is present at least since i.MX53, however is poorly documented in all known SoC datasheets, hence this document aims to clarify the usage, currently on i.MX7D and i.MX8MM. Signed-off-by: Marek Vasut <marex(a)denx.de> # Original MX7D work, this document Signed-off-by: Igor Opaniuk <igor.opaniuk(a)foundries.io> # All the MX8M work Cc: Christoph Niedermaier <cniedermaier(a)dh-electronics.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Harald Seiler <hws(a)denx.de> Cc: Igor Opaniuk <igor.opaniuk(a)foundries.io> Cc: Jan Kiszka <jan.kiszka(a)siemens.com> Cc: Ludwig Zenz <lzenz(a)dh-electronics.com> Cc: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> Cc: Ye Li <ye.li(a)nxp.com> Cc: uboot-imx <uboot-imx(a)nxp.com> --- NOTE: This all was pieced together from various scraps of information. Links to further reading below. - MX53/Vybrid https://community.nxp.com/t5/Vybrid-Processors/Vybrid-secondary-image-table… - MX53 https://community.nxp.com/t5/i-MX-Processors/i-MX53-Redundant-Boot-blog-arc… - MX8M https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Mini-eMMC-Boot-Fusing/… - MX8M https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/… --- doc/imx/index.rst | 9 +++ doc/imx/misc/index.rst | 9 +++ doc/imx/misc/psb.rst | 174 +++++++++++++++++++++++++++++++++++++++++ doc/index.rst | 11 +++ 4 files changed, 203 insertions(+) create mode 100644 doc/imx/index.rst create mode 100644 doc/imx/misc/index.rst create mode 100644 doc/imx/misc/psb.rst diff --git a/doc/imx/index.rst b/doc/imx/index.rst new file mode 100644 index 00000000000..b225b1d1837 --- /dev/null +++ b/doc/imx/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +NXP i.MX Machine-specific doc +============================= + +.. toctree:: + :maxdepth: 2 + + misc/index diff --git a/doc/imx/misc/index.rst b/doc/imx/misc/index.rst new file mode 100644 index 00000000000..85fbdb6588f --- /dev/null +++ b/doc/imx/misc/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Miscellaneous +============= + +.. toctree:: + :maxdepth: 2 + + psb diff --git a/doc/imx/misc/psb.rst b/doc/imx/misc/psb.rst new file mode 100644 index 00000000000..bde6b1c0207 --- /dev/null +++ b/doc/imx/misc/psb.rst @@ -0,0 +1,174 @@ +i.MX7D/i.MX8MM SRC_GPR10 PERSIST_SECONDARY_BOOT for bootloader A/B switching +============================================================================ + +Introduction +------------ +Since at least iMX53 until iMX8MM, it is possible to have two copies of +bootloader in SD/eMMC and switch between them. The switch is triggered +either by the BootROM in case the bootloader image is faulty OR can be +enforced by the user. + +Operation +--------- + #. Upon Power-On Reset (POR) + + - SRC_GPR10 bit PERSIST_SECONDARY_BOOT is set to 0 + - BootROM attempts to start bootloader A-copy + + - if A-copy valid + + - BootROM starts A-copy + - END + + - if A-copy NOT valid + + - BootROM sets SRC_GPR10 bit PERSIST_SECONDARY_BOOT to 1 + - BootROM triggers WARM reset, GOTO 1) + - END + + #. Upon COLD Reset + + - GOTO 1) + - END + + #. Upon WARM Reset + + - SRC_GPR10 bit PERSIST_SECONDARY_BOOT is retained + + - if SRC_GPR10 bit PERSIST_SECONDARY_BOOT is 0 + + - BootROM attempts to start bootloader A-copy + + - if A-copy valid + + - BootROM starts A-copy + - END + + - if A-copy NOT valid + + - BootROM sets SRC_GPR10 bit PERSIST_SECONDARY_BOOT to 1 + - BootROM triggers WARM reset. GOTO 1.3) + - END + + - if SRC_GPR10 bit PERSIST_SECONDARY_BOOT is 1 + + - BootROM attempts to start bootloader B-copy + + - if B-copy valid + + - BootROM starts B-copy + - END + + - if B-copy NOT valid + - System hangs + - END + +Setup +----- +The bootloader A-copy must be placed at predetermined offset in SD/eMMC. The +bootloader B-copy area offset is determined by an offset stored in Secondary +Image Table (SIT). The SIT must be placed at predetermined offset in SD/eMMC. + +The following table contains offset of SIT, bootloader A-copy and recommended +bootloader B-copy offset. The offsets are in 512 Byte sector units (that is +offset 0x1 means 512 Bytes from the start of SD/eMMC card data partition). +For details on the addition of two numbers in recommended B-copy offset, see +SIT format below. + ++----------+--------------------+-----------------------+-----------------------------+ +| SoC | SIT offset (fixed) | A-copy offset (fixed) | B-copy offset (recommended) | ++----------+--------------------+-----------------------+-----------------------------+ +| iMX7D | 0x1 | 0x2 | 0x800+0x2 | ++----------+--------------------+-----------------------+-----------------------------+ +| iMX8MM | 0x41 | 0x42 | 0x1000+0x42 | ++----------+--------------------+-----------------------+-----------------------------+ + +SIT format +~~~~~~~~~~ +SIT is a 20 byte long structure containing of 5 32-bit words. Those encode +bootloader B-copy area offset (called "firstSectorNumber"), magic value +(called "tag") that is always 0x00112233, and three unused words set to 0. +SIT is documented in [1] and [2]. Example SIT are below:: + + $ hexdump -vC sit-mx7d.bin + 00000000 00 00 00 00 + 00000004 00 00 00 00 + 00000008 33 22 11 00 <--- This is the "tag" + 0000000c 00 08 00 00 <--- This is the "firstSectorNumber" + 00000010 00 00 00 00 + + $ hexdump -vC sit-mx8mm.bin + 00000000 00 00 00 00 + 00000004 00 00 00 00 + 00000008 33 22 11 00 <--- This is the "tag" + 0000000c 00 10 00 00 <--- This is the "firstSectorNumber" + 00000010 00 00 00 00 + +B-copy area offset ("firstSectorNumber") is offset, in units of 512 Byte +sectors, that is added to the start of boot media when switching between +A-copy and B-copy. For A-copy, this offset is 0x0. For B-copy, this offset +is determined by SIT (e.g. if firstSectorNumber is 0x1000 as it is above +in sit-mx8mm.bin, then the B-copy offset is 0x1000 sectors = 2 MiB). + +Bootloader A-copy (e.g. u-boot.imx or flash.bin) is placed at fixed offset +from A-copy area offset (e.g. 0x2 sectors from sector 0x0 for iMX7D, which +means u-boot.imx A-copy must be written to sector 0x2). + +The same applies to bootloader B-copy, which is placed at fixed offset from +B-copy area offset determined by SIT (e.g. 0x2 sectors from sector 0x800 [see +sit-mx7d.bin example above, this can be changed in SIT firstSectorNumber] for +iMX7D, which means u-boot.imx B-copy must be written to sector 0x802) + +**WARNING:** +B-copy area offset ("firstSectorNumber") is NOT equal to bootloader +(image, which is u-boot.imx or flash.bin) B-copy offset. + +To generate SIT, use for example the following bourne shell printf command:: + +$ printf '\x0\x0\x0\x0\x0\x0\x0\x0\x33\x22\x11\x00\x00\x08\x00\x00\x0\x0\x0\x0' > sit-mx7d.bin +$ printf '\x0\x0\x0\x0\x0\x0\x0\x0\x33\x22\x11\x00\x00\x10\x00\x00\x0\x0\x0\x0' > sit-mx8mm.bin + +Write bootloader A/B copy and SIT to SD/eMMC +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Examples of writing SIT and two copies of bootloader to SD or eMMC: + +- iMX8MM, SD card at /dev/sdX, Linux command line + :: + + $ dd if=sit-mx8mm.bin of=/dev/sdX bs=512 seek=65 + $ dd if=flash.bin of=/dev/sdX bs=512 seek=66 + $ dd if=flash.bin of=/dev/sdX bs=512 seek=4162 + +- iMX8MM, eMMC 1 data partition, U-Boot command line + :: + + => mmc partconf 1 0 0 0 + + => dhcp ${loadaddr} sit-mx8mm.bin + => mmc dev 1 + => mmc write ${loadaddr} 0x41 0x1 + + => dhcp ${loadaddr} flash.bin + => setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt + => mmc dev 1 + => mmc write ${loadaddr} 0x42 ${blkcnt} + => mmc write ${loadaddr} 0x1042 ${blkcnt} + +WARM reset into B-copy using WDT +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To perform a reboot into B-copy, the PERSIST_SECONDARY_BOOT must be set +in SRC_GPR0 register. Example on iMX8MM:: + + => mw 0x30390098 0x40000000 + +A WARM reset can be triggered using WDT as follows:: + + => mw.w 0x30280000 0x25 + +References +---------- + +.. [1] i.MX 7Dual Applications Processor Reference Manual, Rev. 1, 01/2018 ; section 6.6.5.3.5 Redundant boot support for expansion device +.. [2] i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 ; section 6.1.5.4.5 Redundant boot support for expansion device diff --git a/doc/index.rst b/doc/index.rst index 4c44955d67f..5d5bb73846c 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -87,6 +87,17 @@ implementation. arch/index +Machine-specific doc +-------------------- + +These books provide programming details about machine-specific +implementation. + +.. toctree:: + :maxdepth: 2 + + imx/index + Board-specific doc ------------------ -- 2.30.2

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[PATCH] pico-imx6ul: Pass the PMIC I2C address in pmic_get()
by Fabio Estevam 09 Apr '21

09 Apr '21

Pass "pfuze3000@8" in pmic_get() so that the PMIC node can be found in the devicetree. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- board/technexion/pico-imx6ul/pico-imx6ul.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c index 62a54d0c8eb5..682c88dee78d 100644 --- a/board/technexion/pico-imx6ul/pico-imx6ul.c +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c @@ -159,7 +159,7 @@ int power_init_board(void) struct udevice *dev; int ret, dev_id, rev_id; - ret = pmic_get("pfuze3000", &dev); + ret = pmic_get("pfuze3000@8", &dev); if (ret == -ENODEV) return 0; if (ret != 0) -- 2.25.1

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[PATCH v2 1/2] mx23_olinuxino: enable device tree
by Trevor Woerner 09 Apr '21

09 Apr '21

Add the dts file for the Olimex Olinuxino from the linux kernel, and enable its use in this machine's defconfig. Signed-off-by: Trevor Woerner <twoerner(a)gmail.com> --- Changes in v2: - none --- arch/arm/dts/Makefile | 3 + arch/arm/dts/imx23-olinuxino.dts | 131 +++++++++++++++++++++++++++++++ configs/mx23_olinuxino_defconfig | 3 +- 3 files changed, 136 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx23-olinuxino.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c6710826a0..d5cffc90d4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -651,6 +651,9 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ dtb-$(CONFIG_MX23) += \ imx23-evk.dtb +dtb-$(CONFIG_TARGET_MX23_OLINUXINO) += \ + imx23-olinuxino.dtb + dtb-$(CONFIG_MX28) += \ imx28-xea.dtb diff --git a/arch/arm/dts/imx23-olinuxino.dts b/arch/arm/dts/imx23-olinuxino.dts new file mode 100644 index 0000000000..0729e72f22 --- /dev/null +++ b/arch/arm/dts/imx23-olinuxino.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam(a)freescale.com> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "imx23.dtsi" + +/ { + model = "i.MX23 Olinuxino Low Cost Board"; + compatible = "olimex,imx23-olinuxino", "fsl,imx23"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x04000000>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: spi@80010000 { + compatible = "fsl,imx23-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; + bus-width = <4>; + broken-cd; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_GPMI_ALE__GPIO_0_17 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + led_pin_gpio2_1: led_gpio2_1@0 { + reg = <0>; + fsl,pinmux-ids = < + MX23_PAD_SSP1_DETECT__GPIO_2_1 + >; + fsl,drive-strength = <MXS_DRIVE_4mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + }; + + ssp1: spi@80034000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx23-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + }; + }; + + apbx@80040000 { + lradc@80050000 { + status = "okay"; + }; + + i2c: i2c@80058000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins_b>; + status = "okay"; + }; + + duart: serial@80070000 { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; + }; + + auart0: serial@8006c000 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + dr_mode = "host"; + vbus-supply = <&reg_usb0_vbus>; + status = "okay"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb0_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ + gpio = <&gpio0 17 0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_gpio2_1>; + + user { + label = "green"; + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + }; +}; diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 0da54c9e76..2bf6818ee3 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_TEXT_BASE=0x00001000 CONFIG_TARGET_MX23_OLINUXINO=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx23-olinuxino" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_ARCH_MISC_INIT=y @@ -24,6 +25,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y @@ -44,4 +46,3 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y -CONFIG_OF_LIBFDT=y -- 2.30.0.rc0

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[PATCH v1] imx: bootaux fix elf loading
by Max Krummenacher 09 Apr '21

09 Apr '21

This reverts the arch/arm/mach-imx/imx_bootaux.c changes of commit 805b3cac1e0c. The loader function name was changed so that it does not clash with the generically available function in lib/elf.c. imx-bootaux loads an elf file linked for an auxilary core. Thus the loader function requires address translation from the auxilary core's address space to where those are mapped into U-Boot's address space. So the elf loader is specific and must not be replaced with a generic loader which doesn't provide the address translation functionality. Fixes commit 805b3cac1e0c ("lib: elf: Move the generic elf loading/validating functions to lib") Signed-off-by: Max Krummenacher <max.krummenacher(a)toradex.com> --- arch/arm/mach-imx/imx_bootaux.c | 67 ++++++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index e1fc4b3e19a..30fb45d48c2 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -14,6 +14,71 @@ #include <linux/compiler.h> #include <cpu_func.h> +#ifndef CONFIG_IMX8M +const __weak struct rproc_att hostmap[] = { }; + +static const struct rproc_att *get_host_mapping(unsigned long auxcore) +{ + const struct rproc_att *mmap = hostmap; + + while (mmap && mmap->size) { + if (mmap->da <= auxcore && + mmap->da + mmap->size > auxcore) + return mmap; + mmap++; + } + + return NULL; +} + +/* + * A very simple elf loader for the auxilary core, assumes the image + * is valid, returns the entry point address. + * Translates load addresses in the elf file to the U-Boot address space. + */ +static unsigned long load_elf_image_m_core_phdr(unsigned long addr) +{ + Elf32_Ehdr *ehdr; /* ELF header structure pointer */ + Elf32_Phdr *phdr; /* Program header structure pointer */ + int i; + + ehdr = (Elf32_Ehdr *)addr; + phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i, ++phdr) { + const struct rproc_att *mmap = get_host_mapping(phdr->p_paddr); + void *dst, *src; + + if (phdr->p_type != PT_LOAD) + continue; + + if (!mmap) { + printf("Invalid aux core address: %08x", + phdr->p_paddr); + return 0; + } + + dst = (void *)(phdr->p_paddr - mmap->da) + mmap->sa; + src = (void *)addr + phdr->p_offset; + + debug("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + + if (phdr->p_filesz) + memcpy(dst, src, phdr->p_filesz); + if (phdr->p_filesz != phdr->p_memsz) + memset(dst + phdr->p_filesz, 0x00, + phdr->p_memsz - phdr->p_filesz); + flush_cache((unsigned long)dst & + ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(phdr->p_filesz, CONFIG_SYS_CACHELINE_SIZE)); + } + + return ehdr->e_entry; +} +#endif + int arch_auxiliary_core_up(u32 core_id, ulong addr) { ulong stack, pc; @@ -31,7 +96,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) */ if (valid_elf_image(addr)) { stack = 0x0; - pc = load_elf_image_phdr(addr); + pc = load_elf_image_m_core_phdr(addr); if (!pc) return CMD_RET_FAILURE; -- 2.20.1

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[PATCH 1/2] mmc: fsl_esdhc_imx: remove redundant cmd11 related code.
by haibo.chen＠nxp.com 09 Apr '21

09 Apr '21

From: Haibo Chen <haibo.chen(a)nxp.com> Common code already handle the voltage switch sequence based on spec, so remove the redundant voltage switch code. Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/fsl_esdhc_imx.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 637537d262..722f33c68c 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -521,15 +521,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, goto out; } - /* Switch voltage to 1.8V if CMD11 succeeded */ - if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { - esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); - - printf("Run CMD11 1.8V switch\n"); - /* Sleep for 5 ms - max time for card to switch to 1.8V */ - udelay(5000); - } - /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { int timeout = 50000; -- 2.17.1

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[PATCH 1/2] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output
by haibo.chen＠nxp.com 09 Apr '21

09 Apr '21

From: Haibo Chen <haibo.chen(a)nxp.com> For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card clock output. After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"), we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON, after CMD11, hardware will gate off the card clock automatically, so card do not detect the clock off/on behavior, so will draw the data0 line low until next command. Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support") Tested-by: Tim Harvey <tharvey(a)gateworks.com> Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/fsl_esdhc_imx.c | 29 +++++++++++++++++++++-------- include/fsl_esdhc_imx.h | 2 ++ 2 files changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index e0e132698e..af36558b3c 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -654,7 +654,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); #ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN); + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); #else esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); #endif @@ -666,7 +669,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n"); #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #else esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -721,8 +724,14 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); struct fsl_esdhc *regs = priv->esdhc_regs; u32 val; + u32 tmp; + int ret; if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET); /* @@ -740,6 +749,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) pr_warn("HS400 strobe DLL status REF not lock!\n"); if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) pr_warn("HS400 strobe DLL status SLV not lock!\n"); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); } } @@ -963,14 +973,18 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #ifdef MMC_SUPPORTS_TUNING if (mmc->clk_disable) { #ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN); + u32 tmp; + + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); #else esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); #endif } else { #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | - VENDORSPEC_CKEN); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #else esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -1046,7 +1060,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #ifndef CONFIG_FSL_USDHC esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); #else - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #endif /* Set the initial clock speed */ @@ -1184,8 +1198,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, esdhc_write32(&regs->autoc12err, 0); esdhc_write32(&regs->clktunectrlstatus, 0); #else - esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | - VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #endif if (priv->vs18_enable) diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 45ed635a77..b092034464 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -39,6 +39,7 @@ #define VENDORSPEC_HCKEN 0x00001000 #define VENDORSPEC_IPGEN 0x00000800 #define VENDORSPEC_INIT 0x20007809 +#define VENDORSPEC_FRC_SDCLK_ON 0x00000100 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -96,6 +97,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDOFF (0x00000080) #define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) -- 2.17.1

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[PATCH] ARM: pcm058: Match mainline Linux NAND ECC layout/behaviour
by Niel Fourie 09 Apr '21

09 Apr '21

Enabled "fsl,legacy-bch-geometry" in U-Boot device tree overlay to match the legacy BCH geometry layout, which mainline Linux applies when "fsl,use-minimum-ecc" is not specified in the device tree. Reinstated SYS_NAND_ONFI_DETECTION, which when disabled, masked the mismatch on SOMs with Winbond NAND flash chips. Signed-off-by: Niel Fourie <lusus(a)denx.de> --- arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi | 5 +++++ include/configs/pcm058.h | 1 + 2 files changed, 6 insertions(+) diff --git a/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi b/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi index 8555be16966..0bea652beea 100644 --- a/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi +++ b/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi @@ -40,3 +40,8 @@ &m25p80 { u-boot,dm-spl; }; + +&gpmi { + fsl,legacy-bch-geometry; +}; + diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 4f03699117b..bc48e809498 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -19,6 +19,7 @@ /* Enable NAND support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_ONFI_DETECTION /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -- 2.30.2

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[PATCH 1/2] stm32mp: update uart number in trace of serial device not found
by Patrick Delaunay 09 Apr '21

09 Apr '21

Align the uart number in the trace of setup_boot_mode() with the name of the uart/usart device (start at 1) and not with the instance value (start at 0), i.e. the serial device sequence number and the index in serial_addr[]. Fixes: f49eb16c17e2c ("stm32mp: stm32prog: replace alias by serial device sequence number") Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/mach-stm32mp/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 897ec13ad8..2f05c5e91b 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -503,7 +503,7 @@ static void setup_boot_mode(void) gd->flags &= ~(GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE); printf("uart%d = %s not found in device tree!\n", - instance, cmd); + instance + 1, cmd); break; } sprintf(cmd, "%d", dev_seq(dev)); -- 2.17.1

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