September 2020 - U-Boot

[PATCH] musb-new: Use predefined configuration data for SUN50I_H6
by Roman Stratiienko 21 Sep '20

21 Sep '20

Same was done in the kernel for all devices compatible with 'allwinner,sun8i-a33-musb' at [1] and [2]. Fixes musb initialization on H6 SOC. [1] - https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drive… [2] - https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drive… Signed-off-by: Roman Stratiienko <r.stratiienko(a)gmail.com> --- CC: Ondrej Jirman <megous(a)megous.com> CC: Icenowy Zheng <icenowy(a)aosc.io> CC: Marek Vasut <marex(a)denx.de> CC: linux-sunxi(a)googlegroups.com Hello community, '$ fastboot usb 0' command works, but host still doesn't see any USB devices. Does anyone have any suggestions where to look? --- drivers/usb/musb-new/musb_regs.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h index c4d7203b85..5f012f3b41 100644 --- a/drivers/usb/musb-new/musb_regs.h +++ b/drivers/usb/musb-new/musb_regs.h @@ -432,7 +432,9 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase) static inline u8 musb_read_configdata(void __iomem *mbase) { #if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T || \ - defined CONFIG_MACH_SUNXI_H3_H5 || defined CONFIG_MACH_SUN50I + defined CONFIG_MACH_SUNXI_H3_H5 || defined CONFIG_MACH_SUN50I || \ + defined CONFIG_MACH_SUN50I_H6 + /* <Sigh> allwinner saves a reg, and we need to hardcode this */ return 0xde; #else -- 2.25.1

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[PATCH v2] cmd: acpi: Print revisions in hex format
by Andy Shevchenko 21 Sep '20

21 Sep '20

The revisions are usually dates in hex-decimal format representing YYYYmmdd. Print them in hex to see this clearly. Before: ... FACP 000e5420 0000f4 (v06 U-BOOT U-BOOTBL 538970376 INTL 0) DSDT 000e4780 000ba0 (v02 U-BOOT U-BOOTBL 65536 INTL 538968870) ... After: ... FACP 000e5420 0000f4 (v06 U-BOOT U-BOOTBL 20200908 INTL 0) DSDT 000e4780 000ba0 (v02 U-BOOT U-BOOTBL 10000 INTL 20200326) ... Fixes: 0b885bcfd9b0 ("acpi: Add an acpi command") Cc: Wolfgang Wallner <wolfgang.wallner(a)br-automation.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- v2: fixed test cases as well (Bin) cmd/acpi.c | 2 +- test/dm/acpi.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/cmd/acpi.c b/cmd/acpi.c index 085a3a650d1a..a3419b42b556 100644 --- a/cmd/acpi.c +++ b/cmd/acpi.c @@ -26,7 +26,7 @@ static void dump_hdr(struct acpi_table_header *hdr) printf("%.*s %08lx %06x", ACPI_NAME_LEN, hdr->signature, (ulong)map_to_sysmem(hdr), hdr->length); if (has_hdr) { - printf(" (v%02d %.6s %.8s %u %.4s %d)\n", hdr->revision, + printf(" (v%02d %.6s %.8s %x %.4s %x)\n", hdr->revision, hdr->oem_id, hdr->oem_table_id, hdr->oem_revision, hdr->aslc_id, hdr->aslc_revision); } else { diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 16aa1616c948..1f252a8d4540 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -366,21 +366,21 @@ static int dm_test_acpi_cmd_list(struct unit_test_state *uts) ut_assert_nextline("RSDP %08lx %06lx (v02 U-BOOT)", addr, sizeof(struct acpi_rsdp)); addr = ALIGN(addr + sizeof(struct acpi_rsdp), 16); - ut_assert_nextline("RSDT %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)", + ut_assert_nextline("RSDT %08lx %06lx (v01 U-BOOT U-BOOTBL %x INTL 0)", addr, sizeof(struct acpi_table_header) + 3 * sizeof(u32), U_BOOT_BUILD_DATE); addr = ALIGN(addr + sizeof(struct acpi_rsdt), 16); - ut_assert_nextline("XSDT %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)", + ut_assert_nextline("XSDT %08lx %06lx (v01 U-BOOT U-BOOTBL %x INTL 0)", addr, sizeof(struct acpi_table_header) + 3 * sizeof(u64), U_BOOT_BUILD_DATE); addr = ALIGN(addr + sizeof(struct acpi_xsdt), 64); - ut_assert_nextline("DMAR %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)", + ut_assert_nextline("DMAR %08lx %06lx (v01 U-BOOT U-BOOTBL %x INTL 0)", addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); addr = ALIGN(addr + sizeof(struct acpi_dmar), 16); - ut_assert_nextline("DMAR %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)", + ut_assert_nextline("DMAR %08lx %06lx (v01 U-BOOT U-BOOTBL %x INTL 0)", addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); addr = ALIGN(addr + sizeof(struct acpi_dmar), 16); - ut_assert_nextline("DMAR %08lx %06lx (v01 U-BOOT U-BOOTBL %u INTL 0)", + ut_assert_nextline("DMAR %08lx %06lx (v01 U-BOOT U-BOOTBL %x INTL 0)", addr, sizeof(struct acpi_dmar), U_BOOT_BUILD_DATE); ut_assert_console_end(); -- 2.28.0

2 1

[PATCH v1] cmd: acpi: Print revisions in hex format
by Andy Shevchenko 21 Sep '20

21 Sep '20

The revisions are usually dates in hex-decimal format representing YYYYmmdd. Print them in hex to see this clearly. Before: ... FACP 000e5420 0000f4 (v06 U-BOOT U-BOOTBL 538970376 INTL 0) DSDT 000e4780 000ba0 (v02 U-BOOT U-BOOTBL 65536 INTL 538968870) ... After: ... FACP 000e5420 0000f4 (v06 U-BOOT U-BOOTBL 20200908 INTL 0) DSDT 000e4780 000ba0 (v02 U-BOOT U-BOOTBL 10000 INTL 20200326) ... Fixes: 0b885bcfd9b0 ("acpi: Add an acpi command") Cc: Wolfgang Wallner <wolfgang.wallner(a)br-automation.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- cmd/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/acpi.c b/cmd/acpi.c index 085a3a650d1a..a3419b42b556 100644 --- a/cmd/acpi.c +++ b/cmd/acpi.c @@ -26,7 +26,7 @@ static void dump_hdr(struct acpi_table_header *hdr) printf("%.*s %08lx %06x", ACPI_NAME_LEN, hdr->signature, (ulong)map_to_sysmem(hdr), hdr->length); if (has_hdr) { - printf(" (v%02d %.6s %.8s %u %.4s %d)\n", hdr->revision, + printf(" (v%02d %.6s %.8s %x %.4s %x)\n", hdr->revision, hdr->oem_id, hdr->oem_table_id, hdr->oem_revision, hdr->aslc_id, hdr->aslc_revision); } else { -- 2.28.0

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[PATCH 00/11] powerpc: Remove some platforms support
by Priyanka Jain 21 Sep '20

21 Sep '20

Remove some of NXP powerpc platforms support which are no longer maintained. Previous versions of uboot are recommended for use Priyanka Jain (11): board/freescale: Remove p1023rdb board support configs: Remove P1010RDB secure boot configs board/freescale: Remove P1025RDB board support board/freescale: Remove P1020UTM board support board/freescale: Remove P1020MBG board support board/freescale: Remove P1021RDB board support board/freescale: Remove P1024RDB board support configs: Remove P3041DS secure boot configs powerpc:Remove P4080DS secure boot configs board/freescale: Remove P5020DS board support configs: Remove P5040DS secure boot configs arch/powerpc/cpu/mpc85xx/Kconfig | 61 ---- board/freescale/common/Makefile | 1 - board/freescale/corenet_ds/Kconfig | 15 - board/freescale/corenet_ds/MAINTAINERS | 10 - board/freescale/corenet_ds/Makefile | 2 - board/freescale/corenet_ds/p5020ds_ddr.c | 15 - board/freescale/corenet_ds/rcw_p5020ds.cfg | 11 - board/freescale/p1010rdb/MAINTAINERS | 12 - board/freescale/p1023rdb/Kconfig | 12 - board/freescale/p1023rdb/MAINTAINERS | 6 - board/freescale/p1023rdb/Makefile | 8 - board/freescale/p1023rdb/ddr.c | 85 ----- board/freescale/p1023rdb/law.c | 17 - board/freescale/p1023rdb/p1023rdb.c | 160 --------- board/freescale/p1023rdb/tlb.c | 98 ----- board/freescale/p1_p2_rdb_pc/Kconfig | 7 +- board/freescale/p1_p2_rdb_pc/MAINTAINERS | 26 -- board/freescale/p1_p2_rdb_pc/README | 2 - board/freescale/p1_p2_rdb_pc/ddr.c | 7 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 114 ------ board/freescale/p1_p2_rdb_pc/tlb.c | 4 +- .../P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig | 65 ---- .../P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig | 64 ---- ...010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig | 66 ---- configs/P1010RDB-PA_NAND_SECBOOT_defconfig | 63 ---- configs/P1010RDB-PA_NOR_SECBOOT_defconfig | 61 ---- .../P1010RDB-PA_SPIFLASH_SECBOOT_defconfig | 64 ---- .../P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig | 65 ---- .../P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig | 64 ---- ...010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig | 66 ---- configs/P1010RDB-PB_NAND_SECBOOT_defconfig | 63 ---- configs/P1010RDB-PB_NOR_SECBOOT_defconfig | 62 ---- .../P1010RDB-PB_SPIFLASH_SECBOOT_defconfig | 64 ---- configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 69 ---- configs/P1020MBG-PC_36BIT_defconfig | 57 --- configs/P1020MBG-PC_SDCARD_defconfig | 67 ---- configs/P1020MBG-PC_defconfig | 55 --- configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 69 ---- configs/P1020UTM-PC_36BIT_defconfig | 57 --- configs/P1020UTM-PC_SDCARD_defconfig | 67 ---- configs/P1020UTM-PC_defconfig | 55 --- configs/P1021RDB-PC_36BIT_NAND_defconfig | 86 ----- configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 81 ----- configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 83 ----- configs/P1021RDB-PC_36BIT_defconfig | 69 ---- configs/P1021RDB-PC_NAND_defconfig | 84 ----- configs/P1021RDB-PC_SDCARD_defconfig | 79 ---- configs/P1021RDB-PC_SPIFLASH_defconfig | 81 ----- configs/P1021RDB-PC_defconfig | 67 ---- configs/P1023RDB_defconfig | 50 --- configs/P1024RDB_36BIT_defconfig | 63 ---- configs/P1024RDB_NAND_defconfig | 78 ---- configs/P1024RDB_SDCARD_defconfig | 72 ---- configs/P1024RDB_SPIFLASH_defconfig | 74 ---- configs/P1024RDB_defconfig | 61 ---- configs/P1025RDB_36BIT_defconfig | 65 ---- configs/P1025RDB_NAND_defconfig | 81 ----- configs/P1025RDB_SDCARD_defconfig | 74 ---- configs/P1025RDB_SPIFLASH_defconfig | 77 ---- configs/P1025RDB_defconfig | 63 ---- configs/P3041DS_NAND_SECURE_BOOT_defconfig | 62 ---- configs/P3041DS_SECURE_BOOT_defconfig | 60 ---- configs/P4080DS_SECURE_BOOT_defconfig | 59 --- configs/P5020DS_NAND_SECURE_BOOT_defconfig | 63 ---- configs/P5020DS_NAND_defconfig | 60 ---- configs/P5020DS_SDCARD_defconfig | 58 --- configs/P5020DS_SECURE_BOOT_defconfig | 60 ---- configs/P5020DS_SPIFLASH_defconfig | 59 --- configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 53 --- configs/P5020DS_defconfig | 57 --- configs/P5040DS_NAND_SECURE_BOOT_defconfig | 63 ---- configs/P5040DS_SECURE_BOOT_defconfig | 60 ---- include/configs/P1023RDB.h | 338 ------------------ include/configs/P5020DS.h | 25 -- include/configs/p1_p2_rdb_pc.h | 106 +----- 75 files changed, 7 insertions(+), 4500 deletions(-) delete mode 100644 board/freescale/corenet_ds/p5020ds_ddr.c delete mode 100644 board/freescale/corenet_ds/rcw_p5020ds.cfg delete mode 100644 board/freescale/p1023rdb/Kconfig delete mode 100644 board/freescale/p1023rdb/MAINTAINERS delete mode 100644 board/freescale/p1023rdb/Makefile delete mode 100644 board/freescale/p1023rdb/ddr.c delete mode 100644 board/freescale/p1023rdb/law.c delete mode 100644 board/freescale/p1023rdb/p1023rdb.c delete mode 100644 board/freescale/p1023rdb/tlb.c delete mode 100644 configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PA_NAND_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PA_NOR_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_NAND_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_NOR_SECBOOT_defconfig delete mode 100644 configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig delete mode 100644 configs/P1020MBG-PC_36BIT_SDCARD_defconfig delete mode 100644 configs/P1020MBG-PC_36BIT_defconfig delete mode 100644 configs/P1020MBG-PC_SDCARD_defconfig delete mode 100644 configs/P1020MBG-PC_defconfig delete mode 100644 configs/P1020UTM-PC_36BIT_SDCARD_defconfig delete mode 100644 configs/P1020UTM-PC_36BIT_defconfig delete mode 100644 configs/P1020UTM-PC_SDCARD_defconfig delete mode 100644 configs/P1020UTM-PC_defconfig delete mode 100644 configs/P1021RDB-PC_36BIT_NAND_defconfig delete mode 100644 configs/P1021RDB-PC_36BIT_SDCARD_defconfig delete mode 100644 configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig delete mode 100644 configs/P1021RDB-PC_36BIT_defconfig delete mode 100644 configs/P1021RDB-PC_NAND_defconfig delete mode 100644 configs/P1021RDB-PC_SDCARD_defconfig delete mode 100644 configs/P1021RDB-PC_SPIFLASH_defconfig delete mode 100644 configs/P1021RDB-PC_defconfig delete mode 100644 configs/P1023RDB_defconfig delete mode 100644 configs/P1024RDB_36BIT_defconfig delete mode 100644 configs/P1024RDB_NAND_defconfig delete mode 100644 configs/P1024RDB_SDCARD_defconfig delete mode 100644 configs/P1024RDB_SPIFLASH_defconfig delete mode 100644 configs/P1024RDB_defconfig delete mode 100644 configs/P1025RDB_36BIT_defconfig delete mode 100644 configs/P1025RDB_NAND_defconfig delete mode 100644 configs/P1025RDB_SDCARD_defconfig delete mode 100644 configs/P1025RDB_SPIFLASH_defconfig delete mode 100644 configs/P1025RDB_defconfig delete mode 100644 configs/P3041DS_NAND_SECURE_BOOT_defconfig delete mode 100644 configs/P3041DS_SECURE_BOOT_defconfig delete mode 100644 configs/P4080DS_SECURE_BOOT_defconfig delete mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig delete mode 100644 configs/P5020DS_NAND_defconfig delete mode 100644 configs/P5020DS_SDCARD_defconfig delete mode 100644 configs/P5020DS_SECURE_BOOT_defconfig delete mode 100644 configs/P5020DS_SPIFLASH_defconfig delete mode 100644 configs/P5020DS_SRIO_PCIE_BOOT_defconfig delete mode 100644 configs/P5020DS_defconfig delete mode 100644 configs/P5040DS_NAND_SECURE_BOOT_defconfig delete mode 100644 configs/P5040DS_SECURE_BOOT_defconfig delete mode 100644 include/configs/P1023RDB.h delete mode 100644 include/configs/P5020DS.h -- 2.17.1

1 11

[PATCH v2 00/16] x86: zboot: Enhance the 'zboot' command
by Simon Glass 21 Sep '20

21 Sep '20

This command is currently monolithic and does not support scripts which want to adjust the boot process. This series updates it to be more like 'bootm', in that it has sub-commands for each stage of the boot. This allows some stages to be adjusted or skipped. It also adds a way to dump out the setup block. With these changes it is possible to boot an x86 Chrome OS image from a script. Changes in v2: - Fix comment about argv[0] in do_zboot_parent() - Add a comment explaining the logic for a specified setup-base address Simon Glass (16): x86: Update the bootparam header x86: zimage: Use a state struct to hold the state x86: zimage: Avoid using #ifdef x86: zboot: Move kernel-version code into a function x86: zboot: Correct image type x86: zimage: Disable interrupts just before booting x86: zboot: Set up a sub-command structure x86: zboot: Add a 'go' subcommand x86: zboot: Add an 'info' subcommand x86: zboot: Add an 'setup' subcommand x86: zboot: Set environment variables for image locations x86: zboot: Allow setting a separate setup base address x86: zboot: Add an option to dump the setup information x86: zboot: Allow overriding the command line cros: Update chromium documentation cros: Add information about booting Chrome OS on x86 README | 4 + arch/x86/include/asm/bootparam.h | 25 +- arch/x86/include/asm/e820.h | 1 + arch/x86/include/asm/zimage.h | 30 +- arch/x86/lib/bootm.c | 2 +- arch/x86/lib/zimage.c | 483 +++++++++++++++++++++++++++---- doc/README.chromium | 41 ++- 7 files changed, 520 insertions(+), 66 deletions(-) -- 2.28.0.402.g5ffc5be6b7-goog

4 36

[PATCH] pci: layerscape: Remove the shadow SVR definitiones
by Zhiqiang Hou 21 Sep '20

21 Sep '20

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> This patch moves the SVR definitiones to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- .../arm/include/asm/arch-fsl-layerscape/soc.h | 30 +--------------- .../arm/include/asm/arch-fsl-layerscape/svr.h | 34 +++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/svr.h | 8 +++++ drivers/pci/pcie_layerscape.h | 12 ++----- 4 files changed, 45 insertions(+), 39 deletions(-) create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/svr.h create mode 100644 arch/arm/include/asm/arch-ls102xa/svr.h diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 020548ac6c..6946f30f54 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -16,6 +16,7 @@ #include <asm/arch/immap_lsch3.h> #endif #endif +#include <asm/arch/svr.h> #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE #define gur_in32(a) in_le32(a) @@ -77,35 +78,6 @@ enum boot_src get_boot_src(void); #endif #endif #define SVR_WO_E 0xFFFFFE -#define SVR_LS1012A 0x870400 -#define SVR_LS1043A 0x879200 -#define SVR_LS1023A 0x879208 -/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ -#define SVR_LS1043A_P23 0x879202 -#define SVR_LS1023A_P23 0x87920A -#define SVR_LS1017A 0x870B24 -#define SVR_LS1018A 0x870B20 -#define SVR_LS1027A 0x870B04 -#define SVR_LS1028A 0x870B00 -#define SVR_LS1046A 0x870700 -#define SVR_LS1026A 0x870708 -#define SVR_LS1048A 0x870320 -#define SVR_LS1084A 0x870302 -#define SVR_LS1088A 0x870300 -#define SVR_LS1044A 0x870322 -#define SVR_LS2045A 0x870120 -#define SVR_LS2080A 0x870110 -#define SVR_LS2085A 0x870100 -#define SVR_LS2040A 0x870130 -#define SVR_LS2088A 0x870900 -#define SVR_LS2084A 0x870910 -#define SVR_LS2048A 0x870920 -#define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870918 -#define SVR_LS2041A 0x870914 -#define SVR_LX2160A 0x873600 -#define SVR_LX2120A 0x873620 -#define SVR_LX2080A 0x873602 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/svr.h b/arch/arm/include/asm/arch-fsl-layerscape/svr.h new file mode 100644 index 0000000000..97c9775644 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/svr.h @@ -0,0 +1,34 @@ +#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ +#define _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ + +#define SVR_LS1012A 0x870400 +#define SVR_LS1043A 0x879200 +#define SVR_LS1023A 0x879208 +/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */ +#define SVR_LS1043A_P23 0x879202 +#define SVR_LS1023A_P23 0x87920A +#define SVR_LS1017A 0x870B24 +#define SVR_LS1018A 0x870B20 +#define SVR_LS1027A 0x870B04 +#define SVR_LS1028A 0x870B00 +#define SVR_LS1046A 0x870700 +#define SVR_LS1026A 0x870708 +#define SVR_LS1048A 0x870320 +#define SVR_LS1084A 0x870302 +#define SVR_LS1088A 0x870300 +#define SVR_LS1044A 0x870322 +#define SVR_LS2045A 0x870120 +#define SVR_LS2080A 0x870110 +#define SVR_LS2085A 0x870100 +#define SVR_LS2040A 0x870130 +#define SVR_LS2088A 0x870900 +#define SVR_LS2084A 0x870910 +#define SVR_LS2048A 0x870920 +#define SVR_LS2044A 0x870930 +#define SVR_LS2081A 0x870918 +#define SVR_LS2041A 0x870914 +#define SVR_LX2160A 0x873600 +#define SVR_LX2120A 0x873620 +#define SVR_LX2080A 0x873602 + +#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SVR_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/svr.h b/arch/arm/include/asm/arch-ls102xa/svr.h new file mode 100644 index 0000000000..a069eb2d9e --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/svr.h @@ -0,0 +1,8 @@ +#ifndef _ASM_LS102X_SVR_H_ +#define _ASM_LS102X_SVR_H_ + +#define SVR_LS102XA 0 +#define SVR_VAR_PER_SHIFT 8 +#define SVR_LS102XA_MASK 0x700 + +#endif /* _ASM_LS102X_SVR_H_ */ diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index 0124e8e051..8cdf516d9f 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -10,6 +10,8 @@ #include <pci.h> #include <linux/sizes.h> +#include <asm/arch-fsl-layerscape/svr.h> +#include <asm/arch-ls102xa/svr.h> #ifndef CONFIG_SYS_PCI_MEMORY_BUS #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE @@ -121,16 +123,6 @@ /* CS2 */ #define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */ -#define SVR_LS102XA 0 -#define SVR_VAR_PER_SHIFT 8 -#define SVR_LS102XA_MASK 0x700 -#define SVR_LS2088A 0x870900 -#define SVR_LS2084A 0x870910 -#define SVR_LS2048A 0x870920 -#define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870918 -#define SVR_LS2041A 0x870914 - /* LS1021a PCIE space */ #define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL #define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL -- 2.17.1

3 2

[PATCH v2 1/2] x86: acpi: Fix calculation of DSDT length
by Wolfgang Wallner 21 Sep '20

21 Sep '20

Currently, the calculation for the length of the DSDT table includes any bytes that are added for alignment, but those bytes are not initialized. This is because the DSDT length is calculated after a call to acpi_inc_align(). Split this up into the following sequence: * acpi_inc() * Calculate DSDT length * acpi_align() Signed-off-by: Wolfgang Wallner <wolfgang.wallner(a)br-automation.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Added Reviewed-by tags arch/x86/lib/acpi_table.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 3a93fedfc3..6b827bfa3f 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -427,7 +427,7 @@ ulong write_acpi_tables(ulong start_addr) (char *)&AmlCode + sizeof(struct acpi_table_header), dsdt->length - sizeof(struct acpi_table_header)); - acpi_inc_align(ctx, dsdt->length - sizeof(struct acpi_table_header)); + acpi_inc(ctx, dsdt->length - sizeof(struct acpi_table_header)); /* Pack GNVS into the ACPI table area */ for (i = 0; i < dsdt->length; i++) { @@ -450,6 +450,8 @@ ulong write_acpi_tables(ulong start_addr) dsdt->checksum = 0; dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length); + acpi_align(ctx); + /* * Fill in platform-specific global NVS variables. If this fails we * cannot return the error but this should only happen while debugging. -- 2.28.0

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[PATCH] x86: fsp: Replace e-mmc with emmc in devicetree bindings
by Wolfgang Wallner 21 Sep '20

21 Sep '20

The term eMMC is used inconsistently within the FSP devicetree bindigs (e-mmc and emmc), especially for "emmc-host-max-speed" documentation and code disagree. Change all eMMC instances within the FSP bindings to consistently use "emmc". The term "emmc" is already used a lot within U-Boot, while "e-mmc" is only used in the FSP bindings. Signed-off-by: Wolfgang Wallner <wolfgang.wallner(a)br-automation.com> --- arch/x86/cpu/apollolake/fsp_bindings.c | 6 +++--- doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt | 2 +- doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/cpu/apollolake/fsp_bindings.c b/arch/x86/cpu/apollolake/fsp_bindings.c index bbf04b5009..319c78b95a 100644 --- a/arch/x86/cpu/apollolake/fsp_bindings.c +++ b/arch/x86/cpu/apollolake/fsp_bindings.c @@ -555,7 +555,7 @@ const struct fsp_binding fsp_m_bindings[] = { }, { .type = FSP_UINT8, .offset = offsetof(struct fsp_m_config, e_mmc_trace_len), - .propname = "fspm,e-mmc-trace-len", + .propname = "fspm,emmc-trace-len", }, { .type = FSP_UINT8, .offset = offsetof(struct fsp_m_config, skip_cse_rbp), @@ -1465,11 +1465,11 @@ const struct fsp_binding fsp_s_bindings[] = { }, { .type = FSP_UINT8, .offset = offsetof(struct fsp_s_config, e_mmc_enabled), - .propname = "fsps,e-mmc-enabled", + .propname = "fsps,emmc-enabled", }, { .type = FSP_UINT8, .offset = offsetof(struct fsp_s_config, e_mmc_host_max_speed), - .propname = "fsps,e-mmc-host-max-speed", + .propname = "fsps,emmc-host-max-speed", }, { .type = FSP_UINT8, .offset = offsetof(struct fsp_s_config, ufs_enabled), diff --git a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt index 666400e085..36936f2eb6 100644 --- a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt +++ b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt @@ -174,7 +174,7 @@ Optional properties: - fspm,oem-loading-base: OEM File Loading Address - fspm,oem-file-name: OEM File Name to Load - fspm,mrc-boot-data-ptr: -- fspm,e-mmc-trace-len: eMMC Trace Length +- fspm,emmc-trace-len: eMMC Trace Length 0x0: Long 0x1: Short - fspm,skip-cse-rbp: Skip CSE RBP to support zero sized IBB diff --git a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt index 731a310cf8..b605ed0056 100644 --- a/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt +++ b/doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt @@ -318,7 +318,7 @@ Optional properties: 0x6: warm reset (default) 0xE: cold reset - fsps,sdcard-enabled: SD Card Support (D27:F0) -- fsps,e-mmc-enabled: SeMMC Support (D28:F0) +- fsps,emmc-enabled: SeMMC Support (D28:F0) - fsps,emmc-host-max-speed: eMMC Max Speed 0: HS400(default) 1: HS200 -- 2.28.0

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[PATCH v1] x86: edison: Move config SYS_MALLOC_LEN to Kconfig
by Andy Shevchenko 21 Sep '20

21 Sep '20

This patch moves the the config SYS_MALLOC_LEN to Kconfig as it is already done for zynq arch in commit 01aa5b8f0503 ("Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq"). Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- board/intel/edison/Kconfig | 3 +++ include/configs/edison.h | 4 ---- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/board/intel/edison/Kconfig b/board/intel/edison/Kconfig index ef9b14aa2bfd..05d65445e407 100644 --- a/board/intel/edison/Kconfig +++ b/board/intel/edison/Kconfig @@ -12,6 +12,9 @@ config SYS_SOC config SYS_CONFIG_NAME default "edison" +config SYS_MALLOC_LEN + default 0x08000000 + config SYS_TEXT_BASE default 0x01101000 diff --git a/include/configs/edison.h b/include/configs/edison.h index 606c656a7272..0e1205bdb54c 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -23,10 +23,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) - -/* Environment */ - /* RTC */ #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 -- 2.28.0

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x86: apl: Acessing SPI flash when booting with Coreboot/U-Boot
by Wolfgang Wallner 21 Sep '20

21 Sep '20

Hi Simon, Since commit 609b90a6a9c0 ("x86: spi: Rewrite logic for obtaining the SPI memory map") I have trouble accessing the SPI flash on my Apollo Lake board when booting with Coreboot and having U-Boot as the payload. Accessing the SPI flash returns -91 (EPROTOTYPE). My understanding of what happens is the following: - ich_spi_ofdata_to_platdata() calls ich_spi_get_basics(), the parameter 'can_probe' is hardcoded to true - There is no PCH device in my devicetree (there is also no PCH driver contained in my build) - As can_probe is true, ich_spi_get_basics() tries to find a PCH device and returns -EPROTOTYPE as it finds none As far as I see the PCH is not used in the code paths relevant to Apollo Lake. I think this behavior can not be triggered in a standalone U-Boot on Apollo Lake, as in this case arch_cpu_init_tpl() requires an LPC, which is below the PCH, and so a PCH has to be part of the devicetree anyway. In this case a PCH would be found in ich_spi_get_basics(), but it would not get used. As a quick workaround [1], I have set can_probe hardcoded to false, and with this change I can access the SPI flash again. Do you have any advice on how to fix this? How about making the value for can_probe depend on a check for ich_version == ICHV_APL? regards, Wolfgang [1] Workaround patch: --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -1016,7 +1016,7 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev) #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct ich_spi_priv *priv = dev_get_priv(dev); - ret = ich_spi_get_basics(dev, true, &priv->pch, &plat->ich_version, + ret = ich_spi_get_basics(dev, false, &priv->pch, &plat->ich_version,

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