September 2020 - U-Boot

[PATCH v3 00/17] x86: zboot: Enhance the 'zboot' command
by Simon Glass 22 Sep '20

22 Sep '20

This command is currently monolithic and does not support scripts which want to adjust the boot process. This series updates it to be more like 'bootm', in that it has sub-commands for each stage of the boot. This allows some stages to be adjusted or skipped. It also adds a way to dump out the setup block. With these changes it is possible to boot an x86 Chrome OS image from a script. Changes in v3: - Add a comment about complete_zboot() - Adjust maxargs in this patch - Fix 'summary' typo - Mention that the environment variables are for x86 only - Move command help into the patch for each command - Reduce maxargs to 6 - Split the 'load' command into its own patch - Update two local arrays to be static - Use 'Commandline' instead of 'Commandline' Changes in v2: - Add a comment explaining the logic for a specified setup-base address - Adjust maxargs in this patch - Fix comment about argv[0] in do_zboot_parent() Simon Glass (17): x86: Update the bootparam header x86: zimage: Use a state struct to hold the state x86: zimage: Avoid using #ifdef x86: zboot: Move kernel-version code into a function x86: zboot: Correct image type x86: zimage: Disable interrupts just before booting x86: zboot: Set up a sub-command structure x86: zboot: Add a 'go' subcommand x86: zboot: Add an 'info' subcommand x86: zboot: Add an 'load' subcommand x86: zboot: Add an 'setup' subcommand x86: zboot: Set environment variables for image locations x86: zboot: Allow setting a separate setup base address x86: zboot: Add an option to dump the setup information x86: zboot: Allow overriding the command line cros: Update chromium documentation cros: Add information about booting Chrome OS on x86 README | 4 + arch/x86/include/asm/bootparam.h | 25 +- arch/x86/include/asm/e820.h | 1 + arch/x86/include/asm/zimage.h | 30 +- arch/x86/lib/bootm.c | 2 +- arch/x86/lib/zimage.c | 484 +++++++++++++++++++++++++++---- doc/README.chromium | 41 ++- 7 files changed, 521 insertions(+), 66 deletions(-) -- 2.28.0.526.ge36021eeef-goog

2 23

[PATCH 1/2] tools: socfpgaimage: Add check params function for Arria 10 (v1)
by Ley Foon Tan 22 Sep '20

22 Sep '20

Add check params function for Arria 10 (header v1). >From [1] page 42, entry point offset should be 4 bytes aligned and any value smaller than 0x14 is invalid. Rename existing socfpgaimage_check_params() for v0. [1]: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug… Signed-off-by: Ley Foon Tan <ley.foon.tan(a)intel.com> --- tools/socfpgaimage.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/tools/socfpgaimage.c b/tools/socfpgaimage.c index 6dfd64e31dd5..f71b3d59ddcb 100644 --- a/tools/socfpgaimage.c +++ b/tools/socfpgaimage.c @@ -62,6 +62,9 @@ #define HEADER_OFFSET 0x40 #define VALIDATION_WORD 0x31305341 +/* Minimum and default entry point offset */ +#define ENTRY_POINT_OFFSET 0x14 + static uint8_t buffer_v0[0x10000]; static uint8_t buffer_v1[0x40000]; @@ -275,7 +278,7 @@ static void socfpgaimage_print_header(const void *ptr) printf("Not a sane SOCFPGA preloader\n"); } -static int socfpgaimage_check_params(struct image_tool_params *params) +static int socfpgaimage_check_params_v0(struct image_tool_params *params) { /* Not sure if we should be accepting fflags */ return (params->dflag && (params->fflag || params->lflag)) || @@ -283,6 +286,26 @@ static int socfpgaimage_check_params(struct image_tool_params *params) (params->lflag && (params->dflag || params->fflag)); } +static int socfpgaimage_check_params_v1(struct image_tool_params *params) +{ + /* + * If the entry point is specified, ensure it is >= ENTRY_POINT_OFFSET + * and it is 4 bytes aligned. + */ + if (params->eflag && (params->ep < ENTRY_POINT_OFFSET || + params->ep % 4 != 0)) { + fprintf(stderr, + "Error: Entry point must be greater than 0x%x.\n", + ENTRY_POINT_OFFSET); + return -1; + } + + /* Not sure if we should be accepting fflags */ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)); +} + static int socfpgaimage_check_image_types_v0(uint8_t type) { if (type == IH_TYPE_SOCFPGAIMAGE) @@ -377,7 +400,7 @@ U_BOOT_IMAGE_TYPE( "Altera SoCFPGA Cyclone V / Arria V image support", 0, /* This will be modified by vrec_header() */ (void *)buffer_v0, - socfpgaimage_check_params, + socfpgaimage_check_params_v0, socfpgaimage_verify_header, socfpgaimage_print_header, socfpgaimage_set_header_v0, @@ -392,7 +415,7 @@ U_BOOT_IMAGE_TYPE( "Altera SoCFPGA Arria10 image support", 0, /* This will be modified by vrec_header() */ (void *)buffer_v1, - socfpgaimage_check_params, + socfpgaimage_check_params_v1, socfpgaimage_verify_header, socfpgaimage_print_header, socfpgaimage_set_header_v1, -- 2.19.0

1 1

[PATCH v3 0/7] riscv: Correctly handle IPIs already pending upon boot
by Sean Anderson 22 Sep '20

22 Sep '20

On the K210, the prior stage bootloader does not clear IPIs. This presents a problem, because U-Boot up until this point assumes (with one exception) that IPIs are cleared when it starts. This series attempts to fix this in a robust manner, and fix several concurrency bugs I noticed while fixing these other areas. Heinrich previously submitted a patch addressing part of this problem in [1]. [1] https://patchwork.ozlabs.org/project/uboot/patch/20200811035648.3284-1-xypr… Changes in v3: - Rename riscv_ipi_init_secondary_hart to dummy_pending_ipi_clear - Only compile dummy_pending_ipi_clear when SMP is enabled - Clarify XIP comment - Updated and expanded most commit messages Changes in v2: - Use a valid bit instead of addr to validate IPIs - Make riscv_ipi_init_secondary_hart static - Remove fences after amoswaps - Set gp early with XIP - Clarify comments regarding tp Sean Anderson (7): Revert "riscv: Clear pending interrupts before enabling IPIs" riscv: Match memory barriers between send_ipi_many and handle_ipi riscv: Use a valid bit to ignore already-pending IPIs riscv: Clear pending IPIs on initialization riscv: Consolidate fences into AMOs for available_harts_lock riscv: Ensure gp is NULL or points to valid data riscv: Add some comments to start.S arch/riscv/cpu/cpu.c | 20 +++++++++++++ arch/riscv/cpu/start.S | 58 ++++++++++++++++++++++++++++-------- arch/riscv/include/asm/smp.h | 7 +++++ arch/riscv/lib/interrupts.c | 3 +- arch/riscv/lib/smp.c | 16 +++++++++- 5 files changed, 89 insertions(+), 15 deletions(-) -- 2.28.0

3 12

[PATCH v3 00/10] riscv: Add SPI support for Kendryte K210
by Sean Anderson 21 Sep '20

21 Sep '20

This series adds support for SPI on the Kendryte K210. This covers the MMC slot (currently broken) and SPI flash on the Sipeed Maix Bit. This series makes significant changes to the designware SPI driver. I would really appreciate if the maintainers I CC'd could test this series and ensure that SPI still works on all their devices. I have tried my best not to affect existing devices, but I'd rather find out if this breaks stuff now rather than later. In particular: Ley Foon Tan, can you try using dw_spi_dw32_init with the Stratix 10 and Agilex SoCFPGAs? From their documentation, it is unclear whether one should use the DFS or DFS_32 field. I have used dw_spi_dw16_init for these devices, since that keeps the same behavior as before this series, but I am interested in seeing whether the DFS_32 works. Gregory Clement, Lars Povlsen, and Horatiu Vultur, can you confirm the register layout of ctrlr0 and version of the device on the MSCC Ocelot and Jaguar 2? I couldn't find any documentation for the device on those SoCs online. Alexey Brodkin and Eugeniy Paltsev, can you confirm the register layout of ctrlr0 and version of the device on ARC SoCs? I couldn't find any documentation for the device on those SoCs online. In addition, can you clarify the nature of SSI_MAX_XFER_SIZE? Is it set once before the device is fabricated, or is it set at runtime? Is there any way to detect it at runtime? Is my supposition that it was introduced in version 3.23 correct? Have there been any other breaking changes which I have overlooked? I tried investigating some of this, but I was unable to find any definitive ruling on the matter. All I could find was this forum post which doesn't really explain anything [1]. [1] https://community.intel.com/t5/Intel-Makers/D2000-SPI-word-frame-size/td-p/… This series was previously part of https://patchwork.ozlabs.org/project/uboot/list/?series=161576 This series depends on https://patchwork.ozlabs.org/project/uboot/list/?series=185489 Known bugs: - The MMC cannot be accessed with the dw_spi driver Changes in v3: - Lower the log level of some messages - Prefix user-facing logs with SPI@<address> - Rebase onto U-Boot master - Remove env and bootcmd configuration. I'm going to punt on those for now, since I haven't worked out the best way to boot with SPI yet. Those settings may be added back in a follow-up patch. - Reword error messages as "message (error %d)" - Synchronize compatible strings between docs and driver - Use constant 0x10000 instead of SZ_64K. The latter is not included on some platforms and I'm too lazy to figure out what the correct header is. Changes in v2: - Add Gigadevice SPI chips to dependencies - Add external gpio cs support - Clean up exec_op - Configure ctrlr0 register layout based on compatible string - Convert debug calls to log_ instead of removing the ones which affect timing - Document new compatible strings - Limit data transfers to 64k - Remove broken-wp property (implicit due to no wp gpio) - Remove ctrl0 field offsets from device tree - Switch to new compatible strings - Switch to new pinmux binding style Sean Anderson (10): spi: dw: Convert calls to debug to log_* spi: dw: Rename "cs-gpio" to "cs-gpios" spi: dw: Use generic function to read reg address spi: dw: Rearrange struct dw_spi_priv spi: dw: Add SoC-specific compatible strings spi: dw: Configure ctrlr0 layout based on compatible string spi: dw: Document devicetree binding spi: dw: Add mem_ops riscv: Add device tree bindings for SPI riscv: Add support for SPI on Kendryte K210 arch/arc/dts/axs10x_mb.dtsi | 5 +- arch/arc/dts/hsdk-common.dtsi | 5 +- arch/arm/dts/socfpga.dtsi | 6 +- arch/arm/dts/socfpga_agilex.dtsi | 6 +- arch/arm/dts/socfpga_arria10.dtsi | 6 +- arch/arm/dts/socfpga_stratix10.dtsi | 6 +- arch/mips/dts/mscc,jr2.dtsi | 2 +- arch/mips/dts/mscc,ocelot.dtsi | 2 +- arch/riscv/dts/k210-maix-bit.dts | 46 ++- arch/riscv/dts/k210.dtsi | 15 +- board/sipeed/maix/Kconfig | 11 + configs/sipeed_maix_bitm_defconfig | 1 + doc/board/sipeed/maix.rst | 46 +++ .../spi/snps,dw-apb-ssi.txt | 56 +++ drivers/spi/designware_spi.c | 385 +++++++++++++++--- 15 files changed, 511 insertions(+), 87 deletions(-) create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt -- 2.28.0

2 11

[ANN] U-Boot v2020.10-rc5 released
by Tom Rini 21 Sep '20

21 Sep '20

Hey all, It's release day and time for the final -rc prior to the final. I see a few bugfixes out there I do want to grab related to PowerPC. I'm going to pull this -rc in to -next as well as that should also unblock some other changes as it pulls in a build time fix for rockchip in some cases. Once again, for a changelog, git log --merges v2020.10-rc4..v2020.10-rc5 and as always, I ask for more details in the PRs people send me so I can put them in the merge commit. Things look on track for release on October 5th, thanks all! -- Tom

1 0

Please pull u-boot-x86
by Bin Meng 21 Sep '20

21 Sep '20

Hi Tom, This PR contains the following x86 changes for v2020.10: - Several ACPI bug fixes - Intel edison: Move config SYS_MALLOC_LEN to Kconfig - Use "emmc" in ApolloLake FSP devicetree bindings Azure results: PASS https://dev.azure.com/bmeng/GitHub/_build/results?buildId=292&view=results The following changes since commit 400f84c5baaec9b8a9f30e4ea77785e6f9e00c4b: Merge tag 'efi-2020-10-rc5-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi (2020-09-19 08:35:20 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-x86 for you to fetch changes up to 40edea3a07ebb89e86c9bde8c94000c8f6613be7: x86: acpi: Add memset to initialize SPCR table (2020-09-21 16:41:36 +0800) ---------------------------------------------------------------- Andy Shevchenko (2): x86: edison: Move config SYS_MALLOC_LEN to Kconfig cmd: acpi: Print revisions in hex format Wolfgang Wallner (3): x86: fsp: Replace e-mmc with emmc in devicetree bindings x86: acpi: Fix calculation of DSDT length x86: acpi: Add memset to initialize SPCR table arch/x86/cpu/apollolake/fsp_bindings.c | 6 +++--- arch/x86/lib/acpi_table.c | 6 +++++- board/intel/edison/Kconfig | 3 +++ cmd/acpi.c | 2 +- doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-m.txt | 2 +- doc/device-tree-bindings/fsp/fsp2/apollolake/fsp-s.txt | 2 +- include/configs/edison.h | 4 ---- test/dm/acpi.c | 10 +++++----- 8 files changed, 19 insertions(+), 16 deletions(-) Regards, Bin

2 1

[PATCH 1/1] rng: stm32mp1: use log() instead of printf()
by Heinrich Schuchardt 21 Sep '20

21 Sep '20

The logging system provides flexible filtering and enhanced output. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- drivers/rng/stm32mp1_rng.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/rng/stm32mp1_rng.c b/drivers/rng/stm32mp1_rng.c index 7ef7ff9756..c1bae180f7 100644 --- a/drivers/rng/stm32mp1_rng.c +++ b/drivers/rng/stm32mp1_rng.c @@ -3,6 +3,8 @@ * Copyright (c) 2019, Linaro Limited */ +#define LOG_CATEGORY UCLASS_RNG + #include <common.h> #include <clk.h> #include <dm.h> @@ -53,7 +55,7 @@ static int stm32_rng_read(struct udevice *dev, void *data, size_t len) for (i = 0; i < 12; i++) readl(pdata->base + RNG_DR); if (readl(pdata->base + RNG_SR) & RNG_SR_SEIS) { - printf("RNG Noise"); + log_err("RNG Noise"); return -EIO; } /* start again */ -- 2.28.0

3 3

[PATCH] net: ravb: Fix NULL pointer access
by Biju Das 21 Sep '20

21 Sep '20

Some phy's like rtl8211e do not support writeext() callback. Add a check to avoid null pointer access before calling writeext() callback. Signed-off-by: Biju Das <biju.das.jz(a)bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj(a)bp.renesas.com> --- drivers/net/ravb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 886f53ee82..623d377897 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -438,7 +438,8 @@ static int ravb_config(struct udevice *dev) writel(mask, eth->iobase + RAVB_REG_ECMR); - phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19); + if (phy->drv->writeext) + phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19); return 0; } -- 2.17.1

3 12

Pending x86 patches
by Simon Glass 21 Sep '20

21 Sep '20

Hi Bin, At present I have a lot of x86 patches pending, such that it is very difficult to make further progress. I'd like to suggest that we get these into a 'next' branch ASAP so I can finalise the coral ACPI support. I'm happy to do this if you are busy. If there are review comments we can squash them in before applying to master. Regards, Simon

2 2

[PATCH 0/5] sunxi: video: Add V3S simple-framebuffer
by Martin Cerveny 21 Sep '20

21 Sep '20

There are patches to enable "allwinner,simple-framebuffer" with "mixer0-lcd0" pipeline for V3s. First patch corrects "2x pll" loop for pixelclock search. Second patch enable PWM0 (for backlight support). Third patch is the main extension to code and build: - V3s has 2x VI and 1x UI channels (use UI channel), so use third channel. - V3s uses PLL3 (PLL_VIDEO) for both DE2 and TCON0 pixelclock. PLL10 is used for DDR2. - V3s supports resolution upto 1024x1024. Also scale down memory requirements for V3s (64MB embedded DDR2) - V3s does not support HDMI. Fourth patch extends u-boot DTS (linux DTS patch coming soon) Fifth patch enable PWM drivers and corrects CONFIG_VIDEO_LCD_DCLK_PHASE. Tested with "Lichee Zero" V3s and 480x272 LCD (not configured DRM DE2/TCON0/panel in linux DTS). - https://github.com/mcerveny/u-boot/tree/simplefb_v3s_v1 Martin Cerveny (5): sunxi: video: No double clock on DE2 pwm: sunxi: v3s: Enable PWM0 sunxi: video: v3s: Enable LCD support arm: dts: v3s: Add support for simple-framebuffer with DE2/TCON sunxi: add drivers and configs needed for LCD display arch/arm/dts/sun8i-v3s.dtsi | 128 +++++++++++++++++- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +- arch/arm/include/asm/arch-sunxi/gpio.h | 2 + arch/arm/mach-sunxi/Kconfig | 1 + configs/LicheePi_Zero_defconfig | 4 + drivers/pwm/sunxi_pwm.c | 3 + drivers/video/sunxi/lcdc.c | 7 +- drivers/video/sunxi/sunxi_de2.c | 25 +++- drivers/video/sunxi/sunxi_dw_hdmi.c | 2 + drivers/video/sunxi/sunxi_lcd.c | 9 +- 10 files changed, 172 insertions(+), 14 deletions(-) -- 2.17.1

4 14