September 2020 - U-Boot

[PATCH 1/2] arm: rmobile: Add RZ/G2M SoC
by Biju Das 22 Sep '20

22 Sep '20

Add CPU and PRR IDs for R8A774A1(a.k.a RZ/G2M) SoC. RZ/Gx SoC's are identical to R-Car SoC's apart from some automotive peripherals and they also share the same PRR CPU ID's. For example the RZ/G2M SoC has the same PRR ID 0x52 as R-Car M3W SoC. To differentiate RZ/G SoC's from R-Car SoC's add a member family_type in struct rmobile_cpuinfo and compare the compatible string from device tree for SoC identification of RZ/G SoC. Also sorted the header alphabetically. Signed-off-by: Biju Das <biju.das.jz(a)bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj(a)bp.renesas.com> --- V1-->V2 Add comments in the code for SoC identification logic for RZ/G SoC's --- arch/arm/mach-rmobile/cpu_info.c | 83 +++++++++++++++----- arch/arm/mach-rmobile/include/mach/rmobile.h | 1 + 2 files changed, 65 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index fdbbd72e28..d45a474ba9 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -3,13 +3,23 @@ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> * (C) Copyright 2012 Renesas Solutions Corp. */ -#include <common.h> -#include <cpu_func.h> #include <asm/cache.h> -#include <init.h> #include <asm/io.h> +#include <common.h> +#include <cpu_func.h> +#include <dm/device.h> #include <env.h> +#include <init.h> #include <linux/ctype.h> +#include <linux/libfdt.h> + +enum soc_family_type { + SOC_SHMOBILE = 0, + SOC_RMOBILE, + SOC_RZG2, + SOC_RCAR_GEN2, + SOC_RCAR_GEN3, +}; #ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) @@ -31,6 +41,7 @@ void enable_caches(void) #ifdef CONFIG_DISPLAY_CPUINFO #ifndef CONFIG_RZA1 +DECLARE_GLOBAL_DATA_PTR; static u32 __rmobile_get_cpu_type(void) { return 0x0; @@ -52,36 +63,70 @@ static u32 __rmobile_get_cpu_rev_fraction(void) u32 rmobile_get_cpu_rev_fraction(void) __attribute__((weak, alias("__rmobile_get_cpu_rev_fraction"))); +static const struct udevice_id soc_ids[] = { + { .compatible = "renesas,r8a774a1", .data = SOC_RZG2 }, + { }, +}; + /* CPU infomation table */ static const struct { u16 cpu_type; u8 cpu_name[10]; + enum soc_family_type family_type; } rmobile_cpuinfo[] = { - { RMOBILE_CPU_TYPE_SH73A0, "SH73A0" }, - { RMOBILE_CPU_TYPE_R8A7740, "R8A7740" }, - { RMOBILE_CPU_TYPE_R8A7790, "R8A7790" }, - { RMOBILE_CPU_TYPE_R8A7791, "R8A7791" }, - { RMOBILE_CPU_TYPE_R8A7792, "R8A7792" }, - { RMOBILE_CPU_TYPE_R8A7793, "R8A7793" }, - { RMOBILE_CPU_TYPE_R8A7794, "R8A7794" }, - { RMOBILE_CPU_TYPE_R8A7795, "R8A7795" }, - { RMOBILE_CPU_TYPE_R8A7796, "R8A7796" }, - { RMOBILE_CPU_TYPE_R8A77965, "R8A77965" }, - { RMOBILE_CPU_TYPE_R8A77970, "R8A77970" }, - { RMOBILE_CPU_TYPE_R8A77980, "R8A77980" }, - { RMOBILE_CPU_TYPE_R8A77990, "R8A77990" }, - { RMOBILE_CPU_TYPE_R8A77995, "R8A77995" }, + { RMOBILE_CPU_TYPE_SH73A0, "SH73A0", SOC_SHMOBILE }, + { RMOBILE_CPU_TYPE_R8A7740, "R8A7740", SOC_RMOBILE }, + { RMOBILE_CPU_TYPE_R8A774A1, "R8A774A1", SOC_RZG2 }, + { RMOBILE_CPU_TYPE_R8A7790, "R8A7790", SOC_RCAR_GEN2 }, + { RMOBILE_CPU_TYPE_R8A7791, "R8A7791", SOC_RCAR_GEN2 }, + { RMOBILE_CPU_TYPE_R8A7792, "R8A7792", SOC_RCAR_GEN2 }, + { RMOBILE_CPU_TYPE_R8A7793, "R8A7793", SOC_RCAR_GEN2 }, + { RMOBILE_CPU_TYPE_R8A7794, "R8A7794", SOC_RCAR_GEN2 }, + { RMOBILE_CPU_TYPE_R8A7795, "R8A7795", SOC_RCAR_GEN3 }, + { RMOBILE_CPU_TYPE_R8A7796, "R8A7796", SOC_RCAR_GEN3 }, + { RMOBILE_CPU_TYPE_R8A77965, "R8A77965", SOC_RCAR_GEN3 }, + { RMOBILE_CPU_TYPE_R8A77970, "R8A77970", SOC_RCAR_GEN3 }, + { RMOBILE_CPU_TYPE_R8A77980, "R8A77980", SOC_RCAR_GEN3 }, + { RMOBILE_CPU_TYPE_R8A77990, "R8A77990", SOC_RCAR_GEN3 }, + { RMOBILE_CPU_TYPE_R8A77995, "R8A77995", SOC_RCAR_GEN3 }, { 0x0, "CPU" }, }; +static const struct udevice_id *of_soc_match_compatible(void) +{ + const struct udevice_id *of_match = soc_ids; + int i; + + for (i = 0; i < ARRAY_SIZE(soc_ids); i++) { + if (!fdt_node_check_compatible(gd->fdt_blob, 0, + of_match->compatible)) + return of_match; + of_match++; + } + + return NULL; +} + static int rmobile_cpuinfo_idx(void) { int i = 0; u32 cpu_type = rmobile_get_cpu_type(); + const struct udevice_id *match = of_soc_match_compatible(); + /* + * This loop identifies CPU based on PRR register, it differentiates + * RZ/G SoC's from R-Car SoC's by matching RZ/G SoC compatible string + * from DT against the family_type. + */ for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) - if (rmobile_cpuinfo[i].cpu_type == cpu_type) - break; + if (rmobile_cpuinfo[i].cpu_type == cpu_type) { + if (match && + rmobile_cpuinfo[i].family_type == match->data) + break; + else if (!match && + rmobile_cpuinfo[i].family_type != SOC_RZG2) + break; + } return i; } diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index a50249dc96..8bb64f59dd 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -27,6 +27,7 @@ /* PRR CPU IDs */ #define RMOBILE_CPU_TYPE_SH73A0 0x37 #define RMOBILE_CPU_TYPE_R8A7740 0x40 +#define RMOBILE_CPU_TYPE_R8A774A1 0x52 #define RMOBILE_CPU_TYPE_R8A7790 0x45 #define RMOBILE_CPU_TYPE_R8A7791 0x47 #define RMOBILE_CPU_TYPE_R8A7792 0x4A -- 2.17.1

2 17

[PATCH] arm: rmobile: Use imply for BOARD_EARLY_INIT_F
by Biju Das 22 Sep '20

22 Sep '20

Use "imply" instead of "select" for BOARD_EARLY_INIT_F config option, and then disable it on boards which don't need it. Updated grpeach_defconfig to disable BOARD_EARLY_INIT_F option for RZA1. Signed-off-by: Biju Das <biju.das.jz(a)bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj(a)bp.renesas.com> --- arch/arm/Kconfig | 2 +- configs/grpeach_defconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80702c23d3..f827d7a60e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -940,9 +940,9 @@ config ARCH_QEMU config ARCH_RMOBILE bool "Renesas ARM SoCs" - select BOARD_EARLY_INIT_F if !RZA1 select DM select DM_SERIAL + imply BOARD_EARLY_INIT_F imply CMD_DM imply FAT_WRITE imply SYS_THUMB_BUILD diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index fb5a7b001b..c15168c37b 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="ignore_loglevel" +# BOARD_EARLY_INIT_F is not set # CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set -- 2.17.1

1 1

[PATCH] usb: xhci-rcar: Add support for R8A774A1 SoC
by Lad Prabhakar 22 Sep '20

22 Sep '20

The R8A774A1 is compatible with the generic rcar-gen3-xhci controller. This patch adds the compatibility flag, to support the xHCI controller. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj(a)bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz(a)bp.renesas.com> --- drivers/usb/host/xhci-rcar.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index 8fc51df3d1..5379dba566 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -146,6 +146,7 @@ static int xhci_rcar_ofdata_to_platdata(struct udevice *dev) } static const struct udevice_id xhci_rcar_ids[] = { + { .compatible = "renesas,rcar-gen3-xhci" }, { .compatible = "renesas,xhci-r8a7795" }, { .compatible = "renesas,xhci-r8a7796" }, { .compatible = "renesas,xhci-r8a77965" }, -- 2.17.1

2 1

[PATCH] usb: dwc2: Fix contorl OUT transfer issue
by Chance.Yang 22 Sep '20

22 Sep '20

In buffer DMA mode, gadget should re-configure EP 0 to received SETUP packets when doeptsiz.xfersize is equal to a setup packet size(8 bytes) and EP 0 is in WAIT_FOR_SETUP state. Since EP 0 is not enabled in WAIT_FOR_SETUP state, SETUP packets is NOT received from RxFifo and wriiten to the external memory. Signed-off-by: Chance.Yang <chance.yang(a)vatics.com> --- drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c index 1c0505eb28..9ff9cd5694 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c @@ -421,6 +421,9 @@ static void process_ep_out_intr(struct dwc2_udc *dev) { u32 ep_intr, ep_intr_status; u8 ep_num = 0; + u32 ep_tsr = 0, xfer_size = 0; + u32 epsiz_reg = (u32)&reg->out_endp[ep_num].doeptsiz; + u32 req_size = sizeof(struct usb_ctrlrequest); ep_intr = readl(&reg->daint); debug_cond(DEBUG_OUT_EP != 0, @@ -441,10 +444,17 @@ static void process_ep_out_intr(struct dwc2_udc *dev) if (ep_num == 0) { if (ep_intr_status & TRANSFER_DONE) { - if (dev->ep0state != - WAIT_FOR_OUT_COMPLETE) + ep_tsr = readl(epsiz_reg); + xfer_size = (ep_tsr & + DOEPT_SIZ_XFER_SIZE_MAX_EP0); + + if (xfer_size == req_size && + dev->ep0state == WAIT_FOR_SETUP) { + dwc2_udc_pre_setup(); + } else if (dev->ep0state != + WAIT_FOR_OUT_COMPLETE) { complete_rx(dev, ep_num); - else { + } else { dev->ep0state = WAIT_FOR_SETUP; dwc2_udc_pre_setup(); } -- 2.17.1

2 1

[PATCH] mmc: fsl_esdhc_imx: replace all readl/writel to esdhc_read32/esdhc_write32
by haibo.chen＠nxp.com 22 Sep '20

22 Sep '20

From: Haibo Chen <haibo.chen(a)nxp.com> Currently, readl/writel and esdhc_read32/esdhc_write32 are used. To align the usage, change to only use esdhc_read32/esdhc_write32. Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/fsl_esdhc_imx.c | 64 ++++++++++++++++++------------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 0c866b168f..a0a0903ae4 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -729,7 +729,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) u32 val; if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { - writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl); + esdhc_write32(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl); /* * enable strobe dll ctrl and adjust the delay target @@ -738,10 +738,10 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) val = ESDHC_STROBE_DLL_CTRL_ENABLE | (priv->strobe_dll_delay_target << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); - writel(val, &regs->strobe_dllctrl); + esdhc_write32(val, &regs->strobe_dllctrl); /* wait 1us to make sure strobe dll status register stable */ mdelay(1); - val = readl(&regs->strobe_dllstat); + val = esdhc_read32(&regs->strobe_dllstat); if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK)) pr_warn("HS400 strobe DLL status REF not lock!\n"); if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) @@ -755,18 +755,18 @@ static int esdhc_set_timing(struct mmc *mmc) struct fsl_esdhc *regs = priv->esdhc_regs; u32 mixctrl; - mixctrl = readl(&regs->mixctrl); + mixctrl = esdhc_read32(&regs->mixctrl); mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN); switch (mmc->selected_mode) { case MMC_LEGACY: esdhc_reset_tuning(mmc); - writel(mixctrl, &regs->mixctrl); + esdhc_write32(mixctrl, &regs->mixctrl); break; case MMC_HS_400: case MMC_HS_400_ES: mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN; - writel(mixctrl, &regs->mixctrl); + esdhc_write32(mixctrl, &regs->mixctrl); esdhc_set_strobe_dll(mmc); break; case MMC_HS: @@ -777,12 +777,12 @@ static int esdhc_set_timing(struct mmc *mmc) case UHS_SDR25: case UHS_SDR50: case UHS_SDR104: - writel(mixctrl, &regs->mixctrl); + esdhc_write32(mixctrl, &regs->mixctrl); break; case UHS_DDR50: case MMC_DDR_52: mixctrl |= MIX_CTRL_DDREN; - writel(mixctrl, &regs->mixctrl); + esdhc_write32(mixctrl, &regs->mixctrl); break; default: printf("Not supported %d\n", mmc->selected_mode); @@ -862,8 +862,8 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) struct fsl_esdhc_priv *priv = dev_get_priv(dev); struct fsl_esdhc *regs = priv->esdhc_regs; struct mmc *mmc = &plat->mmc; - u32 irqstaten = readl(&regs->irqstaten); - u32 irqsigen = readl(&regs->irqsigen); + u32 irqstaten = esdhc_read32(&regs->irqstaten); + u32 irqsigen = esdhc_read32(&regs->irqsigen); int i, ret = -ETIMEDOUT; u32 val, mixctrl; @@ -873,25 +873,25 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */ if (priv->flags & ESDHC_FLAG_STD_TUNING) { - val = readl(&regs->autoc12err); - mixctrl = readl(&regs->mixctrl); + val = esdhc_read32(&regs->autoc12err); + mixctrl = esdhc_read32(&regs->mixctrl); val &= ~MIX_CTRL_SMPCLK_SEL; mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN); val |= MIX_CTRL_EXE_TUNE; mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN; - writel(val, &regs->autoc12err); - writel(mixctrl, &regs->mixctrl); + esdhc_write32(val, &regs->autoc12err); + esdhc_write32(mixctrl, &regs->mixctrl); } /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */ - mixctrl = readl(&regs->mixctrl); + mixctrl = esdhc_read32(&regs->mixctrl); mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK); - writel(mixctrl, &regs->mixctrl); + esdhc_write32(mixctrl, &regs->mixctrl); - writel(IRQSTATEN_BRR, &regs->irqstaten); - writel(IRQSTATEN_BRR, &regs->irqsigen); + esdhc_write32(IRQSTATEN_BRR, &regs->irqstaten); + esdhc_write32(IRQSTATEN_BRR, &regs->irqsigen); /* * Issue opcode repeatedly till Execute Tuning is set to 0 or the number @@ -902,22 +902,22 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) { if (mmc->bus_width == 8) - writel(0x7080, &regs->blkattr); + esdhc_write32(0x7080, &regs->blkattr); else if (mmc->bus_width == 4) - writel(0x7040, &regs->blkattr); + esdhc_write32(0x7040, &regs->blkattr); } else { - writel(0x7040, &regs->blkattr); + esdhc_write32(0x7040, &regs->blkattr); } /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */ - val = readl(&regs->mixctrl); + val = esdhc_read32(&regs->mixctrl); val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK); - writel(val, &regs->mixctrl); + esdhc_write32(val, &regs->mixctrl); /* We are using STD tuning, no need to check return value */ mmc_send_tuning(mmc, opcode, NULL); - ctrl = readl(&regs->autoc12err); + ctrl = esdhc_read32(&regs->autoc12err); if ((!(ctrl & MIX_CTRL_EXE_TUNE)) && (ctrl & MIX_CTRL_SMPCLK_SEL)) { ret = 0; @@ -925,8 +925,8 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) } } - writel(irqstaten, &regs->irqstaten); - writel(irqsigen, &regs->irqsigen); + esdhc_write32(irqstaten, &regs->irqstaten); + esdhc_write32(irqsigen, &regs->irqsigen); esdhc_stop_tuning(mmc); @@ -1179,7 +1179,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, if (priv->vs18_enable) esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT); - writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten); + esdhc_write32(SDHCI_IRQ_EN_BITS, &regs->irqstaten); cfg = &plat->cfg; #ifndef CONFIG_DM_MMC memset(cfg, '\0', sizeof(*cfg)); @@ -1260,10 +1260,10 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - writel(0, &regs->dllctrl); + esdhc_write32(0, &regs->dllctrl); if (priv->flags & ESDHC_FLAG_USDHC) { if (priv->flags & ESDHC_FLAG_STD_TUNING) { - u32 val = readl(&regs->tuning_ctrl); + u32 val = esdhc_read32(&regs->tuning_ctrl); val |= ESDHC_STD_TUNING_EN; val &= ~ESDHC_TUNING_START_TAP_MASK; @@ -1282,7 +1282,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, * after the whole tuning procedure always can't get any response. */ val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE; - writel(val, &regs->tuning_ctrl); + esdhc_write32(val, &regs->tuning_ctrl); } } @@ -1648,9 +1648,9 @@ static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev) struct fsl_esdhc *regs = priv->esdhc_regs; u32 m; - m = readl(&regs->mixctrl); + m = esdhc_read32(&regs->mixctrl); m |= MIX_CTRL_HS400_ES; - writel(m, &regs->mixctrl); + esdhc_write32(m, &regs->mixctrl); return 0; } -- 2.17.1

3 2

[PATCH 1/2] mmc: do not send cmd13 if the parameter 'send_status' is 0 for __mmc_switch
by haibo.chen＠nxp.com 22 Sep '20

22 Sep '20

From: Haibo Chen <haibo.chen(a)nxp.com> According to the code logic in __mmc_switch, if the parameter 'send_status' is zero, no need to send cmd13, just wait the stated timeout time, then can return directly. Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> --- drivers/mmc/mmc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index d79cdef62e..6cb2af4232 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -805,8 +805,10 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, * capable of polling by using mmc_wait_dat0, then rely on waiting the * stated timeout to be sufficient. */ - if (ret == -ENOSYS && !send_status) + if (ret == -ENOSYS && !send_status) { mdelay(timeout_ms); + return 0; + } /* Finally wait until the card is ready or indicates a failure * to switch. It doesn't hurt to use CMD13 here even if send_status -- 2.17.1

1 1

[PATCH v1 00/22] Add Intel Diamond Mesa SoC support
by Siew Chin Lim 22 Sep '20

22 Sep '20

This patchset add Intel Diamond Mesa SoC[1] support. Intel Diamond Mesa SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Diamond Mesa are clock manager and DDR subsystem, other IPs have minor changes compared to Agilex. These patchsets have dependency on: Enable ARM Trusted Firmware for U-Boot https://lists.denx.de/pipermail/u-boot/2020-August/423530.html [1]: https://www.intel.com/content/www/us/en/products/programmable/asic/easic-de… Siew Chin Lim (22): arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 arm: socfpga: dm: Add base address for Intel Diamond Mesa arm: socfpga: dm: Add firewall support for Agilex and Diamond Mesa arm: socfpga: Rename Stratix10 and Agilex handoff common macros arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c arm: socfpga: Rearrange sequence of macros in handoff_soc64.h arm: socfpga: Restructure Stratix10 and Agilex handoff code arm: socfpga: Add handoff data support for Diamond Mesa drivers: clk: dm: Add clock driver for Diamond Mesa arm: socfpga: dm: Get clock manager base address for Diamond Mesa drivers: clk: dm: Add memory clock driver for Diamond Mesa arm: socfpga: Move Stratix10 and Agilex clock manager common code arm: socfpga: Changed to store QSPI reference clock in kHz arm: socfpga: dm: Add clock manager for Diamond Mesa ddr: altera: dm: Add SDRAM driver for Diamond Mesa arm: socfpga: Move Stratix10 and Agilex SPL common code arm: socfpga: dm: Add SPL for Diamond Mesa board: intel: dm: Add socdk board support for Diamond Mesa arm: dts: dm: Add base dtsi and devkit dts for Diamond Mesa configs: dm: Add Diamond Mesa CONFIGs arm: socfpga: dm: Enable Intel Diamond Mesa bulid arch/arm/Kconfig | 6 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_dm-u-boot.dtsi | 100 ++ arch/arm/dts/socfpga_dm.dtsi | 640 ++++++++++ arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi | 50 + arch/arm/dts/socfpga_dm_socdk.dts | 144 +++ arch/arm/mach-socfpga/Kconfig | 23 + arch/arm/mach-socfpga/Makefile | 33 +- arch/arm/mach-socfpga/clock_manager.c | 11 + arch/arm/mach-socfpga/clock_manager_agilex.c | 6 - .../{clock_manager_agilex.c => clock_manager_dm.c} | 32 +- arch/arm/mach-socfpga/clock_manager_s10.c | 8 +- arch/arm/mach-socfpga/firewall.c | 10 + arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 3 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 6 + .../mach-socfpga/include/mach/clock_manager_dm.h | 14 + .../mach-socfpga/include/mach/clock_manager_s10.h | 1 - arch/arm/mach-socfpga/include/mach/firewall.h | 7 + arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 - arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 81 ++ arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +- .../arm/mach-socfpga/include/mach/system_manager.h | 3 +- .../include/mach/system_manager_soc64.h | 20 +- arch/arm/mach-socfpga/mailbox_s10.c | 28 +- arch/arm/mach-socfpga/misc.c | 3 + arch/arm/mach-socfpga/spl_agilex.c | 16 - arch/arm/mach-socfpga/{spl_agilex.c => spl_dm.c} | 37 +- arch/arm/mach-socfpga/spl_s10.c | 17 - arch/arm/mach-socfpga/spl_soc64.c | 26 + ...system_manager_s10.c => system_manager_soc64.c} | 53 +- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 113 ++ arch/arm/mach-socfpga/wrap_pinmux_config_s10.c | 56 - ...ap_pll_config_s10.c => wrap_pll_config_soc64.c} | 18 +- board/intel/dm-socdk/MAINTAINERS | 7 + board/intel/dm-socdk/Makefile | 7 + board/intel/dm-socdk/socfpga.c | 7 + configs/socfpga_dm_atf_defconfig | 75 ++ configs/socfpga_dm_defconfig | 69 ++ drivers/clk/altera/Makefile | 3 +- drivers/clk/altera/clk-dm.c | 504 ++++++++ drivers/clk/altera/clk-dm.h | 213 ++++ drivers/clk/altera/clk-mem-dm.c | 135 ++ drivers/clk/altera/clk-mem-dm.h | 80 ++ drivers/ddr/altera/Kconfig | 6 +- drivers/ddr/altera/Makefile | 1 + drivers/ddr/altera/sdram_dm.c | 1294 ++++++++++++++++++++ drivers/ddr/altera/sdram_soc64.c | 6 + drivers/fpga/Kconfig | 2 +- drivers/sysreset/Kconfig | 2 +- include/configs/socfpga_dm_socdk.h | 46 + include/configs/socfpga_soc64_common.h | 4 +- include/dt-bindings/clock/dm-clock.h | 71 ++ 52 files changed, 3898 insertions(+), 242 deletions(-) create mode 100644 arch/arm/dts/socfpga_dm-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_dm.dtsi create mode 100644 arch/arm/dts/socfpga_dm_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_dm_socdk.dts copy arch/arm/mach-socfpga/{clock_manager_agilex.c => clock_manager_dm.c} (59%) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_dm.h delete mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_soc64.h copy arch/arm/mach-socfpga/{spl_agilex.c => spl_dm.c} (77%) create mode 100644 arch/arm/mach-socfpga/spl_soc64.c rename arch/arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c} (55%) create mode 100644 arch/arm/mach-socfpga/wrap_handoff_soc64.c delete mode 100644 arch/arm/mach-socfpga/wrap_pinmux_config_s10.c rename arch/arm/mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} (71%) create mode 100644 board/intel/dm-socdk/MAINTAINERS create mode 100644 board/intel/dm-socdk/Makefile create mode 100644 board/intel/dm-socdk/socfpga.c create mode 100644 configs/socfpga_dm_atf_defconfig create mode 100644 configs/socfpga_dm_defconfig create mode 100644 drivers/clk/altera/clk-dm.c create mode 100644 drivers/clk/altera/clk-dm.h create mode 100644 drivers/clk/altera/clk-mem-dm.c create mode 100644 drivers/clk/altera/clk-mem-dm.h create mode 100644 drivers/ddr/altera/sdram_dm.c create mode 100644 include/configs/socfpga_dm_socdk.h create mode 100644 include/dt-bindings/clock/dm-clock.h -- 2.13.0

1 22

[PATCHv6 00/18] powerpc: convert p1010, p1020 and p2020 RDB boards to DM_ETH
by Zhiqiang Hou 22 Sep '20

22 Sep '20

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> This patchset is to convert P1010, P1020 and P2020 RDB boards to DM_ETH. V5: Merged the following thread: https://patchwork.ozlabs.org/project/uboot/list/?series=174343&archive=both… Hou Zhiqiang (16): net: fsl_mdio: Change to use virtual address net: fsl_mdio: Correct the MII management register block address net: tsec: convert to use DM_MDIO when DM_ETH enabled net: tsec: Add fixed-link PHY support net: tsec: Add the compatible string "gianfar" support powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r() configs: p1_p2_rdb: Add the default address of vsc7385 firmware dts: powerpc: p1020rdb: Add eTSEC DT nodes powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled configs: P1020RDB: Enable DM_ETH config dts: powerpc: p1010rdb: Add eTSEC DT nodes powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH configs: P1010RDB: Enable DM_ETH config dts: powerpc: p2020rdb: Add eTSEC DT nodes configs: P2020RDB: Enable DM_ETH config Vladimir Oltean (2): phy: make phy_connect_fixed work with a null mdio bus configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN arch/powerpc/cpu/mpc8xxx/cpu.c | 2 + arch/powerpc/dts/p1010rdb-pa.dts | 1 + arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 + arch/powerpc/dts/p1010rdb.dtsi | 50 +++++++++++++++ arch/powerpc/dts/p1010si-post.dtsi | 25 ++++++++ arch/powerpc/dts/p1020-post.dtsi | 20 +++++- arch/powerpc/dts/p1020rdb-pc.dts | 1 + arch/powerpc/dts/p1020rdb-pc.dtsi | 55 ++++++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 1 + arch/powerpc/dts/p1020rdb-pd.dts | 45 ++++++++++++++ arch/powerpc/dts/p2020-post.dtsi | 8 ++- arch/powerpc/dts/p2020rdb-pc.dts | 1 + arch/powerpc/dts/p2020rdb-pc.dtsi | 50 +++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 + arch/powerpc/dts/pq3-etsec1-0.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec1-1.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec1-2.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec1-3.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec2-0.dtsi | 35 +++++++++++ arch/powerpc/dts/pq3-etsec2-1.dtsi | 35 +++++++++++ arch/powerpc/dts/pq3-etsec2-2.dtsi | 35 +++++++++++ arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++++ arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++++ arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++++ board/freescale/p1010rdb/p1010rdb.c | 2 + board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 37 ++++++----- configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PA_NAND_defconfig | 2 + configs/P1010RDB-PA_NOR_defconfig | 2 + configs/P1010RDB-PA_SDCARD_defconfig | 2 + configs/P1010RDB-PA_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_NAND_defconfig | 2 + configs/P1010RDB-PB_NOR_defconfig | 2 + configs/P1010RDB-PB_SDCARD_defconfig | 2 + configs/P1010RDB-PB_SPIFLASH_defconfig | 2 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P1020RDB-PC_36BIT_defconfig | 3 + configs/P1020RDB-PC_NAND_defconfig | 3 + configs/P1020RDB-PC_SDCARD_defconfig | 3 + configs/P1020RDB-PC_SPIFLASH_defconfig | 3 + configs/P1020RDB-PC_defconfig | 3 + configs/P1020RDB-PD_NAND_defconfig | 3 + configs/P1020RDB-PD_SDCARD_defconfig | 3 + configs/P1020RDB-PD_SPIFLASH_defconfig | 3 + configs/P1020RDB-PD_defconfig | 3 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P2020RDB-PC_36BIT_defconfig | 3 + configs/P2020RDB-PC_NAND_defconfig | 3 + configs/P2020RDB-PC_SDCARD_defconfig | 3 + configs/P2020RDB-PC_SPIFLASH_defconfig | 3 + configs/P2020RDB-PC_defconfig | 3 + configs/ls1021atsn_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +- drivers/net/fsl_mdio.c | 28 +++++++-- drivers/net/phy/phy.c | 4 +- drivers/net/tsec.c | 62 ++++++++----------- include/configs/p1_p2_rdb_pc.h | 2 + include/fsl_mdio.h | 4 ++ include/tsec.h | 4 ++ 78 files changed, 707 insertions(+), 65 deletions(-) create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi -- 2.17.1

1 18

[PATCHv5 00/18] powerpc: convert p1010, p1020 and p2020 RDB boards to DM_ETH
by Zhiqiang Hou 22 Sep '20

22 Sep '20

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> This patchset is to convert P1010, P1020 and P2020 RDB boards to DM_ETH. V5: Merged the following thread: https://patchwork.ozlabs.org/project/uboot/list/?series=174343&archive=both… Hou Zhiqiang (16): net: fsl_mdio: Change to use virtual address net: fsl_mdio: Correct the MII management register block address net: tsec: convert to use DM_MDIO when DM_ETH enabled net: tsec: Add fixed-link PHY support net: tsec: Add the compatible string "gianfar" support powerpc: mpc8xxx: Don't compile cpu_eth_init() when DM_ETH enabled fsl: p1_p2_rdb: Move vsc7835 firmware uploading to board_early_init_r() configs: p1_p2_rdb: Add the default address of vsc7385 firmware dts: powerpc: p1020rdb: Add eTSEC DT nodes powerpc: p1_p2_rdb: Don't compile board_eth_init() when DM_ETH enabled configs: P1020RDB: Enable DM_ETH config dts: powerpc: p1010rdb: Add eTSEC DT nodes powerpc: p1010rdb: Compile legacy ethernet init function when no DM_ETH configs: P1010RDB: Enable DM_ETH config dts: powerpc: p2020rdb: Add eTSEC DT nodes configs: P2020RDB: Enable DM_ETH config Vladimir Oltean (2): phy: make phy_connect_fixed work with a null mdio bus configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN arch/powerpc/cpu/mpc8xxx/cpu.c | 2 + arch/powerpc/dts/p1010rdb-pa.dts | 1 + arch/powerpc/dts/p1010rdb-pa_36b.dts | 1 + arch/powerpc/dts/p1010rdb.dtsi | 50 +++++++++++++++ arch/powerpc/dts/p1010si-post.dtsi | 25 ++++++++ arch/powerpc/dts/p1020-post.dtsi | 20 +++++- arch/powerpc/dts/p1020rdb-pc.dts | 1 + arch/powerpc/dts/p1020rdb-pc.dtsi | 55 ++++++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 1 + arch/powerpc/dts/p1020rdb-pd.dts | 45 ++++++++++++++ arch/powerpc/dts/p2020-post.dtsi | 8 ++- arch/powerpc/dts/p2020rdb-pc.dts | 1 + arch/powerpc/dts/p2020rdb-pc.dtsi | 50 +++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 + arch/powerpc/dts/pq3-etsec1-0.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec1-1.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec1-2.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec1-3.dtsi | 28 +++++++++ arch/powerpc/dts/pq3-etsec2-0.dtsi | 35 +++++++++++ arch/powerpc/dts/pq3-etsec2-1.dtsi | 35 +++++++++++ arch/powerpc/dts/pq3-etsec2-2.dtsi | 35 +++++++++++ arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi | 16 +++++ arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi | 16 +++++ arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi | 16 +++++ board/freescale/p1010rdb/p1010rdb.c | 2 + board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 37 ++++++----- configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PA_NAND_defconfig | 2 + configs/P1010RDB-PA_NOR_defconfig | 2 + configs/P1010RDB-PA_SDCARD_defconfig | 2 + configs/P1010RDB-PA_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 + configs/P1010RDB-PB_NAND_defconfig | 2 + configs/P1010RDB-PB_NOR_defconfig | 2 + configs/P1010RDB-PB_SDCARD_defconfig | 2 + configs/P1010RDB-PB_SPIFLASH_defconfig | 2 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P1020RDB-PC_36BIT_defconfig | 3 + configs/P1020RDB-PC_NAND_defconfig | 3 + configs/P1020RDB-PC_SDCARD_defconfig | 3 + configs/P1020RDB-PC_SPIFLASH_defconfig | 3 + configs/P1020RDB-PC_defconfig | 3 + configs/P1020RDB-PD_NAND_defconfig | 3 + configs/P1020RDB-PD_SDCARD_defconfig | 3 + configs/P1020RDB-PD_SPIFLASH_defconfig | 3 + configs/P1020RDB-PD_defconfig | 3 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 + configs/P2020RDB-PC_36BIT_defconfig | 3 + configs/P2020RDB-PC_NAND_defconfig | 3 + configs/P2020RDB-PC_SDCARD_defconfig | 3 + configs/P2020RDB-PC_SPIFLASH_defconfig | 3 + configs/P2020RDB-PC_defconfig | 3 + configs/ls1021atsn_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_nor_defconfig | 1 + configs/ls1021atwr_nor_lpuart_defconfig | 1 + configs/ls1021atwr_qspi_defconfig | 1 + ...s1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +- drivers/net/fsl_mdio.c | 28 +++++++-- drivers/net/phy/phy.c | 4 +- drivers/net/tsec.c | 62 ++++++++----------- include/configs/p1_p2_rdb_pc.h | 2 + include/fsl_mdio.h | 4 ++ include/tsec.h | 4 ++ 78 files changed, 707 insertions(+), 65 deletions(-) create mode 100644 arch/powerpc/dts/p1020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/p2020rdb-pc.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec1-3.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-2.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi create mode 100644 arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi -- 2.25.1

3 20

[PATCH 0/5] x86: Updates to some commands
by Simon Glass 22 Sep '20

22 Sep '20

This series adds a few more features to some x86-specific commands. Simon Glass (5): x86: hob: Add way to show a single hob entry x86: hob: Try to show a name instead of a GUID x86: Allow showing details about a HOB entry x86: Add support for more than 8 MTRRs x86: video: Show information about each video device arch/x86/cpu/mtrr.c | 12 ++-- arch/x86/include/asm/fsp/fsp_hob.h | 25 ++++++++ arch/x86/include/asm/mtrr.h | 15 ++++- cmd/bdinfo.c | 26 +++++++- cmd/x86/hob.c | 100 +++++++++++++++++++++++++++-- cmd/x86/mtrr.c | 9 +-- 6 files changed, 167 insertions(+), 20 deletions(-) -- 2.28.0.681.g6f77f65b4e-goog

2 10