May 2020 - U-Boot

[PATCH 00/13] imx: tmu support and scu thermal update
by Peng Fan 11 May '20

11 May '20

This patchset is to support TMU in i.MX8M family, including i.MX8QM SCU thermal update. Peng Fan (8): thermal: Add thermal driver for i.MX8M thermal: imx_tmu: Add support for thermal sensor on iMX8MM thermal: imx_tmu: support TMU arch level initialization thermal: imx_tmu: Fix for temperature out of range thermal: imx_tmu: Check the TEMP range for iMX8MM thermal: imx_tmu: support i.MX8MP imx: regs: add more fuse bank structure imx: cpu: support tmu Ye Li (5): thermal: imx_scu_thermal: Update driver for i.MX8QM thermal sensor imx8mm: Load fuse for TMU TCALIV and TASR imx: i.MX8MN: Enable loading TASR and TCALIV from fuse imx: load calibration parameters from fuse for i.MX8MP imx8mp: Set default SNSR25C for TMU probe1 arch/arm/include/asm/arch-imx8m/imx-regs.h | 41 ++- arch/arm/mach-imx/cpu.c | 4 +- arch/arm/mach-imx/imx8m/soc.c | 75 ++++- drivers/thermal/Kconfig | 9 + drivers/thermal/Makefile | 1 + drivers/thermal/imx_scu_thermal.c | 8 + drivers/thermal/imx_tmu.c | 467 +++++++++++++++++++++++++++++ 7 files changed, 595 insertions(+), 10 deletions(-) create mode 100644 drivers/thermal/imx_tmu.c -- 2.16.4

3 33

[PATCH V2 1/6] dt-bindings: imx_rsrc: add SC_R_NONE
by Peng Fan 11 May '20

11 May '20

Add SC_R_NONE entry Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- V2: New For other patches in patchset, only patch 6 is changed. include/dt-bindings/soc/imx_rsrc.h | 1 + 1 file changed, 1 insertions(+) diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h index 4870eb985b..9200cd3f20 100644 --- a/include/dt-bindings/soc/imx_rsrc.h +++ b/include/dt-bindings/soc/imx_rsrc.h @@ -553,5 +553,6 @@ #define SC_R_VPU_ENC_1 539 #define SC_R_VPU 540 #define SC_R_LAST 541 +#define SC_R_NONE 0xFFF0 #endif /* DT_BINDINGS_RSCRC_IMX_H */ -- 2.16.4

2 11

[PATCH 00/10] imx: imx8qm/qxp update
by Peng Fan 11 May '20

11 May '20

This patchset is various update for i.MX8 from NXP downstream Support reserve ddr memory for M4 Add get board serial power down resources when SPL jump to u-boot recover SPL data check m4 partition boot Fix get_effective_memsize select boot device dynamically Peng Fan (8): imx: imx8qm/qxp: reserving DDR memory for M4 imx: imx8qm/qxp: add get_board_serial imx: imx8qm/imx8qxp: Power down the resources before SPL jump to u-boot imx: imx8qm/qxp: Recover SPL data section for partition reboot imx: imx8qm/qxp: check whether m4 partition booted imx: imx8qm: update fdt_file according to m4 state imx: imx8qxp: update fdt_file according to m4 state imx8: cpu: check resource owned after sid fail Ye Li (2): imx: imx8qm/qxp: Fix issue in get_effective_memsize imx8: Select boot device dynamically arch/arm/cpu/armv8/Kconfig | 6 ++ arch/arm/cpu/armv8/Makefile | 4 ++ arch/arm/cpu/armv8/spl_data.c | 29 +++++++++ arch/arm/cpu/armv8/u-boot-spl.lds | 8 +++ arch/arm/include/asm/arch-imx8/sys_proto.h | 2 + arch/arm/mach-imx/imx8/Kconfig | 10 +++ arch/arm/mach-imx/imx8/cpu.c | 85 ++++++++++++++++++++++++- arch/arm/mach-imx/imx8/fdt.c | 18 ++++-- board/freescale/imx8qm_mek/imx8qm_mek.c | 13 ++++ board/freescale/imx8qm_mek/spl.c | 6 ++ board/freescale/imx8qxp_mek/imx8qxp_mek.c | 13 ++++ board/freescale/imx8qxp_mek/spl.c | 6 ++ drivers/power/domain/imx8-power-domain-legacy.c | 35 ++++++++++ include/configs/imx8qm_mek.h | 2 +- include/configs/imx8qxp_mek.h | 2 +- include/spl.h | 1 + 16 files changed, 231 insertions(+), 9 deletions(-) create mode 100644 arch/arm/cpu/armv8/spl_data.c -- 2.16.4

2 20

[PATCH] pinctrl: nxp: scu: Check the pad partition before set pinmux
by Peng Fan 11 May '20

11 May '20

From: Ye Li <ye.li(a)nxp.com> If a pad is not owned by current partition we should not set its pinmux. Signed-off-by: Ye Li <ye.li(a)nxp.com> Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- drivers/pinctrl/nxp/pinctrl-scu.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/nxp/pinctrl-scu.c b/drivers/pinctrl/nxp/pinctrl-scu.c index aa11075e0a..c032be782a 100644 --- a/drivers/pinctrl/nxp/pinctrl-scu.c +++ b/drivers/pinctrl/nxp/pinctrl-scu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018-2019 NXP */ #include <common.h> @@ -29,6 +29,11 @@ static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info *info, u32 pad, * to handle that in scfw, so config it in pad conf func */ + if (!sc_rm_is_pad_owned(-1, pad)) { + debug("Pad[%u] is not owned by curr partition\n", pad); + return -EPERM; + } + val |= PADRING_IFMUX_EN_MASK; val |= PADRING_GP_EN_MASK; val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK; @@ -57,7 +62,7 @@ int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, u32 *pin_data, config_val = pin_data[j++]; ret = imx_pinconf_scu_set(info, pin_id, mux, config_val); - if (ret) + if (ret && ret != -EPERM) printf("Set pin %d, mux %d, val %d, error\n", pin_id, mux, config_val); } -- 2.16.4

2 1

[PATCH 1/2] misc: fuse: Update imx8 fuse driver for 8QM
by Peng Fan 11 May '20

11 May '20

From: Ye Li <ye.li(a)nxp.com> Add the second ECC fuse area for 8QM which is different with 8QXP Signed-off-by: Ye Li <ye.li(a)nxp.com> Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- drivers/misc/imx8/fuse.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c index 1309215d4d..4d7f2f524d 100644 --- a/drivers/misc/imx8/fuse.c +++ b/drivers/misc/imx8/fuse.c @@ -15,8 +15,13 @@ DECLARE_GLOBAL_DATA_PTR; #define FSL_ECC_WORD_START_1 0x10 #define FSL_ECC_WORD_END_1 0x10F +#ifdef CONFIG_IMX8QM +#define FSL_ECC_WORD_START_2 0x1A0 +#define FSL_ECC_WORD_END_2 0x1FF +#elif defined(CONFIG_IMX8QXP) #define FSL_ECC_WORD_START_2 0x220 #define FSL_ECC_WORD_END_2 0x31F +#endif #define FSL_QXP_FUSE_GAP_START 0x110 #define FSL_QXP_FUSE_GAP_END 0x21F -- 2.16.4

2 3

[PATCH V2 resend 0/4] support i.MX module fuse
by Peng Fan 11 May '20

11 May '20

To i.MX chips, for one kind of SoC, it may have different fuse configuration to control whether the module is usable in the chip. To make sure one software could run this kind of SoC, we add fuse check. The patchset is a resend of patchset which was sent near one year ago: https://patchwork.ozlabs.org/project/uboot/patch/20190801090117.24692-1-pen… I dropped the R-b/A-b tags since long time. Peng Fan (4): imx: add module fuse support i2c: mxc: add fuse check usb: mx6: add fuse check net: fec: add fuse check arch/arm/include/asm/mach-imx/module_fuse.h | 127 +++++++++++ arch/arm/include/asm/mach-imx/sys_proto.h | 1 + arch/arm/mach-imx/Kconfig | 7 + arch/arm/mach-imx/mx6/Makefile | 1 + arch/arm/mach-imx/mx6/module_fuse.c | 322 ++++++++++++++++++++++++++++ drivers/i2c/mxc_i2c.c | 17 ++ drivers/net/fec_mxc.c | 14 ++ drivers/usb/host/ehci-mx6.c | 16 ++ 8 files changed, 505 insertions(+) create mode 100644 arch/arm/include/asm/mach-imx/module_fuse.h create mode 100644 arch/arm/mach-imx/mx6/module_fuse.c -- 2.16.4

3 10

[PATCH] mtd: nand: raw: mxs_nand changes for nandbcb
by Peng Fan 11 May '20

11 May '20

From: Han Xu <han.xu(a)nxp.com> Add more BCH setting mode and remove the unnecessary platform constrain Signed-off-by: Han Xu <han.xu(a)nxp.com> Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- drivers/mtd/nand/raw/mxs_nand.c | 43 ++++++++++++++++++++++++++++++++++++++--- include/mxs_nand.h | 3 ++- 2 files changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index c3191feca8..e3516cd141 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -710,7 +710,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand, d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; - if ((is_mx7() || is_imx8m()) && nand_info->en_randomizer) { + if (nand_info->en_randomizer) { d->cmd.pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE | GPMI_ECCCTRL_RANDOMIZER_TYPE2; d->cmd.pio_words[3] |= (page % 256) << 16; @@ -867,7 +867,7 @@ static int mxs_nand_ecc_write_page(struct mtd_info *mtd, d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf; d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf; - if ((is_mx7() || is_imx8m()) && nand_info->en_randomizer) { + if (nand_info->en_randomizer) { d->cmd.pio_words[2] |= GPMI_ECCCTRL_RANDOMIZER_ENABLE | GPMI_ECCCTRL_RANDOMIZER_TYPE2; /* @@ -1489,7 +1489,7 @@ void mxs_nand_get_layout(struct mtd_info *mtd, struct mxs_nand_layout *l) /* * Set BCH to specific layout used by ROM bootloader to read FCB. */ -void mxs_nand_mode_fcb(struct mtd_info *mtd) +void mxs_nand_mode_fcb_62bit(struct mtd_info *mtd) { u32 tmp; struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; @@ -1522,6 +1522,43 @@ void mxs_nand_mode_fcb(struct mtd_info *mtd) writel(tmp, &bch_regs->hw_bch_flash0layout1); } +/* + * Set BCH to specific layout used by ROM bootloader to read FCB. + */ +void mxs_nand_mode_fcb_40bit(struct mtd_info *mtd) +{ + u32 tmp; + struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE; + struct nand_chip *nand = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); + + /* no randomizer in this setting*/ + nand_info->en_randomizer = 0; + + mtd->writesize = 1024; + mtd->oobsize = 1576 - 1024; + + /* 8 ecc_chunks_*/ + tmp = 7 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET; + /* 32 bytes for metadata */ + tmp |= 32 << BCH_FLASHLAYOUT0_META_SIZE_OFFSET; + /* using ECC40 level to be performed */ + tmp |= 0x14 << BCH_FLASHLAYOUT0_ECC0_OFFSET; + /* 0x20 * 4 bytes of the data0 block */ + tmp |= 0x20 << BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET; + tmp |= 0 << BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET; + writel(tmp, &bch_regs->hw_bch_flash0layout0); + + /* 1024 for data + 552 for OOB */ + tmp = 1576 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET; + /* using ECC40 level to be performed */ + tmp |= 0x14 << BCH_FLASHLAYOUT1_ECCN_OFFSET; + /* 0x20 * 4 bytes of the data0 block */ + tmp |= 0x20 << BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET; + tmp |= 0 << BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET; + writel(tmp, &bch_regs->hw_bch_flash0layout1); +} + /* * Restore BCH to normal settings. */ diff --git a/include/mxs_nand.h b/include/mxs_nand.h index 21d68a909d..c0cefaca90 100644 --- a/include/mxs_nand.h +++ b/include/mxs_nand.h @@ -95,7 +95,8 @@ int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info); int mxs_nand_init_spl(struct nand_chip *nand); int mxs_nand_setup_ecc(struct mtd_info *mtd); -void mxs_nand_mode_fcb(struct mtd_info *mtd); +void mxs_nand_mode_fcb_62bit(struct mtd_info *mtd); +void mxs_nand_mode_fcb_40bit(struct mtd_info *mtd); void mxs_nand_mode_normal(struct mtd_info *mtd); u32 mxs_nand_mark_byte_offset(struct mtd_info *mtd); u32 mxs_nand_mark_bit_offset(struct mtd_info *mtd); -- 2.16.4

2 1

[PATCH] imx8mq_phanbell: Run SPL with caches enabled
by Fabio Estevam 11 May '20

11 May '20

It is safe to run SPL with caches enabled on i.MX8M, so remove such restriction. Signed-off-by: Fabio Estevam <festevam(a)gmail.com> --- configs/imx8mq_phanbell_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 5be02a3382..d6a4414ad6 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -1,6 +1,4 @@ CONFIG_ARM=y -CONFIG_SPL_SYS_ICACHE_OFF=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_ENV_SIZE=0x1000 -- 2.17.1

2 1

[PATCH 0/6] imx: clean up sip file
by Peng Fan 11 May '20

11 May '20

No need keep imx sip code, since we could use arm_smccc_smc Peng Fan (6): imx8: misc: use arm_smccc_smc imx8m: soc: use arm_smccc_smc imx: bootaux: use arm_smccc_smc imx8: fuse: use arm_smccc_smc imx: power-domain: use arm_smccc_smc imx: remove imx sip file arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/imx8/misc.c | 7 +++-- arch/arm/mach-imx/imx8m/soc.c | 7 +++-- arch/arm/mach-imx/imx_bootaux.c | 11 ++++++-- arch/arm/mach-imx/sip.c | 46 ------------------------------- drivers/misc/imx8/fuse.c | 19 ++++++++----- drivers/power/domain/imx8m-power-domain.c | 10 ++++--- 7 files changed, 38 insertions(+), 64 deletions(-) delete mode 100644 arch/arm/mach-imx/sip.c -- 2.16.4

1 6

[PATCH v8 00/21] RISC-V SiFive FU540 support SPL
by Pragnesh Patel 11 May '20

11 May '20

This series add support for SPL to FU540. U-Boot SPL can boot from L2 LIM (0x0800_0000) and jump to OpenSBI(FW_DYNAMIC firmware) and U-Boot proper from MMC devices. This series depends on: [1] https://patchwork.ozlabs.org/patch/1281853 [2] https://patchwork.ozlabs.org/patch/1281852 All these together is available for testing here [3] [3] https://github.com/pragnesh26992/u-boot/tree/spl How to test this patch: 1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y 2) export OPENSBI=<path/to/opensbi/build/platform/generic/firmware/fw_dynamic.bin> 3) Change to u-boot-dir 4) make sifive_fu540_defconfig 5) make all 6) Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch) # sudo sgdisk --clear \ > --set-alignment=2 \ > --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \ > --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \ > --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \ > /dev/sda 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082 Changes in v8: - Remove SPL_CRC7_SUPPORT Kconfig option and compile crc7.o when CONFIG_MMC_SPI selected - Add "TODO" in drivers/ram/sifive/sdram_fu540.c - Remove unnecessary TODO from drivers/clk/sifive/fu540-prci.c - Make fu540-hifive-unleashed-a00-sdram-ddr4.dtsi file dual-licensed - Add 2 new patches sifive: fu540: Add sample SD gpt partition layout (https://patchwork.ozlabs.org/patch/1092) sifive: fu540: Add U-Boot proper sector start (https://patchwork.ozlabs.org/patch/1093) - Remove patch riscv: Enable cpu clock if it is present (https://patchwork.ozlabs.org/patch/1281573) - Update doc/board/sifive/fu540.rst for PLATFORM=generic Changes in v7: - Standardize SD gpt partition layout - Add delay for SiFive OTP driver - Use DM way for corepll and ddrpll - Add new cpu fu540 (arch/riscv/cpu/fu540) - Update document for FU540 (doc/board/sifive/fu540.rst) Changes in v6: - Typo Correction - Make fu540-c000-u-boot.dtsi and hifive-unleashed-a00-u-boot.dtsi Dual Licensed - Sync Hifive unleashed dts from Linux - Add arch/riscv/fu540 for FU540 specific code Changes in v5: - Return read/write bytes for sifive_otp_read and sifive_otp_write - Correct Palmer's email address Changes in v4: - Split misc DM driver patch into multiple patches - Added new SPL_CRC7_SUPPORT Kconfig option - Added DM driver for DDR - Added clk_enable and clk_disable ops in SiFive PRCI driver - Added early clock initialization for SPL in SiFive PRCI driver - Added SPL config options in sifive_fu540_defconfig instead of creatiing a new config file for SPL - Update fu540.rst on how to build and flash U-boot SPL Changes in v3: - Remove arch-fu540 and arch-sifive from arch/riscv/include/asm/ - Split SPL patches into DDR and SPL and spl defconfig - Update fu540/MAINTAINERS file - Update fu540.rst on how to build and flash U-boot SPL Changes in v2: - Add DM driver Sifive OTP - Split SPL patches into multiple patches - Add a seprate patch for _image_binary_end and crc7.c - Add a seprate patch to add board -u-boot.dtsi files - Update FU540 RISC-V documentation Jagan Teki (2): sifive: fu540: Add sample SD gpt partition layout sifive: fu540: Add U-Boot proper sector start Pragnesh Patel (19): misc: add driver for the SiFive otp controller riscv: sifive: fu540: Use OTP DM driver for serial environment variable riscv: Add _image_binary_end for SPL lib: Makefile: build crc7.c when CONFIG_MMC_SPI riscv: sifive: dts: fu540: Add board -u-boot.dtsi files sifive: fu540: add ddr driver sifive: dts: fu540: Add DDR controller and phy register settings riscv: sifive: dts: fu540: add U-Boot dmc node clk: sifive: fu540-prci: Add clock enable and disable ops clk: sifive: fu540-prci: Add ddr clock initialization in SPL clk: sifive: fu540-prci: Add ehternet clock initialization in SPL riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux riscv: cpu: fu540: Add support for cpu fu540 riscv: Add place-holder for driver compilation riscv: sifive: fu540: add SPL configuration configs: fu540: Add config options for U-Boot SPL sifive: dts: fu540: Enable L2 Cache in U-Boot riscv: sifive: fu540: enable all cache ways from U-Boot proper doc: sifive: fu540: Add description for OpenSBI generic platform arch/riscv/Kconfig | 1 + arch/riscv/cpu/fu540/Kconfig | 15 + arch/riscv/cpu/fu540/Makefile | 12 + arch/riscv/cpu/fu540/cache.c | 53 + arch/riscv/cpu/fu540/cpu.c | 22 + arch/riscv/cpu/fu540/dram.c | 38 + arch/riscv/cpu/fu540/spl.c | 23 + arch/riscv/cpu/u-boot-spl.lds | 1 + arch/riscv/dts/fu540-c000-u-boot.dtsi | 88 + arch/riscv/dts/fu540-c000.dtsi | 37 +- ...fu540-hifive-unleashed-a00-sdram-ddr4.dtsi | 1489 +++++++++++++++++ .../dts/hifive-unleashed-a00-u-boot.dtsi | 22 + arch/riscv/dts/hifive-unleashed-a00.dts | 9 + arch/riscv/include/asm/arch-fu540/cache.h | 14 + arch/riscv/include/asm/arch-fu540/clk.h | 14 + arch/riscv/include/asm/arch-fu540/gpio.h | 38 + arch/riscv/include/asm/arch-fu540/spl.h | 14 + board/sifive/fu540/Kconfig | 18 +- board/sifive/fu540/Makefile | 4 + board/sifive/fu540/fu540.c | 145 +- board/sifive/fu540/spl.c | 72 + common/spl/Kconfig | 3 +- configs/sifive_fu540_defconfig | 8 + doc/board/sifive/fu540.rst | 145 +- drivers/clk/sifive/fu540-prci.c | 196 ++- drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/sifive-otp.c | 273 +++ drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 2 + drivers/ram/sifive/Kconfig | 13 + drivers/ram/sifive/Makefile | 6 + drivers/ram/sifive/sdram_fu540.c | 416 +++++ include/configs/sifive-fu540.h | 31 + lib/Makefile | 2 +- 35 files changed, 3127 insertions(+), 106 deletions(-) create mode 100644 arch/riscv/cpu/fu540/Kconfig create mode 100644 arch/riscv/cpu/fu540/Makefile create mode 100644 arch/riscv/cpu/fu540/cache.c create mode 100644 arch/riscv/cpu/fu540/cpu.c create mode 100644 arch/riscv/cpu/fu540/dram.c create mode 100644 arch/riscv/cpu/fu540/spl.c create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi create mode 100644 arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h create mode 100644 board/sifive/fu540/spl.c create mode 100644 drivers/misc/sifive-otp.c create mode 100644 drivers/ram/sifive/Kconfig create mode 100644 drivers/ram/sifive/Makefile create mode 100644 drivers/ram/sifive/sdram_fu540.c -- 2.17.1

3 30