May 2020 - U-Boot

[v4] dm: ppc: MPC8548CDS: add i2c DM support
by Biwen Li 01 May '20

01 May '20

From: Biwen Li <biwen.li(a)nxp.com> This supports i2c DM for board MPC8548CDS Signed-off-by: Biwen Li <biwen.li(a)nxp.com> --- Change in v4: - fix build error Change in v3: - none Change in v2: - none board/freescale/common/sys_eeprom.c | 3 ++- include/configs/MPC8548CDS.h | 9 ++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 6f151b0f71..c487e3a515 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -595,6 +595,7 @@ unsigned int get_cpu_board_revision(void) (void *)&be, sizeof(be)); #else struct udevice *dev; + int ret; #ifdef CONFIG_SYS_EEPROM_BUS_NUM ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM, CONFIG_SYS_I2C_EEPROM_ADDR, @@ -603,7 +604,7 @@ unsigned int get_cpu_board_revision(void) #else ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, - &dev) + &dev); #endif if (!ret) dm_i2c_read(dev, 0, (void *)&be, sizeof(be)); diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a68d190f6a..b7796236fd 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. + * Copyright 2020 NXP */ /* @@ -304,12 +305,18 @@ extern unsigned long get_clock_freq(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL #define CONFIG_SYS_FSL_I2C_SPEED 400000 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } +#else +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif +#define CONFIG_SYS_I2C_FSL /* EEPROM */ #define CONFIG_ID_EEPROM -- 2.17.1

1 0

[PATCH v3 0/7] x86: efi: Add a 64-bit coreboot payload
by Simon Glass 01 May '20

01 May '20

This series creates a new 64-bit 'coreboot64' build which can be launched from coreboot. It uses SPL to effect the jump to 64-bit mode. This was done in an attempt to get the Ubuntu FirmwareTestSuite[1] working. Unfortunately the latest version shows a splash screen and hangs, perhaps due to some missing EFI support. [1] https://wiki.ubuntu.com/FirmwareTestSuite Changes in v3: - Add new patch to make coreboot detection work in 64-bit code - Show bit width for all archs, use sizeof(void *) Changes in v2: - Add a new patch to indicate 32/64-bit in bdinfo Simon Glass (7): x86: Move coreboot-table detection to common 32/64-bit code x86: Allow building an SPL image for coreboot x86: Move work-around out of cpu_jump_to_64bit_uboot() x86: Update SPL for coreboot x86: coreboot: Allow building an SPL image x86: Add an indication of 32/64-bit to bdinfo x86: Add a 64-bit coreboot build Makefile | 6 ++++ arch/x86/cpu/Makefile | 4 ++- arch/x86/cpu/coreboot/Kconfig | 1 + arch/x86/cpu/coreboot/Makefile | 8 ++++- arch/x86/cpu/coreboot/coreboot.c | 3 +- arch/x86/cpu/coreboot/coreboot_spl.c | 12 +++++++ arch/x86/cpu/cpu.c | 25 +++++++++++++++ arch/x86/cpu/i386/cpu.c | 36 +-------------------- arch/x86/cpu/intel_common/Makefile | 2 ++ arch/x86/cpu/x86_64/cpu.c | 2 ++ arch/x86/dts/coreboot-u-boot.dtsi | 18 +++++++++++ arch/x86/lib/spl.c | 23 ++++++++++--- board/coreboot/coreboot/MAINTAINERS | 7 ++++ cmd/bdinfo.c | 20 ++++++++++++ configs/coreboot64_defconfig | 48 ++++++++++++++++++++++++++++ doc/board/coreboot/coreboot.rst | 10 ++++++ 16 files changed, 183 insertions(+), 42 deletions(-) create mode 100644 arch/x86/cpu/coreboot/coreboot_spl.c create mode 100644 arch/x86/dts/coreboot-u-boot.dtsi create mode 100644 configs/coreboot64_defconfig -- 2.26.2.526.g744177e7f7-goog

3 23

[PATCH v4 6/7] x86: Add an indication of 32/64-bit to bdinfo
by Simon Glass 01 May '20

01 May '20

It is useful to know what mode U-Boot is running in. Add a message at the end of the 'bdinfo' output. Signed-off-by: Simon Glass <sjg(a)chromium.org> Suggested-by: Mark Kettenis <kettenis(a)openbsd.org> --- Changes in v4: - Fix signed/unsigned mismatch in printf() Changes in v3: - Show bit width for all archs, use sizeof(void *) Changes in v2: - Add a new patch to indicate 32/64-bit in bdinfo cmd/bdinfo.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index d6a7175b37..9edcf8d74e 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -15,6 +15,11 @@ DECLARE_GLOBAL_DATA_PTR; +__maybe_unused void print_cpu_word_size(void) +{ + printf("%-12s= %u-bit\n", "Build", (uint)sizeof(void *) * 8); +} + __maybe_unused static void print_num(const char *name, ulong value) { @@ -208,6 +213,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_baudrate(); print_num("relocaddr", gd->relocaddr); board_detail(); + print_cpu_word_size(); + return 0; } @@ -227,6 +234,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); return 0; } @@ -252,6 +260,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_num("fdt_blob", (ulong)gd->fdt_blob); print_num("new_fdt", (ulong)gd->new_fdt); print_num("fdt_size", (ulong)gd->fdt_size); + print_cpu_word_size(); return 0; } @@ -283,6 +292,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #endif print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); return 0; } @@ -294,6 +304,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_std_bdinfo(gd->bd); print_num("relocaddr", gd->relocaddr); print_num("reloc off", gd->reloc_off); + print_cpu_word_size(); return 0; } @@ -354,6 +365,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, #endif if (gd->fdt_blob) print_num("fdt_blob", (ulong)gd->fdt_blob); + print_cpu_word_size(); return 0; } @@ -368,6 +380,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_bi_flash(bd); print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); + return 0; } @@ -388,6 +402,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_mhz("ethspeed", bd->bi_ethspeed); #endif print_baudrate(); + print_cpu_word_size(); return 0; } @@ -405,6 +420,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) print_num("FB base ", gd->fb_base); #endif + print_cpu_word_size(); + return 0; } @@ -419,6 +436,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_bi_dram(bd); print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); return 0; } @@ -435,6 +453,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_num("reloc off", gd->reloc_off); print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); return 0; } @@ -448,6 +467,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_bi_mem(bd); print_eth_ip_addr(); print_baudrate(); + print_cpu_word_size(); return 0; } -- 2.26.2.526.g744177e7f7-goog

3 3

[v2 01/27] rtc: ds1337: Add driver model support
by Biwen Li 01 May '20

01 May '20

From: Biwen Li <biwen.li(a)nxp.com> Add support of driver model of ds1337 Signed-off-by: Biwen Li <biwen.li(a)nxp.com> --- drivers/rtc/ds1337.c | 127 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/drivers/rtc/ds1337.c b/drivers/rtc/ds1337.c index 9b31048e97..e12d368675 100644 --- a/drivers/rtc/ds1337.c +++ b/drivers/rtc/ds1337.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2001-2008 + * Copyright 2020 NXP * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * Keith Outwater, keith_outwater(a)mvis.com` */ @@ -12,6 +13,7 @@ #include <common.h> #include <command.h> +#include <dm.h> #include <rtc.h> #include <i2c.h> @@ -60,6 +62,7 @@ #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ +#if !CONFIG_IS_ENABLED(DM_RTC) static uchar rtc_read (uchar reg); static void rtc_write (uchar reg, uchar val); @@ -188,3 +191,127 @@ static void rtc_write (uchar reg, uchar val) { i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } +#else +static uchar rtc_read (struct udevice *dev, uchar reg) +{ + return (dm_i2c_reg_read (dev, reg)); +} + +static void rtc_write (struct udevice *dev, uchar reg, uchar val) +{ + dm_i2c_reg_write (dev, reg, val); +} + +static int ds1337_rtc_get (struct udevice *dev, struct rtc_time *tmp) +{ + int rel = 0; + uchar sec, min, hour, mday, wday, mon_cent, year, control, status; + + control = rtc_read (dev, RTC_CTL_REG_ADDR); + status = rtc_read (dev, RTC_STAT_REG_ADDR); + sec = rtc_read (dev, RTC_SEC_REG_ADDR); + min = rtc_read (dev, RTC_MIN_REG_ADDR); + hour = rtc_read (dev, RTC_HR_REG_ADDR); + wday = rtc_read (dev, RTC_DAY_REG_ADDR); + mday = rtc_read (dev, RTC_DATE_REG_ADDR); + mon_cent = rtc_read (dev, RTC_MON_REG_ADDR); + year = rtc_read (dev, RTC_YR_REG_ADDR); + + /* No century bit, assume year 2000 */ +#ifdef CONFIG_RTC_DS1388 + mon_cent |= 0x80; +#endif + + debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " + "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", + year, mon_cent, mday, wday, hour, min, sec, control, status); + + if (status & RTC_STAT_BIT_OSF) { + printf ("### Warning: RTC oscillator has stopped\n"); + /* clear the OSF flag */ + rtc_write (dev, RTC_STAT_REG_ADDR, + rtc_read (dev, RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); + rel = -1; + } + + tmp->tm_sec = bcd2bin (sec & 0x7F); + tmp->tm_min = bcd2bin (min & 0x7F); + tmp->tm_hour = bcd2bin (hour & 0x3F); + tmp->tm_mday = bcd2bin (mday & 0x3F); + tmp->tm_mon = bcd2bin (mon_cent & 0x1F); + tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900); + tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); + tmp->tm_yday = 0; + tmp->tm_isdst= 0; + + debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + return rel; +} + +static int ds1337_rtc_set (struct udevice *dev, const struct rtc_time *tmp) +{ + uchar century; + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + rtc_write (dev, RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); + + century = (tmp->tm_year >= 2000) ? 0x80 : 0; + rtc_write (dev, RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century); + + rtc_write (dev, RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); + rtc_write (dev, RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); + rtc_write (dev, RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); + rtc_write (dev, RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); + rtc_write (dev, RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); + + return 0; +} + +#ifdef CONFIG_RTC_DS1337_NOOSC + #define RTC_DS1337_RESET_VAL \ + (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) +#else + #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) +#endif +static int ds1337_rtc_reset (struct udevice *dev) +{ +#ifdef CONFIG_RTC_DS1337 + rtc_write (dev, RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); +#elif defined CONFIG_RTC_DS1388 + rtc_write(dev, RTC_CTL_REG_ADDR, 0x0); /* hw default */ +#endif +#ifdef CONFIG_RTC_DS1339_TCR_VAL + rtc_write (dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL); +#endif +#ifdef CONFIG_RTC_DS1388_TCR_VAL + rtc_write(dev, RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL); +#endif + return 0; +} + +static const struct rtc_ops ds1337_rtc_ops = { + .get = ds1337_rtc_get, + .set = ds1337_rtc_set, + .reset = ds1337_rtc_reset, +}; + +static const struct udevice_id ds1337_rtc_ids[] = { + { .compatible = "ds1337" }, + { .compatible = "ds1338" }, + { .compatible = "ds1338" }, + { } +}; + +U_BOOT_DRIVER(rtc_ds1337) = { + .name = "rtc-ds1337", + .id = UCLASS_RTC, + .of_match = ds1337_rtc_ids, + .ops = &ds1337_rtc_ops, +}; +#endif -- 2.17.1

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[RESEND 1/4] powerpc: Enable device tree support for P1010RDB
by Biwen Li 01 May '20

01 May '20

From: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Add device tree for P1010RDB boards and enable CONFIG_OF_CONTROL so that device tree can be compiled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> --- arch/powerpc/dts/Makefile | 2 + arch/powerpc/dts/p1010rdb-pa.dts | 17 +++ arch/powerpc/dts/p1010rdb-pa_36b.dts | 17 +++ arch/powerpc/dts/p1010rdb-pb.dts | 17 +++ arch/powerpc/dts/p1010rdb-pb_36b.dts | 17 +++ arch/powerpc/dts/p1010rdb_32b.dtsi | 22 ++++ arch/powerpc/dts/p1010rdb_36b.dtsi | 22 ++++ arch/powerpc/dts/p1010si-post.dtsi | 46 +++++++ arch/powerpc/dts/p1010si-pre.dtsi | 27 ++++ configs/P1010RDB-PA_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PA_36BIT_NOR_defconfig | 4 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 3 +- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 3 +- configs/P1010RDB-PA_NAND_defconfig | 3 +- configs/P1010RDB-PA_NOR_defconfig | 4 +- configs/P1010RDB-PA_SDCARD_defconfig | 3 +- configs/P1010RDB-PA_SPIFLASH_defconfig | 3 +- configs/P1010RDB-PB_36BIT_NAND_defconfig | 3 +- configs/P1010RDB-PB_36BIT_NOR_defconfig | 4 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 3 +- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 3 +- configs/P1010RDB-PB_NAND_defconfig | 3 +- configs/P1010RDB-PB_NOR_defconfig | 4 +- configs/P1010RDB-PB_SDCARD_defconfig | 3 +- configs/P1010RDB-PB_SPIFLASH_defconfig | 3 +- p1010rdb-pb.dts | 123 +++++++++++++++++++ 26 files changed, 346 insertions(+), 16 deletions(-) create mode 100644 arch/powerpc/dts/p1010rdb-pa.dts create mode 100644 arch/powerpc/dts/p1010rdb-pa_36b.dts create mode 100644 arch/powerpc/dts/p1010rdb-pb.dts create mode 100644 arch/powerpc/dts/p1010rdb-pb_36b.dts create mode 100644 arch/powerpc/dts/p1010rdb_32b.dtsi create mode 100644 arch/powerpc/dts/p1010rdb_36b.dtsi create mode 100644 arch/powerpc/dts/p1010si-post.dtsi create mode 100644 arch/powerpc/dts/p1010si-pre.dtsi create mode 100644 p1010rdb-pb.dts diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 3195351c9c..7eb005f450 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb +dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb +dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts new file mode 100644 index 0000000000..c66c4923ac --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pa.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB"; + compatible = "fsl,P1010RDB"; + + /include/ "p1010rdb_32b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts new file mode 100644 index 0000000000..b943de7cbb --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB"; + compatible = "fsl,P1010RDB"; + + /include/ "p1010rdb_36b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pb.dts b/arch/powerpc/dts/p1010rdb-pb.dts new file mode 100644 index 0000000000..2675d5d92b --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB-PB"; + compatible = "fsl,P1010RDB-PB"; + + /include/ "p1010rdb_32b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pb_36b.dts b/arch/powerpc/dts/p1010rdb-pb_36b.dts new file mode 100644 index 0000000000..45ccf91c41 --- /dev/null +++ b/arch/powerpc/dts/p1010rdb-pb_36b.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +/include/ "p1010si-pre.dtsi" + +/ { + model = "fsl,P1010RDB-PB"; + compatible = "fsl,P1010RDB-PB"; + + /include/ "p1010rdb_36b.dtsi" +}; + +/include/ "p1010si-post.dtsi" diff --git a/arch/powerpc/dts/p1010rdb_32b.dtsi b/arch/powerpc/dts/p1010rdb_32b.dtsi new file mode 100644 index 0000000000..5da790da5e --- /dev/null +++ b/arch/powerpc/dts/p1010rdb_32b.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source + * + * Copyright 2020 NXP + */ + +soc: soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; +}; + +pci1: pcie@ffe09000 { + reg = <0 0xffe09000 0 0x1000>; + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; +}; + +pci0: pcie@ffe0a000 { + reg = <0 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; +}; diff --git a/arch/powerpc/dts/p1010rdb_36b.dtsi b/arch/powerpc/dts/p1010rdb_36b.dtsi new file mode 100644 index 0000000000..54dd16e43b --- /dev/null +++ b/arch/powerpc/dts/p1010rdb_36b.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010RDB Device Tree Source (36-bit address map) + * + * Copyright 2020 NXP + */ + +soc: soc@fffe00000 { + ranges = <0x0 0xf 0xffe00000 0x100000>; +}; + +pci1: pcie@fffe09000 { + reg = <0xf 0xffe09000 0 0x1000>; + ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +}; + +pci0: pcie@fffe0a000 { + reg = <0xf 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; +}; diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi new file mode 100644 index 0000000000..e24b5e4063 --- /dev/null +++ b/arch/powerpc/dts/p1010si-post.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2020 NXP + */ + +&soc { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,p1010-immr", "simple-bus"; + bus-frequency = <0>; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <255>; + }; +}; + +/* controller at 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* controller at 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/p1010si-pre.dtsi b/arch/powerpc/dts/p1010si-pre.dtsi new file mode 100644 index 0000000000..9d7bb6c95d --- /dev/null +++ b/arch/powerpc/dts/p1010si-pre.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1010 Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2020 NXP + */ + +/dts-v1/; + +/include/ "e500v2_power_isa.dtsi" + +/ { + compatible = "fsl,P1010"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,P1010@0 { + device_type = "cpu"; + reg = <0x0>; + }; + }; +}; diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 85b97d1e15..b0dd5f8f7e 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" @@ -76,6 +78,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index e1109637c1..93042f8cc8 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -57,6 +60,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 4b8ddd997c..657b10033b 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -70,6 +72,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 2975f404fc..396921722d 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -72,6 +74,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 632ecd7af5..b080bb726b 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y @@ -75,6 +77,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 037fe0ab89..a5296a53a5 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -56,6 +59,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 48a1d34cc9..1df83cefe3 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -69,6 +71,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index f43c60011c..6bff366f81 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -71,6 +73,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index dd7d689163..abf8882f21 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" @@ -76,6 +78,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 7e8c150603..beb8f098c4 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -57,6 +60,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 7996490e93..7244dacec0 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -70,6 +72,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 4291002d34..1d40aa054b 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" +CONFIG_OF_CONTROL=y CONFIG_PHYS_64BIT=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -72,6 +74,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 4a216dd55b..0d9df36ea1 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xFF800000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_SYS_CUSTOM_LDSCRIPT=y CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y @@ -75,6 +77,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 2cc52ed76d..653c89bfdd 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -3,7 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -56,6 +59,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index d90cc8e7bb..7bc05e57ba 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -69,6 +71,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index e6833d43e3..16976e4a88 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -13,6 +13,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_TEXT_BASE=0xD0001000 CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y +CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" +CONFIG_OF_CONTROL=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -71,6 +73,5 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y CONFIG_DM_I2C=y CONFIG_DM_RTC=y diff --git a/p1010rdb-pb.dts b/p1010rdb-pb.dts new file mode 100644 index 0000000000..7e9a6e17d8 --- /dev/null +++ b/p1010rdb-pb.dts @@ -0,0 +1,123 @@ +/dts-v1/; + +/ { + compatible = "fsl,P1010RDB-PB"; + #address-cells = <0x2>; + #size-cells = <0x2>; + interrupt-parent = <0x1>; + model = "fsl,P1010RDB-PB"; + + cpus { + power-isa-version = "2.03"; + power-isa-b; + power-isa-e; + power-isa-atb; + power-isa-cs; + power-isa-e.le; + power-isa-e.pm; + power-isa-ecl; + power-isa-mmc; + power-isa-sp; + power-isa-sp.fd; + power-isa-sp.fs; + power-isa-sp.fv; + mmu-type = "power-embedded"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + PowerPC,P1010@0 { + device_type = "cpu"; + reg = <0x0>; + }; + }; + + soc@ffe00000 { + ranges = <0x0 0x0 0xffe00000 0x100000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + device_type = "soc"; + compatible = "fsl,p1010-immr", "simple-bus"; + bus-frequency = <0x0>; + + pic@40000 { + interrupt-controller; + #address-cells = <0x0>; + #interrupt-cells = <0x4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic"; + device_type = "open-pic"; + big-endian; + single-cpu-affinity; + last-interrupt-source = <0xff>; + phandle = <0x1>; + }; + + i2c@3000 { + #address-cells = <0x1>; + #size-cells = <0x0>; + cell-index = <0x0>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x3000 0x100>; + interrupts = <0x2b 0x2 0x0 0x0>; + + rtc@68 { + compatible = "pericom,pt7c4338"; + reg = <0x68>; + }; + }; + + i2c@3100 { + #address-cells = <0x1>; + #size-cells = <0x0>; + cell-index = <0x1>; + compatible = "fsl-i2c"; + u-boot,dm-pre-reloc; + reg = <0x3100 0x100>; + interrupts = <0x2b 0x2 0x0 0x0>; + }; + }; + + pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; + ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000 0x1000000 0x0 0x0 0x0 0xffc10000 0x0 0x10000>; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <0x1>; + #address-cells = <0x3>; + #size-cells = <0x2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + }; + + pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0x0 0xffc00000 0x0 0x10000>; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <0x2>; + #address-cells = <0x3>; + #size-cells = <0x2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + }; + + binman { + filename = "u-boot-with-dtb.bin"; + skip-at-start = <0xeff40000>; + sort-by-offset; + pad-byte = <0xff>; + size = <0xc0000>; + + u-boot-with-ucode-ptr { + offset = <0xeff40000>; + optional-ucode; + }; + + u-boot-dtb-with-ucode { + align = <0x100>; + }; + + powerpc-mpc85xx-bootpg-resetvec { + offset = <0xeffff000>; + }; + }; +}; -- 2.17.1

2 4

am65x build issues
by Jan Kiszka 01 May '20

01 May '20

Hi all, I've noticed that building am65x_evm_a53_defconfig causes the dtbs to be built twice, once for the main u-boot and once for the spl. This is because of an extra dependency in mach-k3/config_secure.mk added by 508369672ca3. Why should the produced dtbs depend on the target that produces them? Why not simply this? diff --git a/arch/arm/mach-k3/config_secure.mk b/arch/arm/mach-k3/config_secure.mk index 6d63c57665..cbe9b684fb 100644 --- a/arch/arm/mach-k3/config_secure.mk +++ b/arch/arm/mach-k3/config_secure.mk @@ -34,11 +34,8 @@ MKIMAGEFLAGS_u-boot.img_HS = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ $(patsubst %,-b arch/$(ARCH)/dts/%.dtb_HS,$(subst ",,$(CONFIG_OF_LIST))) -OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -$(OF_LIST_TARGETS): dtbs - u-boot-nodtb.bin_HS: u-boot-nodtb.bin FORCE $(call if_changed,k3secureimg) -u-boot.img_HS: u-boot-nodtb.bin_HS u-boot.img $(patsubst %.dtb,%.dtb_HS,$(OF_LIST_TARGETS)) FORCE +u-boot.img_HS: u-boot-nodtb.bin_HS u-boot.img dtbs FORCE $(call if_changed,mkimage) Disclaimer: I didn't actually test the HS path, just the unsigned build. But also with this change, make -j remains broken for this target: [...] COPY u-boot.dtb MKIMAGE u-boot-dtb.img MKIMAGE u-boot.img CAT u-boot-dtb.bin COPY u-boot.bin CC spl/./lib/asm-offsets.s CC spl/./arch/arm/lib/asm-offsets.s ../tools/k3_fit_atf.sh \ spl/dts/k3-am654-base-board.dtb > u-boot-spl-k3.its LDS spl/u-boot-spl.lds FDTGREP spl/dts/k3-am654-base-board.dtb Usage: fdtgrep - extract portions from device tree [...] Error: Cannot open output file make[2]: *** [../scripts/Makefile.spl:465: spl/dts/k3-am654-base-board.dtb] Error 1 make[2]: *** Waiting for unfinished jobs.... Something is fishy with dependencies here. Any ideas? Thanks, Jan

2 2

[PATCH v2 1/2] Revert "kbuild: remove unused dtc-version.sh script"
by Simon Glass 01 May '20

01 May '20

We need this to make building dtc optional. It makes no sense to build our own dtc if the system one works correctly. This reverts commit ddb87a0b40262ff99d675e946f57427642303938. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- scripts/Kbuild.include | 1 + scripts/dtc-version.sh | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100755 scripts/dtc-version.sh diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index dfb67226b0..b34dedade7 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -152,6 +152,7 @@ cc-ifversion = $(shell [ $(cc-version) $(1) $(2) ] && echo $(3) || echo $(4)) # added for U-Boot binutils-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/binutils-version.sh $(AS)) +dtc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/dtc-version.sh $(DTC)) # cc-ldoption # Usage: ldflags += $(call cc-ldoption, -Wl$(comma)--hash-style=both) diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh new file mode 100755 index 0000000000..0744c39eb0 --- /dev/null +++ b/scripts/dtc-version.sh @@ -0,0 +1,21 @@ +#!/bin/sh +# +# dtc-version dtc-command +# +# Prints the dtc version of `dtc-command' in a canonical 6-digit form +# such as `010404' for dtc 1.4.4 +# + +dtc="$*" + +if [ ${#dtc} -eq 0 ]; then + echo "Error: No dtc command specified." + printf "Usage:\n\t$0 <dtc-command>\n" + exit 1 +fi + +MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1) +MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2) +PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1) + +printf "%02d%02d%02d\\n" $MAJOR $MINOR $PATCH -- 2.26.2.303.gf8c07b1a785-goog

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