May 2020 - U-Boot

[U-Boot] [PATCH 00/29] Add the SPI DM support for PPC
by Xiaowei Bao 12 May '20

12 May '20

Add the SPI DM support for PPC. depends on: http://patchwork.ozlabs.org/project/uboot/list/?series=127282 Xiaowei Bao (29): dts: P1020: Add ESPI DT nodes dts: P1020RDB: Add ESPI slave device node configs: P1020RDB: Enable ESPI driver dts: P2020: Add ESPI DT nodes dts: P2020RDB: Add ESPI slave device node configs: P2020RDB: Enable ESPI driver dts: P2041: Add ESPI DT nodes dts: P2041RDB: Add ESPI slave device node configs: P2041RDB: Enable ESPI driver dts: P3041: Add ESPI DT nodes dts: P3041DS: Add ESPI slave device node configs: P3041DS: Enable ESPI driver dts: P4080: Add ESPI DT nodes dts: P4080DS: Add ESPI slave device node configs: P4080DS: Enable ESPI driver dts: P5040: Add ESPI DT nodes dts: P5040DS: Add ESPI slave device node configs: P5040DS: Enable ESPI driver dts: T102x: Add ESPI DT nodes dts: T1024RDB: Add ESPI slave device node configs: T1024RDB: Enable ESPI driver dts: T104x: Add ESPI DT nodes dts: T1042D4RDB: Add ESPI slave device node configs: T1042D4RDB: Enable ESPI driver dts: T2080RDB: Add ESPI slave device node configs: T2080RDB: Enable ESPI driver dts: T4240: Add ESPI DT nodes dts: T4240RDB: Add ESPI slave device node configs: T4240RDB: Enable ESPI driver arch/powerpc/dts/p1020-post.dtsi | 9 +++++++++ arch/powerpc/dts/p1020rdb-pc.dts | 15 +++++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 15 +++++++++++++++ arch/powerpc/dts/p1020rdb-pd.dts | 15 +++++++++++++++ arch/powerpc/dts/p2020-post.dtsi | 9 +++++++++ arch/powerpc/dts/p2020rdb-pc.dts | 15 +++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 15 +++++++++++++++ arch/powerpc/dts/p2041.dtsi | 9 +++++++++ arch/powerpc/dts/p2041rdb.dts | 14 ++++++++++++++ arch/powerpc/dts/p3041.dtsi | 9 +++++++++ arch/powerpc/dts/p3041ds.dts | 14 ++++++++++++++ arch/powerpc/dts/p4080.dtsi | 9 +++++++++ arch/powerpc/dts/p4080ds.dts | 14 ++++++++++++++ arch/powerpc/dts/p5040.dtsi | 9 +++++++++ arch/powerpc/dts/p5040ds.dts | 14 ++++++++++++++ arch/powerpc/dts/t1024rdb.dts | 15 +++++++++++++++ arch/powerpc/dts/t102x.dtsi | 9 +++++++++ arch/powerpc/dts/t1042d4rdb.dts | 15 +++++++++++++++ arch/powerpc/dts/t104x.dtsi | 9 +++++++++ arch/powerpc/dts/t2080rdb.dts | 15 +++++++++++++++ arch/powerpc/dts/t4240.dtsi | 9 +++++++++ arch/powerpc/dts/t4240rdb.dts | 15 +++++++++++++++ configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_defconfig | 2 ++ configs/P1020RDB-PC_NAND_defconfig | 2 ++ configs/P1020RDB-PC_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_defconfig | 2 ++ configs/P1020RDB-PD_NAND_defconfig | 2 ++ configs/P1020RDB-PD_SDCARD_defconfig | 2 ++ configs/P1020RDB-PD_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PD_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_defconfig | 2 ++ configs/P2020RDB-PC_NAND_defconfig | 2 ++ configs/P2020RDB-PC_SDCARD_defconfig | 2 ++ configs/P2020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P2020RDB-PC_defconfig | 2 ++ configs/P2041RDB_NAND_defconfig | 2 ++ configs/P2041RDB_SDCARD_defconfig | 2 ++ configs/P2041RDB_SPIFLASH_defconfig | 2 ++ configs/P2041RDB_defconfig | 2 ++ configs/P3041DS_NAND_defconfig | 2 ++ configs/P3041DS_SDCARD_defconfig | 2 ++ configs/P3041DS_SPIFLASH_defconfig | 2 ++ configs/P3041DS_defconfig | 2 ++ configs/P4080DS_SDCARD_defconfig | 2 ++ configs/P4080DS_SPIFLASH_defconfig | 2 ++ configs/P4080DS_defconfig | 2 ++ configs/P5040DS_NAND_defconfig | 2 ++ configs/P5040DS_SDCARD_defconfig | 2 ++ configs/P5040DS_SPIFLASH_defconfig | 2 ++ configs/P5040DS_defconfig | 2 ++ configs/T1024RDB_NAND_defconfig | 2 ++ configs/T1024RDB_SDCARD_defconfig | 2 ++ configs/T1024RDB_SPIFLASH_defconfig | 2 ++ configs/T1024RDB_defconfig | 2 ++ configs/T1042D4RDB_NAND_defconfig | 2 ++ configs/T1042D4RDB_SDCARD_defconfig | 2 ++ configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++ configs/T1042D4RDB_defconfig | 2 ++ configs/T2080RDB_NAND_defconfig | 2 ++ configs/T2080RDB_SDCARD_defconfig | 2 ++ configs/T2080RDB_SPIFLASH_defconfig | 2 ++ configs/T2080RDB_defconfig | 2 ++ configs/T4240RDB_SDCARD_defconfig | 2 ++ configs/T4240RDB_defconfig | 2 ++ 71 files changed, 370 insertions(+) -- 2.9.5

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[PATCH 1/3] cmd: optee_rpmb command for read/write of rpmb from optee
by Ruchika Gupta 12 May '20

12 May '20

Enable "optee_rpmb" command to write/read named persistent values created on RPMB by opening session with OPTEE AVB TA. This provides easy test for establishing a session with OPTEE TA and storage of persistent data in MMC RPMB. It includes following subcommands: optee_rpmb read_pvalue - read persistent values on rpmb via OPTEE AVB TA optee_rpmb write_pvalue - write persistent values on rpmb via OPTEE AVB TA Signed-off-by: Ruchika Gupta <ruchika.gupta(a)nxp.com> --- cmd/Kconfig | 16 +++ cmd/Makefile | 1 + cmd/optee_rpmb.c | 269 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 286 insertions(+) create mode 100644 cmd/optee_rpmb.c diff --git a/cmd/Kconfig b/cmd/Kconfig index 6ce9e5521c..b5dc571e60 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1088,6 +1088,14 @@ config CMD_MMC_SWRITE endif +config CMD_OPTEE_RPMB + bool "Enable read/write support on RPMB via OPTEE" + depends on SUPPORT_EMMC_RPMB && OPTEE + help + Enable the commands for reading, writing persistent named values + in the Replay Protection Memory Block partition in eMMC by + using Persistent Objects in OPTEE + config CMD_MTD bool "mtd" depends on MTD @@ -1137,6 +1145,14 @@ config CMD_ONENAND and erasing blocks. It allso provides a way to show and change bad blocks, and test the device. +config CMD_OPTEE_RPMB + bool "Enable read/write support on RPMB via OPTEE" + depends on SUPPORT_EMMC_RPMB && OPTEE + help + Enable the commands for reading, writing persistent named values + in the Replay Protection Memory Block partition in eMMC by + using Persistent Objects in OPTEE + config CMD_OSD bool "osd" help diff --git a/cmd/Makefile b/cmd/Makefile index 6692ed96c6..0159493a13 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -92,6 +92,7 @@ obj-$(CONFIG_CMD_MII) += mii.o obj-$(CONFIG_CMD_MDIO) += mdio.o obj-$(CONFIG_CMD_MISC) += misc.o obj-$(CONFIG_CMD_MMC) += mmc.o +obj-$(CONFIG_CMD_OPTEE_RPMB) += optee_rpmb.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_CMD_MTD) += mtd.o obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o diff --git a/cmd/optee_rpmb.c b/cmd/optee_rpmb.c new file mode 100644 index 0000000000..829d1268f7 --- /dev/null +++ b/cmd/optee_rpmb.c @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <command.h> +#include <common.h> +#include <env.h> +#include <errno.h> +#include <image.h> +#include <malloc.h> +#include <mmc.h> +#include <tee.h> +#include <tee/optee_ta_avb.h> + +struct udevice *tee; +u32 session; + +static int avb_ta_open_session(void) +{ + const struct tee_optee_ta_uuid uuid = TA_AVB_UUID; + struct tee_open_session_arg arg; + int rc; + + tee = tee_find_device(tee, NULL, NULL, NULL); + if (!tee) + return -ENODEV; + + memset(&arg, 0, sizeof(arg)); + tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); + rc = tee_open_session(tee, &arg, 0, NULL); + if (!rc) + session = arg.session; + + return 0; +} + +static int invoke_func(u32 func, ulong num_param, struct tee_param *param) +{ + struct tee_invoke_arg arg; + + if (!tee) + if (avb_ta_open_session()) + return -ENODEV; + + memset(&arg, 0, sizeof(arg)); + arg.func = func; + arg.session = session; + + if (tee_invoke_func(tee, &arg, num_param, param)) + return -EFAULT; + switch (arg.ret) { + case TEE_SUCCESS: + return 0; + case TEE_ERROR_OUT_OF_MEMORY: + case TEE_ERROR_STORAGE_NO_SPACE: + return -ENOSPC; + case TEE_ERROR_ITEM_NOT_FOUND: + return -EIO; + case TEE_ERROR_TARGET_DEAD: + /* + * The TA has paniced, close the session to reload the TA + * for the next request. + */ + tee_close_session(tee, session); + tee = NULL; + return -EIO; + default: + return -EIO; + } +} + +static int read_persistent_value(const char *name, + size_t buffer_size, + u8 *out_buffer, + size_t *out_num_bytes_read) +{ + int rc = 0; + struct tee_shm *shm_name; + struct tee_shm *shm_buf; + struct tee_param param[2]; + size_t name_size = strlen(name) + 1; + + if (!tee) + if (avb_ta_open_session()) + return -ENODEV; + + rc = tee_shm_alloc(tee, name_size, + TEE_SHM_ALLOC, &shm_name); + if (rc) + return -ENOMEM; + + rc = tee_shm_alloc(tee, buffer_size, + TEE_SHM_ALLOC, &shm_buf); + if (rc) { + rc = -ENOMEM; + goto free_name; + } + + memcpy(shm_name->addr, name, name_size); + + memset(param, 0, sizeof(param)); + param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[0].u.memref.shm = shm_name; + param[0].u.memref.size = name_size; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INOUT; + param[1].u.memref.shm = shm_buf; + param[1].u.memref.size = buffer_size; + + rc = invoke_func(TA_AVB_CMD_READ_PERSIST_VALUE, + 2, param); + if (rc) + goto out; + + if (param[1].u.memref.size > buffer_size) { + rc = -EINVAL; + goto out; + } + + *out_num_bytes_read = param[1].u.memref.size; + + memcpy(out_buffer, shm_buf->addr, *out_num_bytes_read); + +out: + tee_shm_free(shm_buf); +free_name: + tee_shm_free(shm_name); + + return rc; +} + +static int write_persistent_value(const char *name, + size_t value_size, + const u8 *value) +{ + int rc = 0; + struct tee_shm *shm_name; + struct tee_shm *shm_buf; + struct tee_param param[2]; + size_t name_size = strlen(name) + 1; + + if (!tee) { + if (avb_ta_open_session()) + return -ENODEV; + } + if (!value_size) + return -EINVAL; + + rc = tee_shm_alloc(tee, name_size, + TEE_SHM_ALLOC, &shm_name); + if (rc) + return -ENOMEM; + + rc = tee_shm_alloc(tee, value_size, + TEE_SHM_ALLOC, &shm_buf); + if (rc) { + rc = -ENOMEM; + goto free_name; + } + + memcpy(shm_name->addr, name, name_size); + memcpy(shm_buf->addr, value, value_size); + + memset(param, 0, sizeof(param)); + param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[0].u.memref.shm = shm_name; + param[0].u.memref.size = name_size; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[1].u.memref.shm = shm_buf; + param[1].u.memref.size = value_size; + + rc = invoke_func(TA_AVB_CMD_WRITE_PERSIST_VALUE, + 2, param); + if (rc) + goto out; + +out: + tee_shm_free(shm_buf); +free_name: + tee_shm_free(shm_name); + + return rc; +} + +int do_optee_rpmb_read(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + const char *name; + size_t bytes; + size_t bytes_read; + void *buffer; + char *endp; + + if (argc != 3) + return CMD_RET_USAGE; + + name = argv[1]; + bytes = simple_strtoul(argv[2], &endp, 10); + if (*endp && *endp != '\n') + return CMD_RET_USAGE; + + buffer = malloc(bytes); + if (!buffer) + return CMD_RET_FAILURE; + + if (read_persistent_value(name, bytes, buffer, &bytes_read) == 0) { + printf("Read %zu bytes, value = %s\n", bytes_read, + (char *)buffer); + free(buffer); + return CMD_RET_SUCCESS; + } + + printf("Failed to read persistent value\n"); + + free(buffer); + + return CMD_RET_FAILURE; +} + +int do_optee_rpmb_write(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + const char *name; + const char *value; + + if (argc != 3) + return CMD_RET_USAGE; + + name = argv[1]; + value = argv[2]; + + if (write_persistent_value(name, strlen(value) + 1, + (const uint8_t *)value) == 0) { + printf("Wrote %zu bytes\n", strlen(value) + 1); + return CMD_RET_SUCCESS; + } + + printf("Failed to write persistent value\n"); + + return CMD_RET_FAILURE; +} + +static cmd_tbl_t cmd_optee_rpmb[] = { + U_BOOT_CMD_MKENT(read_pvalue, 3, 0, do_optee_rpmb_read, "", ""), + U_BOOT_CMD_MKENT(write_pvalue, 3, 0, do_optee_rpmb_write, "", ""), +}; + +static int do_optee_rpmb(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + cmd_tbl_t *cp; + + cp = find_cmd_tbl(argv[1], cmd_optee_rpmb, ARRAY_SIZE(cmd_optee_rpmb)); + + argc--; + argv++; + + if (!cp || argc > cp->maxargs) + return CMD_RET_USAGE; + + if (flag == CMD_FLAG_REPEAT) + return CMD_RET_FAILURE; + + return cp->cmd(cmdtp, flag, argc, argv); +} + +U_BOOT_CMD( + optee_rpmb, 29, 0, do_optee_rpmb, + "Provides commands for testing secure storage on RPMB on OPTEE", + "read_pvalue <name> <bytes> - read a persistent value <name>\n" + "optee_rpmb write_pvalue <name> <value> - write a persistent value <name>\n" + ); -- 2.17.1

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[PATCH v7 00/22] RISC-V SiFive FU540 support SPL
by Pragnesh Patel 12 May '20

12 May '20

This series add support for SPL to FU540.U-Boot SPL can boot from L2 LIM (0x0800_0000) and jump to OpenSBI(FW_DYNAMIC firmware) and U-Boot proper from MMC devices. How to test this patch: 1) Go to OpenSBI-dir : make PLATFORM=generic FW_DYNAMIC=y 2) export OPENSBI=<path/to/opensbi/install_dir/platform/generic/firmware/fw_dynamic.bin> 3) Change to u-boot-dir 4) make sifive_fu540_defconfig 5) make all 6) Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch) # sudo sgdisk --clear \ > --set-alignment=2 \ > --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \ > --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \ > --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \ > /dev/sda 7) sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34 8) sudo dd if=u-boot.itb of=/dev/sda seek=2082 Changes in v7: - Standardize SD gpt partition layout - Add delay for SiFive OTP driver - Use DM way for corepll and ddrpll - Add new cpu fu540 (arch/riscv/cpu/fu540) - Update document for FU540 (doc/board/sifive/fu540.rst) Changes in v6: - Typo Correction - Make fu540-c000-u-boot.dtsi and hifive-unleashed-a00-u-boot.dtsi Dual Licensed - Sync Hifive unleashed dts from Linux - Add arch/riscv/fu540 for FU540 specific code Changes in v5: - Return read/write bytes for sifive_otp_read and sifive_otp_write - Correct Palmer's email address Changes in v4: - Split misc DM driver patch into multiple patches - Added new SPL_CRC7_SUPPORT Kconfig option - Added DM driver for DDR - Added clk_enable and clk_disable ops in SiFive PRCI driver - Added early clock initialization for SPL in SiFive PRCI driver - Added SPL config options in sifive_fu540_defconfig instead of creatiing a new config file for SPL - Update fu540.rst on how to build and flash U-boot SPL Changes in v3: - Remove arch-fu540 and arch-sifive from arch/riscv/include/asm/ - Split SPL patches into DDR and SPL and spl defconfig - Update fu540/MAINTAINERS file - Update fu540.rst on how to build and flash U-boot SPL Changes in v2: - Add DM driver Sifive OTP - Split SPL patches into multiple patches - Add a seprate patch for _image_binary_end and crc7.c - Add a seprate patch to add board -u-boot.dtsi files - Update FU540 RISC-V documentation Pragnesh Patel (22): misc: add driver for the SiFive otp controller riscv: sifive: fu540: Use OTP DM driver for serial environment variable riscv: Add _image_binary_end for SPL lib: Makefile: build crc7.c when CONFIG_MMC_SPI riscv: sifive: dts: fu540: Add board -u-boot.dtsi files sifive: fu540: add ddr driver sifive: dts: fu540: Add DDR controller and phy register settings riscv: sifive: dts: fu540: add U-Boot dmc node clk: sifive: fu540-prci: Add clock enable and disable ops clk: sifive: fu540-prci: ddr and ethernet clock initialization in SPL riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux sifive: dts: fu540: Enable gpio in U-Boot SPL riscv: cpu: fu540: Add support for cpu fu540 riscv: Add place-holder for driver compilation riscv: sifive: dts: fu540: Add clock for cpus node riscv: Enable cpu clock if it is present riscv: sifive: fu540: add SPL configuration configs: fu540: Add config options for U-Boot SPL sifive: dts: fu540: Enable L2 Cache in U-Boot riscv: sifive: fu540: enable all cache ways from U-Boot proper doc: sifive: fu540: Add description for OpenSBI generic platform doc: sifive: fu540: Add description for RISC-V FU540 U-Boot SPL arch/riscv/Kconfig | 1 + arch/riscv/cpu/fu540/Kconfig | 15 + arch/riscv/cpu/fu540/Makefile | 12 + arch/riscv/cpu/fu540/cache.c | 53 + arch/riscv/cpu/fu540/cpu.c | 22 + arch/riscv/cpu/fu540/dram.c | 38 + arch/riscv/cpu/fu540/spl.c | 23 + arch/riscv/cpu/u-boot-spl.lds | 1 + arch/riscv/dts/fu540-c000-u-boot.dtsi | 91 + arch/riscv/dts/fu540-c000.dtsi | 37 +- ...fu540-hifive-unleashed-a00-sdram-ddr4.dtsi | 1489 +++++++++++++++++ .../dts/hifive-unleashed-a00-u-boot.dtsi | 22 + arch/riscv/dts/hifive-unleashed-a00.dts | 9 + arch/riscv/include/asm/arch-fu540/cache.h | 14 + arch/riscv/include/asm/arch-fu540/clk.h | 14 + arch/riscv/include/asm/arch-fu540/gpio.h | 38 + arch/riscv/include/asm/arch-fu540/spl.h | 14 + board/sifive/fu540/Kconfig | 14 +- board/sifive/fu540/Makefile | 4 + board/sifive/fu540/fu540.c | 143 +- board/sifive/fu540/spl.c | 72 + common/spl/Kconfig | 6 + configs/sifive_fu540_defconfig | 9 + doc/board/sifive/fu540.rst | 395 ++++- drivers/clk/sifive/fu540-prci.c | 193 ++- drivers/cpu/riscv_cpu.c | 33 + drivers/misc/Kconfig | 7 + drivers/misc/Makefile | 1 + drivers/misc/sifive-otp.c | 273 +++ drivers/mmc/Kconfig | 1 + drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 2 + drivers/ram/sifive/Kconfig | 13 + drivers/ram/sifive/Makefile | 6 + drivers/ram/sifive/sdram_fu540.c | 416 +++++ include/configs/sifive-fu540.h | 18 + lib/Makefile | 1 + 37 files changed, 3403 insertions(+), 98 deletions(-) create mode 100644 arch/riscv/cpu/fu540/Kconfig create mode 100644 arch/riscv/cpu/fu540/Makefile create mode 100644 arch/riscv/cpu/fu540/cache.c create mode 100644 arch/riscv/cpu/fu540/cpu.c create mode 100644 arch/riscv/cpu/fu540/dram.c create mode 100644 arch/riscv/cpu/fu540/spl.c create mode 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi create mode 100644 arch/riscv/dts/fu540-hifive-unleashed-a00-sdram-ddr4.dtsi create mode 100644 arch/riscv/include/asm/arch-fu540/cache.h create mode 100644 arch/riscv/include/asm/arch-fu540/clk.h create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h create mode 100644 arch/riscv/include/asm/arch-fu540/spl.h create mode 100644 board/sifive/fu540/spl.c create mode 100644 drivers/misc/sifive-otp.c create mode 100644 drivers/ram/sifive/Kconfig create mode 100644 drivers/ram/sifive/Makefile create mode 100644 drivers/ram/sifive/sdram_fu540.c -- 2.17.1

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[PATCH] usb: dwc3: Add versal compatibility string to dwc3 glue ids
by Michal Simek 12 May '20

12 May '20

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Xilinx Versal platform uses dwc3 and hence its compatible string needs to be added to dwc3 glue ids. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- drivers/usb/dwc3/dwc3-generic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index eabd53a36dc9..175866cf4deb 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -420,6 +420,7 @@ static int dwc3_glue_remove(struct udevice *dev) static const struct udevice_id dwc3_glue_ids[] = { { .compatible = "xlnx,zynqmp-dwc3" }, + { .compatible = "xlnx,versal-dwc3" }, { .compatible = "ti,keystone-dwc3"}, { .compatible = "ti,dwc3", .data = (ulong)&ti_ops }, { .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops }, -- 2.26.2

2 1

[PATCH] configs: ls1046a: Define ENV_ADDR value
by Kuldeep Singh 12 May '20

12 May '20

CONFIG_ENV_ADDR helps in picking environment from flash before DDR init. Define value 0x40300000 in QSPI defconfig for LS1046ARDB as value is already defined in TFA. Correct ENV_ADDR and ENV_SECT_SIZE value for LS1046AQDS as per defconfig. Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- configs/ls1046aqds_qspi_defconfig | 3 ++- configs/ls1046aqds_tfa_defconfig | 4 ++-- configs/ls1046ardb_qspi_defconfig | 1 + 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig index 22904a0..1f28ad5 100644 --- a/configs/ls1046aqds_qspi_defconfig +++ b/configs/ls1046aqds_qspi_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_LS1046AQDS=y CONFIG_SYS_TEXT_BASE=0x40100000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x300000 CONFIG_FSL_LS_PPA=y CONFIG_NR_DRAM_BANKS=2 @@ -31,6 +31,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:2m(uboot),14m(free)" CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x40300000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index df85533..18e3993 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -3,7 +3,7 @@ CONFIG_TARGET_LS1046AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_ENV_OFFSET=0x500000 CONFIG_NR_DRAM_BANKS=2 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -39,7 +39,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=0 -CONFIG_ENV_ADDR=0x60500000 +CONFIG_ENV_ADDR=0x40500000 CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index d5e0f02..d836421 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -28,6 +28,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi-0:1m(rcw),15m(u-boot),48m(kernel.i CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x40300000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -- 2.7.4

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Re: mmc: zynq_sdhci: transfer fails with 8-bit data bus
by Michal Simek 12 May '20

12 May '20

On 11. 05. 20 16:06, Benedikt Grassl wrote: > Hi, > > with commit 942b5fc0 the 8-bit data bus seems to work fine in U-Boot. > However, I have one situation where I get transfer errors lateron in > Linux. At the moment I suspect that this is rather a problem of the > Linux driver, but I would like to make sure here first. > My ZynqMP has an eMMC flash connected to SD0 and an SD-card to SD1. When > I boot the device from SD-card and load a kernel ITB (tested both 4.14 > and 5.4), I immediately get errors when writing to the eMMC flash in > Linux: > > print_req_error: I/O error, dev mmcblk0, sector 2048 > Buffer I/O error on dev mmcblk0p1, logical block 0, lost sync page write > mmc0: Got data interrupt 0x00000002 even though no data operation was in progress. > mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== > mmc0: sdhci: Sys addr: 0x00000400 | Version: 0x00001002 > mmc0: sdhci: Blk size: 0x00007200 | Blk cnt: 0x00000400 > mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000033 > mmc0: sdhci: Present: 0x1ff70000 | Host ctl: 0x0000003d > mmc0: sdhci: Power: 0x0000000f | Blk gap: 0x00000080 > mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x00000007 > mmc0: sdhci: Timeout: 0x00000006 | Int stat: 0x00000000 > mmc0: sdhci: Int enab: 0x02ff000b | Sig enab: 0x02ff000b > mmc0: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000 > mmc0: sdhci: Caps: 0x75ecc881 | Caps_1: 0x00002007 > mmc0: sdhci: Cmd: 0x00000c1a | Max curr: 0x00000000 > mmc0: sdhci: Resp[0]: 0x00000b00 | Resp[1]: 0x36475026 > mmc0: sdhci: Resp[2]: 0x49533031 | Resp[3]: 0x00000900 > mmc0: sdhci: Host ctl2: 0x0000008b > mmc0: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000000000 > mmc0: sdhci: ============================================ > > Interestingly, I can work-around this by just typing "mmc info" in the > U-Boot console. As soon as some interaction with mmc0 happens in U-Boot > , this problem disappears (i.e. anything that relies on the mmc layer > to issue transfers to the eMMC flash). > This did not happen before, when only a 4-bit data bus was supported. > Also the latest commit e44c2bc on the Xilinx U-boot git repository does > not solve this problem. Yes we found that 1.8v dt property requires partial revert of your patch because logic in u-boot code is problematic and needs to be fixed. > From my understanding, the Linux driver should be independent of the > initialization done in U-Boot, right? > Does anyone have an idea or a comment to this? Did I miss anything? yes both should be independent. I have no idea what it is wrong in this case but definitely something to look at. Thanks, Michal

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Coreboot tests in gitlab?
by Simon Glass 12 May '20

12 May '20

Hi Bin, What do you think about having a test in gitlab etc. that boots U-Boot from coreboot using qemu? It might be handy as a sanity check. Do you think it would be hard? Regards, SImon

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[PATCH 0/8] Add dwc_eth_qos support for rockchip
by David Wu 12 May '20

12 May '20

Rockchip Socs can support two controllers "snps, dwmac-4.20a" and "snps, dwmac-3.50". In order to support two at gmac-rockchip.c, export public interface functions and struct data, it will be more general for others. David Wu (8): net: dwc_eth_qos: Use dev_ functions calls to get FDT data net: dwc_eth_qos: Fix the software reset net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32 net: dwc_eth_qos: Move interface() to eqos_ops struct net: dwc_eth_qos: Make clk_rx and clk_tx optional net: dwc_eth_qos: Split eqos_start() to get link speed net: dwc_eth_qos: Export common struct and interface at head file net: gmac_rockchip: Add dwc_eth_qos support drivers/net/Kconfig | 2 +- drivers/net/dwc_eth_qos.c | 264 +++++++++++++++++------------------- drivers/net/gmac_rockchip.c | 160 ++++++++++++++++++---- 3 files changed, 263 insertions(+), 163 deletions(-) -- 2.19.1

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[PATCH V2 0/7] imx: drivers: ddr: ddr driver update
by Peng Fan 12 May '20

12 May '20

V2: Drop patch to print dram rate remove board ddr ecc part from patch enabling inline ecc feature This is to upstream NXP vendor tree ddr driver related fix and update Jacky Bai (2): driver: ddr: imx: skip ddr_ss_gpr config on imx8mn driver: ddr: imx: correct the pwrctl setting of selfref_en on imx8m Jian Li (3): imx8mp: enable rd_port_urgent imx8mp: DDR performance tunning imx8mp: Disables use of MR4 TUF flag (MR4[7]) bit Oliver Chen (1): drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue Sherry Sun (1): drivers: ddr: imx8mp: Add inline ECC feature support arch/arm/include/asm/arch-imx8m/ddr.h | 10 ++ board/freescale/imx8mp_evk/lpddr4_timing.c | 5 +- drivers/ddr/imx/imx8m/Kconfig | 7 ++ drivers/ddr/imx/imx8m/ddr_init.c | 79 +++++++++++++- drivers/ddr/imx/imx8m/ddrphy_train.c | 7 ++ drivers/ddr/imx/imx8m/ddrphy_utils.c | 164 +++++++++++++++++++++++++++++ 6 files changed, 268 insertions(+), 4 deletions(-) -- 2.16.4

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[PATCH 0/8] imx: drivers: ddr: ddr driver update
by Peng Fan 12 May '20

12 May '20

This is to upstream NXP vendor tree ddr driver related fix and update Jacky Bai (2): driver: ddr: imx: skip ddr_ss_gpr config on imx8mn driver: ddr: imx: correct the pwrctl setting of selfref_en on imx8m Jian Li (3): imx8mp: enable rd_port_urgent imx8mp: DDR performance tunning imx8mp: Disables use of MR4 TUF flag (MR4[7]) bit Oliver Chen (1): drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue Sherry Sun (1): imx8mp: ddr: Add inline ECC feature support Ye Li (1): drivers: ddr: imx8m: add print for DRAM rate arch/arm/include/asm/arch-imx8m/ddr.h | 10 ++ board/freescale/imx8mp_evk/lpddr4_timing.c | 32 +++++- drivers/ddr/imx/imx8m/Kconfig | 7 ++ drivers/ddr/imx/imx8m/ddr_init.c | 86 ++++++++++++++- drivers/ddr/imx/imx8m/ddrphy_train.c | 7 ++ drivers/ddr/imx/imx8m/ddrphy_utils.c | 166 ++++++++++++++++++++++++++++- 6 files changed, 300 insertions(+), 8 deletions(-) -- 2.16.4

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