January 2020 - U-Boot

[PATCH v2 00/10] Add Support for eMMC boot in AM65x and J721e
by Faiz Abbas 18 Feb '20

18 Feb '20

The following patches add support for eMMC boot in TI's Am65x and J721e devices. v2: 1. Reordered the patches according to Lokesh's preference 2. Fixed patch 2 breaking platforms where DM_MMC is not enabled. Faiz Abbas (10): mmc: Add a saved_clock member mmc: Add init() API mmc: Merge SD_LEGACY and MMC_LEGACY bus modes mmc: sdhci: Expose sdhci_init() as non-static mmc: am654_sdhci: Update output tap delay writes mmc: am654_sdhci: Implement workaround for card detect spl: mmc: Fix spl_mmc_get_uboot_raw_sector() implementation arm: K3: sysfw-loader: Add a config_pm_pre_callback() configs: am65x_evm: Add CONFIG_SUPPORT_EMMC_BOOT configs: j721e_evm: Add Support for eMMC boot arch/arm/dts/k3-am65-main.dtsi | 12 ++- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 11 +- arch/arm/dts/k3-j721e-main.dtsi | 15 ++- arch/arm/mach-imx/imx8/image.c | 3 +- arch/arm/mach-k3/am6_init.c | 33 +++++- arch/arm/mach-k3/include/mach/sysfw-loader.h | 2 +- arch/arm/mach-k3/j721e_init.c | 33 +++++- arch/arm/mach-k3/sysfw-loader.c | 6 +- common/spl/spl_mmc.c | 11 +- configs/am65x_evm_a53_defconfig | 1 + configs/am65x_evm_r5_defconfig | 1 + configs/j721e_evm_a72_defconfig | 3 + configs/j721e_evm_r5_defconfig | 3 + drivers/mmc/am654_sdhci.c | 105 ++++++++++++++++--- drivers/mmc/fsl_esdhc_imx.c | 1 - drivers/mmc/mmc.c | 31 +++--- drivers/mmc/omap_hsmmc.c | 1 - drivers/mmc/sdhci.c | 2 +- drivers/mmc/zynq_sdhci.c | 1 - include/configs/am65x_evm.h | 2 - include/mmc.h | 9 +- include/sdhci.h | 1 + 22 files changed, 235 insertions(+), 52 deletions(-) -- 2.19.2

9 56

[PATCH v1] dfu: Reset timeout in case of DFU request
by Andy Shevchenko 17 Feb '20

17 Feb '20

In case dfu command is being executed with timeout option, the timer may expire in the middle of DFU operation. If there is DFU request coming, we may simple reset timeout value to prevent aborting of ongoing DFU operation. Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> --- drivers/usb/gadget/f_dfu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index 6756155133..a4a57ba5f5 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -596,6 +596,11 @@ dfu_handle(struct usb_function *f, const struct usb_ctrlrequest *ctrl) debug("req_type: 0x%x ctrl->bRequest: 0x%x f_dfu->dfu_state: 0x%x\n", req_type, ctrl->bRequest, f_dfu->dfu_state); +#ifdef CONFIG_DFU_TIMEOUT + /* Forbid aborting by timeout. Next dfu command may update this */ + dfu_set_timeout(0); +#endif + if (req_type == USB_TYPE_STANDARD) { if (ctrl->bRequest == USB_REQ_GET_DESCRIPTOR && (w_value >> 8) == DFU_DT_FUNC) { -- 2.24.1

2 3

[PATCH v6 000/102] x86: Add initial support for apollolake
by Simon Glass 17 Feb '20

17 Feb '20

Apollo Lake is an Intel SoC generation aimed at relatively low-end embedded systems. It was released in 2016 but has become more popular recently with some embedded boards using it. This series adds support for Apollo Lake. As an example it adds an implementation of chromebook_coral (a large range of Chromebooks released in 2017). The series provides enough support to boot to a prompt. with LCD display, storage, USB, EC and keyboard. Since this is the first time U-Boot has used FSP2 there is quite a bit of refactoring needed. This series is available at u-boot-dm/coral-working Changes in v6: - Add .driver_data in the designware_pci_supported array - Add a comment about VANILLA - Add a comment about the need for board_run_command() - Add a comment about why we should not use MTRR_TYPE_WRBACK - Add a comment as to why dev_read_bool() is not used - Add a comment to intel_pinctrl_ops - Add a lot of comments to get_cbfs_fsp() - Add back '#ifdef' line to commit message - Add new patch with methods to find the position/size of next SPL phase - Change comment to apl_hostbridge_early_init_pinctrl, not apl_gpio_early_init - Change commented-out enable_rtc_upper_bank() call to a TODO - Correct a few unrelated defconfig changes - Drop Glacier Lake code - Drop code to handle !CONFIG_OF_TRANSLATE case - Drop extra conditions on CONFIG_VIDEO_FSP - Drop incorrect mention of coreboot in qfw_cpu.c - Drop init of ComB since it is not used - Drop lpc_configure_pads() and probe() function, add a comment about pads - Drop mention of devicetree for VTD feature - Drop mention of ramstage - Drop platform data and pre-PCI code, since DM PCI is available in SPL - Drop unnecessary priv struct and probe method - Drop unwanted debug printf() - Drop unwanted space before comma - Drop use of GPIO_NUM_PAD_CFG_REGS - Expand commit message to mention SPL/TPL specifically - Fix 'hone' typo - Fix FSP-M and FSP-S in comments - Fix comments for struct apl_hostbridge_platdata - Fix various coding style problems - Make BOOT_FROM_FAST_SPI_FLASH a Kconfig option - Move Intel Kconfig pinctrl options into this patch - Move image pos/size access functions and symbols to generic SPL code - Move lpss_reset_release() to another commit - Move lpss_reset_release() to this commit - Move setting of CONFIG_IRQ in sandbox to this patch - Remove hyphens from Firmware-Support-Package - Remove the * in the first line of the binding file - Rename init_for_uart() to board_debug_uart_init() - Rename pci_x86_ofplat_get_devfn() to pci_ofplat_get_devfn() in comment - Split out Kconfig change to new patch to enable full pinctrl in SPL/TPL - Update comment to reference board_debug_uart_init() (its in a later patch) - Use 'No SPI' instead of 'SPI2' as a debug message - Use 'north' as the node name instead of 'n' - Use SZ_4G instead of open-coded shift - Use SZ_4G instead of open-coding the size value - Use a generic compatible string intel,gpio - Use generic gpio compatible string - Use one space after #defines in pm.h Changes in v5: - Add ACPI base address and size - Add L2 cache flush function - Add L2 cache flush functoin - Add a new patch to move qemu CPU fixup function into its own file - Add a way to obtain the port ID for a device - Add function to obtain ACPI gpio number - Add gpio-controller to GPIO nodes - Allocate the FSP-S data instead of using the stack - Change SPL as well - Comment out GPIOs in the fsp_s node since we don't use them yet - Correct CPU ACPI IDs - Correct build error in chromebook_samus_tpl - Don't enable p2sb on sandbox in this patch - Drop SAFETY_MARGIN - Drop unrelated change metioned by Heiko - Enable SMP - Fix FST typo - Fix build errors on some PowerPC boards - Group U-Boot and device tree into a section - Rename APOLLOLAKE_USB2_PORT_MAX - Rename spl section to 'spl' so that binman symbols can find it - Use a define for ACPI base address Changes in v4: - Add a LOG_CATEGORY for silicon init - Add a binding file - Add a comment about the speed logic in __dw_i2c_set_bus_speed() - Add a comment for enable_bios_reset_cpl() - Add a comment in the commit message about why has_max_speed is added - Add a patch to explain of-platdata and header files - Add an extra comment to apl_uart_init() - Add comments about MRC-cache records being the same size - Add comments for exported functions - Add comments to functions - Add more documentation for pci_ofplat_get_devfn() - Add new patch to allow designware I2C driver to work in SPL - Add new patch to drop static data in designware i2c driver - Add new patch to make mrccache_update() static - Add new patch to move early-timer init later - Add support for updating power state - Add u-boot,skip-auto-config-until-reloc property to PCI - Adjust - Adjust condition for binding children - Adjust the comment for struct dw_i2c_speed_config - Allow pinctrl nodes to have subnodes (i.e. GPIO nodes) - Avoid needing to know internals of pinctrl in this driver - Change apollolake to apl - Change the behaviour to be a device-tree option - Detect zero mmio address - Disable SPL_DM_GPIO on omap35_logic to avoid a build error - Drop 'if (0)' call to deep_magic_nexgen_probe() and use #ifndef instead - Drop GPIO_NUM_PAD_CFG_REGS - Drop TCO_BASE_ADDRESS - Drop change to message about a missing uclass - Drop duplicate VBT file CONFIG - Drop duplicate commit 'Create a new sandbox_pci_read_bar() function' - Drop empty operations struct since p2sb does not need it - Drop incorrect coreboot reference from header file - Drop itss uclass change in Makefile (now in previous patch) - Drop itss uclass in Makefile - Drop pmic_pm8916 driver name and use a sandbox name instead - Drop sandbox defconfig change now that p2sb change is correct - Drop the whole interrupt file for TPL - Drop unwanted debug printf("bad\n") - Enable HAVE_VBT for FSP2 also - Enable HAVE_X86_FIT - Enable INTEL_GPIO - Enable IRQ for sandbox64 too to avoid build error - Enable option for slimbootloader, coreboot, efi - Expand commit message to better explain the need to checksum functions - Explain the 'twisty headers' comment - Explain why FSP-M cannot be shown - Fix 'enabled' typo - Fix 'what' typo - Fix FSP_M reference to refer to FSP_S in commit message - Fix Makefile copyright message - Fix alpha order in Kconfig - Fix comment for exec_sync_hwseq_xfer() - Fix comment on fsp_silicon_init() - Fix incorrect mask check in pmc_gpe_init() - Fix indentation nit - Fix up license header - Fix various code-style problems - Mention that the return value is pci_dev_t - Move code to pinctrl driver - Move this to intel_common - Name this P-Unit instead of power unit, in the commit message - New GPIO driver binding - One last desperate attempt to try to explain the purpose of this commit - Rename arch_fsp_s_preinit() to arch_fsps_preinit() - Rename get_coreboot_fsp() and add comments - Rename new file to designware_i2c_pci.c - Rename option to HAVE_SYS_TEXT_BASE - Rename pci_x86_ofplat_get_devfn() to pci_ofplat_get_devfn() - Reverse the sense of the CONFIG option - Set up LPC pads early - Split out GPIO code from the pinctrl driver - Split out into a separate patch - Split out mmio changes into a separate patch - Switch over to use pinctrl for pad init/config - Tidy up header guards - Tidy up mixed case in FSP code - Tidy up the header file a little - Update SPI flash protection only in SPL - Update commit message to indicate that CPU-identity bug is fixed - Update documentation with more detailed memory map - Update the commit message to be clearer, fix 'correct' typo - Update the message to mention the preprocessed file, not un-preprocessed - Use 'Apollo Lake' - Use BIT() macro a bit more - Use BIT() macro bit more - Use CONFIG_INTEL_CAR_CQOS to control car2.S inclusion - Use car_init_ret to return - Use existing VBT Kconfig option - Use hex for size values also - Use hyphen for device-tree properties - Use lower-case pinctrl in arch_cpu_init_dm() - Use pci_ofplat_get_devfn() - Use post_code() calls consistent with car.S - Use priv->pch instead of dev->parent - Use tabs instead of spaces - Use the new pci_ofplat_get_devfn() function - apollolake -> Apollo Lake - use GENMASK() for VTBAR_MASK Changes in v3: - Ad FSP-S support - Add CONFIG_TPL_X86_ASSUME_CPUID to reduce code size - Add Chrome OS EC support - Add FSP-S and VBT also - Add MMC, video, USB configs - Add SPL condition to the option - Add VBT signature - Add a driver for APL SPI for TPL (using of-platdata) - Add a proper SPI node and make the SPI flash node a child - Add a proper implementation of fsp_notify - Add a weak function to avoid errors on other platforms - Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot - Add an extra size parameter to the find_next_mrc_cache() function - Add an fsp: tag - Add bootstage support - Add bootstage timing for memory-mapped reads - Add bootstage timing for reading vbt - Add fsp_locate_fsp to locate an fsp component - Add fspm_done() hook - Add fspm_done() hook to handle FSP-S wierdness (it breaks SPI flash) - Add help to CONFIG_FIT and don't make it 'default y' - Add more documentation - Add snapshot/restore for IRQs - Add spi alias in device tree - Add structures for FSP-S also - Add support for FSP-S component and VBT - Add support for of-platdata for TPL - Add the missing header file - Add two more defines for the CPU driver - Add two more operations to IRQ - Add various minor tidy-ups - Adjust fast_spi_cache_bios_region() to avoid using SPI driver - Change Fast-SPI driver into a helper file used by ICH SPI - Change the sandbox test from ITSS to IRQ - Convert code to use hex increased of decimal - Disable the bootcommand since it does nothing useful on coral - Don't allow BOOT_FROM_FAST_SPI_FLASH with FSP-S - Don't enable SPI flash in TPL by default - Don't imply SPI flash either - Don't include write() and erase() in TPL - Drop 'a4' comment for register offset - Drop CONFIG_SPL_NET_SUPPORT - Drop VBT as we already have it elsewhere - Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f() - Drop dead code - Drop patch '86: timer: Reduce timer code size in TPL on Intel CPUs' - Drop patch 'dm: core: Don't include ofnode functions with of-platdata' - Drop patch 'spi: sandbox: Add a test driver for sandbox SPI flash' - Drop patch 'spl: Allow SPL/TPL to use of-platdata without libfdt' - Drop patch 'x86: apollolake: Add definitions for the Intel Fast SPI interface' - Drop patch 'x86: timer: Set up the timer in timer_early_get_count()' - Drop struct fsp_usp_header as it is now in the API file - Drop unnecessary #else part of CONFIG_HAVE_MICROCODE - Drop unneeded Kconfig file - Drop unused code in lpc_configure_pads() - Enable video and USB3 - Expand comments for BOOT_FROM_FAST_SPI_FLASH - Fix build error when debug UART is disabled - Fix build errors in sandbox_spl, etc - Fix mixed case in GPIO defines - Fix the incorrect value of CPU_ADDR_BITS - Fix value of LPC_BC_LE - Init the p2sb before the northbridge since the latter so it can use GPIOs - Merge in patch "x86: Add support for booting from Fast SPI" - Move an additional error handling fix from a future patch - Move line related to variable-cache into the next patch - Move location of fast_spi.h header file - Move mtrr_add_request() call into this patch - Move mtrr_add_request() call to next patch - Move pad programming into the hostbridge to reduce TPL device-tree size - Move the function to a common file instead of duplicating it - Move the mrccache_get_region() change into this patch - Move write_pirq_routing_table() to avoid 64-bit build error - Only supress the 'MAC address from ROM' warning on sandbox - Reduce amount of early-pad data in TPL - Rename X86_HAS_FIT to HAVE_X86_FIT - Rename power-mgr uclass to acpi-pmc - Reorder file so that write() and erase() are together - Rework how pads configuration is defined in TPL and SPL - Rewrite commit message - Set boot_loader_tolum_size to 0 - Set the environment variables at runtime to avoid other warnings - Shorten log_msg_ret() calls since the function name is always printed - Simplify types for fsp_locate_fsp() - Support TPL without CONFIG_TPL_SPI_SUPPORT - Support TPL without CONFIG_TPL_SPI_SUPPORT (reduces code size) - Support bootstage timing - Switch mmap to use SPI instead of SPI flash - Tidy up Makefile rules to reduce duplication - Tidy up the pad settings in the device tree - Update commit message to explain why HAVE_FIT woudl be confusing - Update device type to pci_dev_t - Update example error message to better show the intended purpose - Update mrccache livetree patch to just convert to livetree - Update the 'fsp' command for FSP2, instead of disabling it - Use a macro for is-power-of-two - Use a zero-based tsc timer - Use pci_get_devfn() - Use the IRQ uclass instead of ITSS - Use the IRQ uclass instead of creating a new ITSS uclass - Use the LPSS code from a separate file Changes in v2: - Change 'queensbay' to 'baytrail' in help - Drop probe() function - Fix 'proides' typo - Fix the Kconfig condition to avoid build errors on snow - Implement set_spi_protect() - Use SPI mmap() instead of SPI flash Simon Glass (102): binman: Add a library to access binman entries dm: gpio: Allow control of GPIO uclass in SPL dm: core: Fix offset_to_ofnode() with invalid offset dm: pci: Allow delaying auto-config until after relocation dm: pci: Move pci_get_devfn() into a common file net: Move the checksum functions to lib/ i2c: designware: Tidy up PCI support i2c: designware: Avoid using static data i2c: designware: Support use in SPL x86: spi: Add helper functions for Intel Fast SPI fdt: Show the preprocessed .dts file on error dm: pinctrl: Allow enabling full pinctrl in SPL/TPL board_r: Move early-timer init later RFC: sandbox: net: Suppress the MAC-address warnings Revert "RFC: sandbox: net: Suppress the MAC-address warnings" x86: timer: use a timer base of 0 x86: timer: Reduce timer code size in TPL on Intel CPUs x86: Drop unnecessary cpu code for TPL x86: Drop unnecessary interrupt code for TPL x86: power: Add an ACPI PMC uclass x86: sandbox: Add a PMC emulator and test pci: Add support for p2sb uclass sandbox: Disable mmio by default in tests sandbox: Add PCI driver and test for p2sb x86: Move UCLASS_IRQ into a separate file sandbox: Add a test for IRQ x86: Define the SPL image start x86: Reduce mrccache record alignment size x86: Correct mrccache find_next_mrc_cache() calculation x86: Adjust mrccache_get_region() to use livetree x86: Adjust mrccache_get_region() to support get_mmap() x86: Add a new global_data member for the cache record x86: Tidy up error handling in mrccache_save() x86: Update mrccache to support multiple caches x86: Add mrccache support for a 'variable' cache x86: Don't export mrccache_update() x86: Move fsp_prepare_mrc_cache() to fsp1 directory x86: Set the DRAM banks to reflect real location x86: Set up the MTRR for SDRAM x86: Don't imply libfdt or SPI flash in TPL x86: Allow removal of standard PCH drivers x86: Allow interrupt to happen once x86: fsp: Make graphics support common to FSP1/2 x86: fsp: Correct wrong header inlude in fsp_support.c x86: fsp: Add FSP2 base support x86: fsp: Set up an MTRR for the graphics frame buffer x86: fsp: Add a new arch_fsp_init_r() hook x86: fsp: Allow remembering the location of FSP-S x86: fsp: Make the notify API call common x86: Don't include the BIOS emulator in TPL x86: Add an option to include a FIT x86: Add support for newer CAR schemes x86: Disable microcode section for FSP2 x86: Update the fsp command for FSP2 x86: Update .dtsi file for FSP2 x86: Add an option to control the position of U-Boot x86: Add an option to control the position of SPL x86: Add an fdtmap and image-header x86: Don't repeat microcode in U-Boot if not needed x86: Separate out U-Boot and device tree in ROM image x86: Make MSR_PKG_POWER_SKU common spi: Correct operations check in dm_spi_xfer() x86: spi: Don't enable SPI_FLASH_BAR by default spi: ich: Move init function just above probe() spi: ich: Move the protection/lockdown code into a function spi: ich: Convert to livetree spi: ich: Fix header order spi: ich: Various small tidy-ups spi: ich: Add mmio_base to struct ich_spi_platdata dm: doc: Add a note about of-platdata and header files spi: ich: Correct max-size bug in ich_spi_adjust_size() spi: ich: Support of-platdata for fast-spi spi: ich: Support hardware sequencing spi: ich: Add support for get_mmap() method spi: ich: Add TPL support spi: ich: Add Apollo Lake support mtd: spi: Export spi_flash_std_probe() x86: Enable pinctrl in SPL and TPL x86: Add low-power subsystem (lpss) support x86: Add a generic Intel pinctrl driver x86: Add a generic Intel GPIO driver x86: Move qemu CPU fixup function into its own file x86: apl: Add basic IO addresses x86: apl: Add PMC driver x86: apl: Add UART driver x86: apl: Add pinctrl driver i2c: designware: Add Apollo Lake support x86: apl: Add systemagent driver x86: apl: Add hostbridge driver x86: apl: Add ITSS driver x86: apl: Add LPC driver x86: apl: Add PCH driver x86: apl: Add PUNIT driver spl: Add methods to find the position/size of next phase x86: apl: Add SPL loaders x86: apl: Add a CPU driver x86: apl: Add SPL/TPL init x86: apl: Add P2SB driver x86: apl: Add Kconfig and Makefile x86: apl: Add FSP structures x86: apl: Add FSP support x86: Add chromebook_coral Kconfig | 9 +- arch/Kconfig | 9 +- arch/arm/include/asm/omap_gpio.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9260.h | 2 +- arch/arm/mach-davinci/include/mach/gpio.h | 2 +- arch/arm/mach-omap2/am33xx/board.c | 4 +- arch/arm/mach-omap2/omap3/board.c | 2 +- arch/arm/mach-omap2/omap5/hwinit.c | 2 +- arch/sandbox/cpu/state.c | 1 + arch/sandbox/dts/sandbox.dtsi | 14 + arch/sandbox/dts/test.dts | 31 + arch/sandbox/include/asm/test.h | 2 + arch/x86/Kconfig | 91 +- arch/x86/cpu/Makefile | 4 +- arch/x86/cpu/apollolake/Kconfig | 96 ++ arch/x86/cpu/apollolake/Makefile | 27 + arch/x86/cpu/apollolake/cpu.c | 41 + arch/x86/cpu/apollolake/cpu_common.c | 17 + arch/x86/cpu/apollolake/cpu_spl.c | 271 ++++++ arch/x86/cpu/apollolake/fsp_m.c | 210 +++++ arch/x86/cpu/apollolake/fsp_s.c | 661 ++++++++++++++ arch/x86/cpu/apollolake/hostbridge.c | 179 ++++ arch/x86/cpu/apollolake/itss.c | 214 +++++ arch/x86/cpu/apollolake/lpc.c | 122 +++ arch/x86/cpu/apollolake/p2sb.c | 167 ++++ arch/x86/cpu/apollolake/pch.c | 36 + arch/x86/cpu/apollolake/pmc.c | 216 +++++ arch/x86/cpu/apollolake/punit.c | 94 ++ arch/x86/cpu/apollolake/spl.c | 178 ++++ arch/x86/cpu/apollolake/systemagent.c | 19 + arch/x86/cpu/apollolake/uart.c | 133 +++ arch/x86/cpu/broadwell/sdram.c | 8 +- arch/x86/cpu/coreboot/Kconfig | 1 + arch/x86/cpu/cpu.c | 4 + arch/x86/cpu/i386/Makefile | 2 + arch/x86/cpu/i386/cpu.c | 41 +- arch/x86/cpu/intel_common/Makefile | 10 + arch/x86/cpu/intel_common/car2.S | 448 ++++++++++ arch/x86/cpu/intel_common/car2_uninit.S | 87 ++ arch/x86/cpu/intel_common/fast_spi.c | 73 ++ arch/x86/cpu/intel_common/lpss.c | 44 + arch/x86/cpu/irq.c | 13 - arch/x86/cpu/ivybridge/sdram.c | 8 +- arch/x86/cpu/mp_init.c | 73 +- arch/x86/cpu/qfw_cpu.c | 73 ++ arch/x86/cpu/quark/dram.c | 8 +- arch/x86/cpu/slimbootloader/Kconfig | 1 + arch/x86/cpu/u-boot-spl.lds | 5 +- arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_coral.dts | 831 ++++++++++++++++++ arch/x86/dts/u-boot.dtsi | 91 +- arch/x86/include/asm/arch-apollolake/cpu.h | 20 + .../asm/arch-apollolake/fsp/fsp_configs.h | 14 + .../asm/arch-apollolake/fsp/fsp_m_upd.h | 123 +++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 292 ++++++ .../include/asm/arch-apollolake/fsp/fsp_vpd.h | 11 + arch/x86/include/asm/arch-apollolake/gpio.h | 490 +++++++++++ arch/x86/include/asm/arch-apollolake/iomap.h | 29 + arch/x86/include/asm/arch-apollolake/itss.h | 43 + arch/x86/include/asm/arch-apollolake/lpc.h | 82 ++ arch/x86/include/asm/arch-apollolake/pch.h | 9 + arch/x86/include/asm/arch-apollolake/pm.h | 19 + .../include/asm/arch-apollolake/systemagent.h | 37 + arch/x86/include/asm/arch-apollolake/uart.h | 20 + arch/x86/include/asm/arch-broadwell/cpu.h | 1 - .../include/asm/arch-ivybridge/model_206ax.h | 1 - arch/x86/include/asm/fast_spi.h | 68 ++ arch/x86/include/asm/fsp/fsp_api.h | 24 + arch/x86/include/asm/fsp/fsp_support.h | 7 - arch/x86/include/asm/fsp1/fsp_api.h | 21 +- arch/x86/include/asm/fsp2/fsp_api.h | 63 ++ arch/x86/include/asm/fsp2/fsp_internal.h | 97 ++ arch/x86/include/asm/global_data.h | 25 +- arch/x86/include/asm/intel_pinctrl.h | 306 +++++++ arch/x86/include/asm/intel_pinctrl_defs.h | 373 ++++++++ arch/x86/include/asm/lpss.h | 36 + arch/x86/include/asm/mrccache.h | 29 +- arch/x86/include/asm/msr-index.h | 10 +- arch/x86/include/asm/processor.h | 12 +- arch/x86/include/asm/spl.h | 1 + arch/x86/lib/Makefile | 2 + arch/x86/lib/fsp/Makefile | 3 + arch/x86/lib/fsp/fsp_common.c | 20 - arch/x86/lib/fsp/fsp_dram.c | 35 +- arch/x86/lib/{fsp1 => fsp}/fsp_graphics.c | 6 +- arch/x86/lib/fsp/fsp_support.c | 2 +- arch/x86/lib/fsp1/Makefile | 1 - arch/x86/lib/fsp1/fsp_common.c | 20 + arch/x86/lib/fsp1/fsp_dram.c | 8 +- arch/x86/lib/fsp2/Makefile | 10 + arch/x86/lib/fsp2/fsp_common.c | 13 + arch/x86/lib/fsp2/fsp_dram.c | 78 ++ arch/x86/lib/fsp2/fsp_init.c | 191 ++++ arch/x86/lib/fsp2/fsp_meminit.c | 97 ++ arch/x86/lib/fsp2/fsp_silicon_init.c | 54 ++ arch/x86/lib/fsp2/fsp_support.c | 131 +++ arch/x86/lib/mrccache.c | 204 +++-- arch/x86/lib/pirq_routing.c | 10 + board/freescale/imx8qm_mek/imx8qm_mek.c | 2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- board/gateworks/gw_ventana/Kconfig | 3 + board/google/Kconfig | 15 + board/google/chromebook_coral/Kconfig | 43 + board/google/chromebook_coral/MAINTAINERS | 6 + board/google/chromebook_coral/Makefile | 5 + board/google/chromebook_coral/coral.c | 19 + board/toradex/apalis-imx8/apalis-imx8.c | 2 +- cmd/Kconfig | 8 + cmd/Makefile | 1 + cmd/pmc.c | 81 ++ cmd/x86/fsp.c | 65 +- common/board_r.c | 32 +- common/spl/spl.c | 20 + configs/chromebook_coral_defconfig | 102 +++ configs/chromebook_samus_tpl_defconfig | 3 + configs/omap35_logic_defconfig | 1 + configs/qemu-x86_64_defconfig | 1 + configs/sandbox64_defconfig | 4 + configs/sandbox_defconfig | 2 + configs/sandbox_flattree_defconfig | 4 + configs/sandbox_spl_defconfig | 4 + configs/tools-only_defconfig | 2 + doc/board/google/chromebook_coral.rst | 241 +++++ .../gpio/intel,apl-gpio.txt | 55 ++ doc/device-tree-bindings/pci/x86-pci.txt | 24 + .../pinctrl/intel,apl-pinctrl.txt | 39 + doc/driver-model/of-plat.rst | 6 + drivers/Makefile | 1 + drivers/core/util.c | 20 + drivers/gpio/Kconfig | 31 + drivers/gpio/Makefile | 5 +- drivers/gpio/at91_gpio.c | 6 +- drivers/gpio/atmel_pio4.c | 2 +- drivers/gpio/da8xx_gpio.c | 7 +- drivers/gpio/da8xx_gpio.h | 2 +- drivers/gpio/intel_gpio.c | 161 ++++ drivers/gpio/mxc_gpio.c | 4 +- drivers/gpio/mxs_gpio.c | 4 +- drivers/gpio/omap_gpio.c | 6 +- drivers/gpio/sunxi_gpio.c | 8 +- drivers/i2c/Makefile | 3 + drivers/i2c/designware_i2c.c | 106 +-- drivers/i2c/designware_i2c.h | 35 + drivers/i2c/designware_i2c_pci.c | 144 +++ drivers/i2c/i2c-uclass.c | 6 +- drivers/i2c/muxes/pca954x.c | 4 +- drivers/misc/Kconfig | 42 + drivers/misc/Makefile | 5 + drivers/misc/irq-uclass.c | 53 ++ drivers/misc/irq_sandbox.c | 55 ++ drivers/misc/p2sb-uclass.c | 216 +++++ drivers/misc/p2sb_emul.c | 272 ++++++ drivers/misc/p2sb_sandbox.c | 39 + drivers/misc/sandbox_adder.c | 60 ++ drivers/mmc/fsl_esdhc_imx.c | 13 +- drivers/mmc/omap_hsmmc.c | 2 +- drivers/mtd/spi/sf_probe.c | 2 +- drivers/net/designware.c | 10 +- drivers/net/designware.h | 4 +- drivers/net/fec_mxc.c | 6 +- drivers/net/fec_mxc.h | 2 +- drivers/net/mvneta.c | 4 +- drivers/net/mvpp2.c | 8 +- drivers/net/sun8i_emac.c | 12 +- drivers/pch/Kconfig | 18 + drivers/pch/Makefile | 4 +- drivers/pci/pci-aardvark.c | 4 +- drivers/pci/pci-uclass.c | 31 +- drivers/pci/pcie_dw_mvebu.c | 4 +- drivers/pinctrl/Kconfig | 23 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/intel/Kconfig | 24 + drivers/pinctrl/intel/Makefile | 6 + drivers/pinctrl/intel/pinctrl.c | 636 ++++++++++++++ drivers/pinctrl/intel/pinctrl_apl.c | 192 ++++ drivers/power/Kconfig | 2 + drivers/power/acpi_pmc/Kconfig | 34 + drivers/power/acpi_pmc/Makefile | 6 + drivers/power/acpi_pmc/acpi-pmc-uclass.c | 244 +++++ drivers/power/acpi_pmc/pmc_emul.c | 246 ++++++ drivers/power/acpi_pmc/sandbox.c | 97 ++ drivers/spi/Kconfig | 1 - drivers/spi/atmel_spi.c | 10 +- drivers/spi/designware_spi.c | 4 +- drivers/spi/ich.c | 534 ++++++++--- drivers/spi/ich.h | 46 +- drivers/spi/spi-uclass.c | 5 +- drivers/timer/Kconfig | 23 + drivers/timer/tsc_timer.c | 10 +- drivers/tpm/tpm2_tis_spi.c | 2 +- include/binman.h | 45 + include/bootstage.h | 3 + include/config_uncmd_spl.h | 1 - include/configs/at91-sama5_common.h | 5 +- include/configs/chromebook_coral.h | 32 + include/configs/gw_ventana.h | 1 - include/configs/mx6ul_14x14_evk.h | 1 + include/dm/ofnode.h | 2 +- include/dm/pci.h | 43 + include/dm/uclass-id.h | 2 + include/init.h | 11 + include/irq.h | 88 ++ include/p2sb.h | 135 +++ include/pci.h | 21 +- include/power/acpi_pmc.h | 185 ++++ include/qfw.h | 8 + include/spi.h | 2 +- include/spi_flash.h | 12 + include/spl.h | 21 +- lib/Kconfig | 10 + lib/Makefile | 3 +- lib/binman.c | 48 + lib/efi/Kconfig | 1 + lib/net_utils.c | 48 + net/Makefile | 1 - net/checksum.c | 59 -- scripts/Makefile.lib | 4 +- scripts/Makefile.uncmd_spl | 1 - test/dm/Makefile | 3 + test/dm/irq.c | 32 + test/dm/p2sb.c | 28 + test/dm/pmc.c | 33 + 222 files changed, 12368 insertions(+), 706 deletions(-) create mode 100644 arch/x86/cpu/apollolake/Kconfig create mode 100644 arch/x86/cpu/apollolake/Makefile create mode 100644 arch/x86/cpu/apollolake/cpu.c create mode 100644 arch/x86/cpu/apollolake/cpu_common.c create mode 100644 arch/x86/cpu/apollolake/cpu_spl.c create mode 100644 arch/x86/cpu/apollolake/fsp_m.c create mode 100644 arch/x86/cpu/apollolake/fsp_s.c create mode 100644 arch/x86/cpu/apollolake/hostbridge.c create mode 100644 arch/x86/cpu/apollolake/itss.c create mode 100644 arch/x86/cpu/apollolake/lpc.c create mode 100644 arch/x86/cpu/apollolake/p2sb.c create mode 100644 arch/x86/cpu/apollolake/pch.c create mode 100644 arch/x86/cpu/apollolake/pmc.c create mode 100644 arch/x86/cpu/apollolake/punit.c create mode 100644 arch/x86/cpu/apollolake/spl.c create mode 100644 arch/x86/cpu/apollolake/systemagent.c create mode 100644 arch/x86/cpu/apollolake/uart.c create mode 100644 arch/x86/cpu/intel_common/car2.S create mode 100644 arch/x86/cpu/intel_common/car2_uninit.S create mode 100644 arch/x86/cpu/intel_common/fast_spi.c create mode 100644 arch/x86/cpu/intel_common/lpss.c create mode 100644 arch/x86/cpu/qfw_cpu.c create mode 100644 arch/x86/dts/chromebook_coral.dts create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h create mode 100644 arch/x86/include/asm/arch-apollolake/iomap.h create mode 100644 arch/x86/include/asm/arch-apollolake/itss.h create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h create mode 100644 arch/x86/include/asm/arch-apollolake/pch.h create mode 100644 arch/x86/include/asm/arch-apollolake/pm.h create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h create mode 100644 arch/x86/include/asm/arch-apollolake/uart.h create mode 100644 arch/x86/include/asm/fast_spi.h create mode 100644 arch/x86/include/asm/fsp/fsp_api.h create mode 100644 arch/x86/include/asm/fsp2/fsp_api.h create mode 100644 arch/x86/include/asm/fsp2/fsp_internal.h create mode 100644 arch/x86/include/asm/intel_pinctrl.h create mode 100644 arch/x86/include/asm/intel_pinctrl_defs.h create mode 100644 arch/x86/include/asm/lpss.h rename arch/x86/lib/{fsp1 => fsp}/fsp_graphics.c (95%) create mode 100644 arch/x86/lib/fsp2/Makefile create mode 100644 arch/x86/lib/fsp2/fsp_common.c create mode 100644 arch/x86/lib/fsp2/fsp_dram.c create mode 100644 arch/x86/lib/fsp2/fsp_init.c create mode 100644 arch/x86/lib/fsp2/fsp_meminit.c create mode 100644 arch/x86/lib/fsp2/fsp_silicon_init.c create mode 100644 arch/x86/lib/fsp2/fsp_support.c create mode 100644 board/google/chromebook_coral/Kconfig create mode 100644 board/google/chromebook_coral/MAINTAINERS create mode 100644 board/google/chromebook_coral/Makefile create mode 100644 board/google/chromebook_coral/coral.c create mode 100644 cmd/pmc.c create mode 100644 configs/chromebook_coral_defconfig create mode 100644 doc/board/google/chromebook_coral.rst create mode 100644 doc/device-tree-bindings/gpio/intel,apl-gpio.txt create mode 100644 doc/device-tree-bindings/pci/x86-pci.txt create mode 100644 doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt create mode 100644 drivers/gpio/intel_gpio.c create mode 100644 drivers/i2c/designware_i2c_pci.c create mode 100644 drivers/misc/irq-uclass.c create mode 100644 drivers/misc/irq_sandbox.c create mode 100644 drivers/misc/p2sb-uclass.c create mode 100644 drivers/misc/p2sb_emul.c create mode 100644 drivers/misc/p2sb_sandbox.c create mode 100644 drivers/misc/sandbox_adder.c create mode 100644 drivers/pinctrl/intel/Kconfig create mode 100644 drivers/pinctrl/intel/Makefile create mode 100644 drivers/pinctrl/intel/pinctrl.c create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c create mode 100644 drivers/power/acpi_pmc/Kconfig create mode 100644 drivers/power/acpi_pmc/Makefile create mode 100644 drivers/power/acpi_pmc/acpi-pmc-uclass.c create mode 100644 drivers/power/acpi_pmc/pmc_emul.c create mode 100644 drivers/power/acpi_pmc/sandbox.c create mode 100644 include/binman.h create mode 100644 include/configs/chromebook_coral.h create mode 100644 include/dm/pci.h create mode 100644 include/irq.h create mode 100644 include/p2sb.h create mode 100644 include/power/acpi_pmc.h create mode 100644 lib/binman.c delete mode 100644 net/checksum.c create mode 100644 test/dm/irq.c create mode 100644 test/dm/p2sb.c create mode 100644 test/dm/pmc.c -- 2.24.0.393.g34dc348eaf-goog

6 234

[U-Boot] [RFC] cmd: add bootslot command to select/boot slot based on boot counts
by Martin Hundebøll 16 Feb '20

16 Feb '20

The existing bootcount feature is targeted systems with a primary, and a rescue boot setup, where the number of boot tries to the primary boot is tracked. If the number exceeds the limit, the alternative/rescue is booted. This patch adds support for a more sophisticated setup, where more than two boot slots can exist, and the order of slots can be configured. The 'bootcommand' command reads the configured slots (and their priority/order) from a configured environment variable ("bootslots" by default). For each conifgured slot, a remaining boot count is maintained in an evnironment variable ("bootcount_<slot>" by default). If the first boot slot has positive boot count, it is booted using the slot specific boot command ("bootcmd_<slot>" by default). Otherwise the next slot is checked. An example environment when using the bootslot command with two slots ("a" and "b"): bootslots=a b bootcount_a=3 bootcount_b=3 bootcmd_a=setenv bootargs $bootargs root=/dev/mmcblk0p1; booti $loadaddr bootcmd_b=setenv bootargs $bootargs root=/dev/mmcblk0p2; booti $loadaddr Once linux is booted, it resets the bootcount variable for the booted slot using "fw_setenv": > fw_setenv bootcount_a 3 When the non-booted slot is updated, the order is updated by setting the bootslots variable with "fw_setenv": > fw_setenv bootslots=b a Signed-off-by: Martin Hundebøll <martin(a)geanix.com> --- cmd/Kconfig | 42 +++++++++ cmd/Makefile | 1 + cmd/bootslot.c | 225 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 268 insertions(+) create mode 100644 cmd/bootslot.c diff --git a/cmd/Kconfig b/cmd/Kconfig index aec209006d..3919606e74 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1277,6 +1277,48 @@ config CMD_BOOTCOUNT Enable the bootcount command, which allows interrogation and reset of the bootcounter. +config CMD_BOOTSLOT + bool "Enable support for multiple boot slots" + help + Parses an ordered list of configured boot slot names (e.g. "a b") + and selects a corresponding boot command based on the current + boot counter for each slot. + +config CMD_BOOTSLOT_ENV_SLOTS + string "Environment variable to read bootslots from" + depends on CMD_BOOTSLOT + default "bootslots" + help + Configures the environment variable to read out when looking for a + list of available boot sloots. + +config CMD_BOOTSLOT_ENV_COUNT + string "Environment variable format string to read/write slot boot count from/to" + depends on CMD_BOOTSLOT + default "bootcount_%s" + help + Configures the prefix to use when reading the boot count for a + specific slot. The prefix is concatenated with the slot name, so + that the boot count for slot "a" is read and saved to "<prefix>a". + +config CMD_BOOTSLOT_ENV_CMD + string "Environment variable format string to read slot boot command from" + depends on CMD_BOOTSLOT + default "bootcmd_%s" + help + Configures the prefix to use when reading the boot command for + specific slot. The prefix is concatenated with the slot name, so + that the boot command for slot "a" is read from "<prefix>a". + +config CMD_BOOTSLOT_DEFAULT_COUNT + int "Default boot count for each configured slot" + depends on CMD_BOOTSLOT + default 3 + help + The default number of times a slot is tried before proceeding to the + slot. The default is used when a slot has no count yet, or when it + is reset with the "bootslot reset" command. + config CMD_BSP bool "Enable board-specific commands" help diff --git a/cmd/Makefile b/cmd/Makefile index 323f1fd2c7..68c8e50c91 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_CMD_BOOTCOUNT) += bootcount.o obj-$(CONFIG_CMD_BOOTEFI) += bootefi.o obj-$(CONFIG_CMD_BOOTMENU) += bootmenu.o obj-$(CONFIG_CMD_BOOTSTAGE) += bootstage.o +obj-$(CONFIG_CMD_BOOTSLOT) += bootslot.o obj-$(CONFIG_CMD_BOOTZ) += bootz.o obj-$(CONFIG_CMD_BOOTI) += booti.o obj-$(CONFIG_CMD_BTRFS) += btrfs.o diff --git a/cmd/bootslot.c b/cmd/bootslot.c new file mode 100644 index 0000000000..03897b1f60 --- /dev/null +++ b/cmd/bootslot.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2018, Geanix, All rights reserved. + */ + +#include <common.h> +#include <environment.h> +#include <stdlib.h> +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/compat.h> +#include <vsprintf.h> + +static char *bootslot_envname(const char *fmt, const char *slot) +{ + int len = strlen(fmt) + strlen(slot); + char *envname = malloc(len + 1); + + sprintf(envname, fmt, slot); + + return envname; +} + +static unsigned long bootslot_get_count(const char *slot) +{ + char *envname; + unsigned long count; + + envname = bootslot_envname(CONFIG_CMD_BOOTSLOT_ENV_COUNT, slot); + count = env_get_ulong(envname, 10, CONFIG_CMD_BOOTSLOT_DEFAULT_COUNT); + free(envname); + + return count; +} + +static void bootslot_set_count(const char *slot, unsigned long count) +{ + char *envname; + + envname = bootslot_envname(CONFIG_CMD_BOOTSLOT_ENV_COUNT, slot); + env_set_ulong(envname, count); + free(envname); +} + +static const char *bootslot_get_cmd(const char *slot) +{ + char *envname; + char *cmd; + + envname = bootslot_envname(CONFIG_CMD_BOOTSLOT_ENV_CMD, slot); + cmd = env_get(envname); + free(envname); + + return cmd; +} + +static char *bootslot_get_slots(int argc, char * const argv[]) +{ + char *slots = NULL; + int len = 1; /* make room for terminating \0 */ + int i; + + /* read boot slots from environment if no args are given, or + * duplicate the argument if a single argument is given */ + if (argc == 1) + return strdup(env_get(CONFIG_CMD_BOOTSLOT_ENV_SLOTS)); + else if (argc == 2) + return strdup(argv[1]); + + /* compute the string length of the list of slots */ + for (i = 1; i < argc; i++) + len += strlen(argv[i]) + 1; /* add room for space separator */ + + /* allocate the string buffer and copy each slot argument to it */ + slots = kzalloc(len, 0); + strcpy(slots, argv[1]); + + for (i = 2; i < argc; i++) { + strcat(slots, " "); + strcat(slots, argv[i]); + } + + return slots; +} + +static int do_bootslot_list(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + char *mem = bootslot_get_slots(argc, argv); + char *slots = mem; + char *slot; + + if (slots == NULL) + return CMD_RET_USAGE; + + printf("slot\tcount\tbootcmd\n"); + while ((slot = strsep(&slots, " ")) != NULL) { + unsigned long count; + const char *bootcmd; + + if (strlen(slot) == 0) + continue; + + count = bootslot_get_count(slot); + bootcmd = bootslot_get_cmd(slot); + + if (bootcmd) + printf("%s\t%lu\t%s\n", slot, count, bootcmd); + else + printf("%s\t%lu\t<not defined>\n", slot, count); + } + + free(mem); + + return CMD_RET_SUCCESS; +} + +static int do_bootslot_reset(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + char *mem = bootslot_get_slots(argc, argv); + char *slots = mem; + char *slot; + + if (slots == NULL) + return CMD_RET_USAGE; + + while ((slot = strsep(&slots, " ")) != NULL) { + if (strlen(slot) == 0) + continue; + bootslot_set_count(slot, CONFIG_CMD_BOOTSLOT_DEFAULT_COUNT); + } + + free(mem); + + return CMD_RET_SUCCESS; +} + +static int do_bootslot_boot(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + char *mem = bootslot_get_slots(argc, argv); + char *slots = mem; + char *slot; + bool found_valid = false; + + if (slots == NULL) + return CMD_RET_USAGE; + + while ((slot = strsep(&slots, " ")) != NULL) { + const char *bootcmd; + unsigned long count; + + if (strlen(slot) == 0) + continue; + + count = bootslot_get_count(slot); + if (count == 0) { + printf("slot %s bootcount is zero; trying next...\n", + slot); + continue; + } + + bootcmd = bootslot_get_cmd(slot); + if (bootcmd == NULL) { + printf("slot %s bootcmd not found; trying next...\n", + slot); + continue; + } + + printf("slot %s has %lu boot tries remaining; booting...\n", + slot, count); + found_valid = true; + bootslot_set_count(slot, --count); + env_save(); + run_command_list(bootcmd, -1, CMD_FLAG_ENV); + break; + } + + free(mem); + + if (found_valid == false) { + printf("no valid bootslot found; resetting counters\n"); + run_command("bootslot reset", 0); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +static cmd_tbl_t cmd_bootslot_sub[] = { + U_BOOT_CMD_MKENT(boot, INT_MAX, 0, do_bootslot_boot, "", ""), + U_BOOT_CMD_MKENT(list, INT_MAX, 1, do_bootslot_list, "", ""), + U_BOOT_CMD_MKENT(reset, INT_MAX, 1, do_bootslot_reset, "", ""), +}; + +/* + * Process a bootslots sub-command + */ +static int do_bootslot(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + cmd_tbl_t *c; + + /* Strip off leading 'bootslot' command argument */ + argc--; + argv++; + + c = find_cmd_tbl(argv[0], cmd_bootslot_sub, + ARRAY_SIZE(cmd_bootslot_sub)); + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + + +U_BOOT_CMD(bootslot, INT_MAX, 1, do_bootslot, + "Bootslot command", + " - select and boot slot based on counters\n" + "boot [<slot>] - Boot the passed or first valid slot in $bootslots\n" + "list [<slot>] - List remaining boot tries for passed or all slots in $bootslots\n" + "reset [<slot>] - Reset remaining boot tries for all or passed slot\n" +); -- 2.18.0

4 5

[PATCH 00/33] sandbox: Move to SDL2
by Simon Glass 14 Feb '20

14 Feb '20

7 47

[U-Boot] [PATCH v3 0/5] usb: host: dwc2: use driver model for PHY and CLOCK
by Patrick Delaunay 14 Feb '20

14 Feb '20

In this serie I update the DWC2 host driver to use the device tree information and the associated PHY and CLOCK drivers when they are available. CI-Travis build is OK for all target after V3: https://travis-ci.org/patrickdelaunay/u-boot/builds/609496187 In V2, I cause the warnings for some boards: drivers/usb/host/built-in.o: In function `dwc2_usb_remove': drivers/usb/host/dwc2.c:1441: undefined reference to `clk_disable_bulk' I test this serie on stm32mp157c-ev1 board, with PHY and CLK support The U-CLASS are provided by: - PHY by USBPHYC driver = ./drivers/phy/phy-stm32-usbphyc.c - CLOCK by RCC clock driver = drivers/clk/clk_stm32mp1.c - RESET by RCC reset driver = drivers/reset/stm32-reset.c And I activate the configuration +CONFIG_USB_DWC2=y PS: it is not the default configuration to avoid conflict with gadget driver To solve a binding issue, I also deactivate the gadget support: by default only one driver is bound to theusbotg_hs node with "snps,dwc2" compatible, and today it is the device one (the first in the driver list). I also need to deactivate hnp-srp support with: &usbotg_hs { /* need to disable ONLY for HOST support */ hnp-srp-disable; }; WARNING: OTG with device or host support is not correctly handle by DWC2 driver (see example for dynamic OTG role in DWC3 driver). The tests executed on the stm32mp157c-ev1 target: STM32MP> usb start starting USB... Bus usb-otg@49000000: USB DWC2 Bus usbh-ehci@5800d000: USB EHCI 1.00 scanning bus usb-otg@49000000 for devices... 2 USB Device(s) found scanning bus usbh-ehci@5800d000 for devices... 3 USB Device(s) found scanning usb for storage devices... 2 Storage Device(s) found STM32MP> usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Mass Storage (480 Mb/s, 300mA) Verbatim STORE N GO 070731C8ACD7EE97 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Hub (480 Mb/s, 2mA) | +-3 Mass Storage (480 Mb/s, 500mA) Generic USB Storage STM32MP> ls usb 0 <DIR> 4096 . <DIR> 4096 .. <DIR> 16384 lost+found <DIR> 4096 record 1490212 xipImage 21058006 vmlinux STM32MP> load usb 0 0xC0000000 vmlinux 21058006 bytes read in 10851 ms (1.9 MiB/s) Changes in v3: - Add stub for clk_disable_bulk Changes in v2: - update dev_err - update commit message - change dev_err to dev_dbg for PHY function call - treat dwc2_shutdown_phy error - add clk_disable_bulk in dwc2_usb_remove Patrick Delaunay (5): dm: clk: add stub for clk_disable_bulk when CONFIG_CLK is desactivated usb: host: dwc2: add phy support usb: host: dwc2: add clk support usb: host: dwc2: force reset assert usb: host: dwc2: add trace to have clean usb start drivers/usb/host/dwc2.c | 100 +++++++++++++++++++++++++++++++++++++++- include/clk.h | 4 ++ 2 files changed, 103 insertions(+), 1 deletion(-) -- 2.17.1

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[PATCH] tools: mkimage: fix STM32 image format for big endian hosts
by Patrick Delaunay 14 Feb '20

14 Feb '20

From: Antonio Borneo <antonio.borneo(a)st.com> Two header fields are not properly converted to little endian before assignment, resulting in incorrect header while executing mkimage on big endian hosts. Convert the value of the header fields image_checksum and edcsa_algorithm to little endian before the assignment. Signed-off-by: Antonio Borneo <antonio.borneo(a)st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay(a)st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> --- tools/stm32image.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/stm32image.c b/tools/stm32image.c index ff3ec5f3f2..18357c0518 100644 --- a/tools/stm32image.c +++ b/tools/stm32image.c @@ -45,7 +45,7 @@ static void stm32image_default_header(struct stm32_header *ptr) ptr->magic_number = HEADER_MAGIC; ptr->header_version[VER_MAJOR_IDX] = HEADER_VERSION_V1; ptr->option_flags = HEADER_DEFAULT_OPTION; - ptr->ecdsa_algorithm = 1; + ptr->ecdsa_algorithm = cpu_to_le32(1); ptr->binary_type = HEADER_TYPE_UBOOT; } @@ -131,7 +131,8 @@ static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd, stm32hdr->image_entry_point = cpu_to_le32(params->ep); stm32hdr->image_length = cpu_to_le32((uint32_t)sbuf->st_size - sizeof(struct stm32_header)); - stm32hdr->image_checksum = stm32image_checksum(ptr, sbuf->st_size); + stm32hdr->image_checksum = + cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size)); } /* -- 2.17.1

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[PATCH 0/4] Several patch to solve warning on stm32mp1 board with W=1
by Patrick Delaunay 14 Feb '20

14 Feb '20

Hi, this serie includes few remaining patches on STM32 drivers or board code to avoid warning when the board stm32mp1 is compiled with W=1. See also patches on: - ENV (V2): http://patchwork.ozlabs.org/patch/1230200/ - MTD (merged): http://patchwork.ozlabs.org/patch/1228814/ Regards Patrick Delaunay (4): board: stm32mp1: board: add include for dfu board: stm32mp1: change dfu function to static pinctrl: stmfx: update the result type of dm_i2c_reg_read clk: stm32mp1: solve type issue in stm32mp1_lse_enable and stm32mp1_clktree board/st/stm32mp1/stm32mp1.c | 5 +++-- drivers/clk/clk_stm32mp1.c | 9 +++++---- drivers/pinctrl/pinctrl-stmfx.c | 7 ++++--- 3 files changed, 12 insertions(+), 9 deletions(-) -- 2.17.1

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[PATCH 0/9] stm32mp1 devicetre-tree and board update
by Patrick Delaunay 14 Feb '20

14 Feb '20

This serie provides the device tree resync with Kernel 5.4-rc5, solves some dtc compilation issue for U-Boot addon and some minor update in stm32mp1 board (documentation and support of revZ). Antonio Borneo (1): ARM: dts: stm32mp1: move FDCAN to PLL4_R Patrick Delaunay (8): ARM: dts: stm32mp1: DT alignment with kernel v5.4 stm32mp1: pwr: use the last binding for pwr ARM: dts: stm32mp1: DT alignment with kernel v5.5-rc7 ARM: dts: stm32mp1: correct ddr node ARM: dts: stm32m1: add reg for pll nodes board: stm32mp1: update readme doc: add board documentation for stm32mp1 stm32mp1: support of STM32MP15x Rev.Z arch/arm/dts/stm32mp15-ddr.dtsi | 2 +- arch/arm/dts/stm32mp157-pinctrl.dtsi | 31 +- arch/arm/dts/stm32mp157-u-boot.dtsi | 4 +- .../arm/dts/stm32mp157a-avenger96-u-boot.dtsi | 10 +- arch/arm/dts/stm32mp157a-avenger96.dts | 11 +- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 27 +- arch/arm/dts/stm32mp157a-dk1.dts | 73 ++- arch/arm/dts/stm32mp157c-dk2.dts | 13 + arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 10 +- arch/arm/dts/stm32mp157c-ed1.dts | 28 +- arch/arm/dts/stm32mp157c-ev1.dts | 8 +- arch/arm/dts/stm32mp157c.dtsi | 48 +- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 10 +- arch/arm/dts/stm32mp15xx-dhcom.dtsi | 8 +- arch/arm/mach-stm32mp/cpu.c | 3 + arch/arm/mach-stm32mp/include/mach/stm32.h | 1 - .../arm/mach-stm32mp/include/mach/sys_proto.h | 1 + arch/arm/mach-stm32mp/pwr_regulator.c | 23 +- arch/arm/mach-stm32mp/syscon.c | 1 - board/st/stm32mp1/README | 504 +-------------- doc/board/index.rst | 1 + doc/board/st/index.rst | 9 + doc/board/st/stm32mp1.rst | 598 ++++++++++++++++++ .../clock/st,stm32mp1.txt | 32 +- .../mtd/stm32-fmc2-nand.txt | 6 +- 25 files changed, 845 insertions(+), 617 deletions(-) create mode 100644 doc/board/st/index.rst create mode 100644 doc/board/st/stm32mp1.rst -- 2.17.1

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[PATCH 0/2] Fix Ethernet boot in am437x-evm
by Faiz Abbas 14 Feb '20

14 Feb '20

The following patches fix ethernet boot in am437x-evm. Faiz Abbas (2): arm: dts: am437x-gp-evm: Add some nodes to u-boot.dtsi configs: am43xx_evm: Enable SPL_ETH_SUPPORT arch/arm/dts/am437x-gp-evm-u-boot.dtsi | 16 ++++++++++++++++ configs/am43xx_evm_defconfig | 1 + 2 files changed, 17 insertions(+) -- 2.19.2

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