March 2019 - U-Boot

[U-Boot] IMX6 NAND boot regression
by Tim Harvey 05 Mar '19

05 Mar '19

Stefan, I'm trying to track down an IMX6 SPL NAND boot regression that started in v2018.07 with your patch series to mxs_nand. I bisected it back to '5346c31e305a37d39f535cc0d5ae87d8b7e81230 mtd: nand: mxs_nand: use self init'. With this particular patch nand bbt scanning would crash the board because of nand_chip.scan_btt not being assigned. This was later fixed in '96d0be07e7498e7174daa6f3b56fc807b9feb71d MTD: nand: mxs_nand_spl: Fix empty function pointer for BBT' but cherry-picking that on top of 5346c31 fixes the immediate crash while scanning but then I find that mxs_read_page_ecc() hangs on the 4th page of reading u-boot.img from the NAND. This gets worse 2 patches later where in '28897e8d21f8e197e259a91c693de09cd81f2d5a: mtd: nand: mxs_nand: use structure for BCH geometry' I find that the first byte of every page read is wrong because mxs_nand_swap_block_mark() is getting called on the page which swaps the first bytes with oob. There are several IMX6 boards out there using both NAND and SPL I believe that I would assume were broken by this series. Any ideas on the proper resolution? Regards, Tim

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[U-Boot] [PATCH] net:phy:aquantia Set only autoneg on in register 4.c441
by Valentin-catalin Neacsu 05 Mar '19

05 Mar '19

For AQR405 in register 4.c441 bit 15 was override with 0. This caused the phy to not negotiate at 2.5GB rate with mac. To avoid this override it needed first to know the previous value of reg 4.c441 and set only bit 3. Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu(a)nxp.com> --- drivers/net/phy/aquantia.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 84f7f0ef1e..c5bd0cecae 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -58,9 +58,14 @@ int aquantia_config(struct phy_device *phydev) AQUANTIA_SYSTEM_INTERFACE_SR); /* If SI is USXGMII then start USXGMII autoneg*/ if ((val & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) { + reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS, + AQUANTIA_VENDOR_PROVISIONING_REG); + + reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA; + phy_write(phydev, MDIO_MMD_PHYXS, AQUANTIA_VENDOR_PROVISIONING_REG, - AQUANTIA_USX_AUTONEG_CONTROL_ENA); + reg_val1); printf("%s: system interface USXGMII\n", phydev->dev->name); } else { -- 2.17.1

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[U-Boot] [PATCH 2/2] net: phy: micrel: Find Micrel PHY node correctly
by James Byrne 05 Mar '19

05 Mar '19

In some of the device trees that specify skew values for KSZ90x1 PHYs the values are stored (incorrectly) in the MAC node, whereas in others it is in an 'ethernet-phy' subnode. Previously the code would fail to find and program these skew values, so this commit changes it to look for an "ethernet-phy" subnode first, and revert to looking in the MAC node if there isn't one. The device trees affected (where the skew values are in a subnode) are imx6qdl-icore-rqs.dtsi, r8a77970-eagle.dts, r8a77990-ebisu.dts, r8a77995-draak.dts, salvator-common.dtsi, sama5d3xcm.dtsi, sama5d3xcm_cmp.dtsi, socfpga_cyclone5_vining_fpga.dts, socfpga_stratix10_socdk.dts and ulcb.dtsi. Before this change the skew values in these device trees would be ignored. The device trees where the skew values are in the MAC node are socfpga_arria10_socdk.dtsi, socfpga_arria5_socdk.dts, socfpga_cyclone5_de0_nano_soc.dts, socfpga_cyclone5_de10_nano.dts, socfpga_cyclone5_de1_soc.dts, socfpga_cyclone5_is1.dts, socfpga_cyclone5_socdk.dts, socfpga_cyclone5_sockit.dts. These should be unaffected by this change. The changes were tested on a sama5d3xcm. Signed-off-by: James Byrne <james.byrne(a)origamienergy.com> --- drivers/net/phy/micrel_ksz90x1.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index 1f8d86ab2e..8dec9f2367 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -114,12 +114,20 @@ static int ksz90x1_of_config_group(struct phy_device *phydev, int val[4]; int i, changed = 0, offset, max; u16 regval = 0; + ofnode node; if (!drv || !drv->writeext) return -EOPNOTSUPP; + /* Look for a PHY node under the Ethernet node */ + node = dev_read_subnode(dev, "ethernet-phy"); + if (!ofnode_valid(node)) { + /* No node found, look in the Ethernet node */ + node = dev_ofnode(dev); + } + for (i = 0; i < ofcfg->grpsz; i++) { - val[i] = dev_read_u32_default(dev, ofcfg->grp[i].name, ~0); + val[i] = ofnode_read_u32_default(node, ofcfg->grp[i].name, ~0); offset = ofcfg->grp[i].off; if (val[i] == -1) { /* Default register value for KSZ9021 */ -- 2.17.1

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[U-Boot] [PATCH 1/2] net: phy: micrel: Use correct skew values on KSZ9021
by James Byrne 05 Mar '19

05 Mar '19

Commit ff7bd212cb8a ("net: phy: micrel: fix divisor value for KSZ9031 phy skew") fixed the skew value divisor for the KSZ9031, but left the code using the same divisor for the KSZ9021, which is incorrect. The preceding commit c16e69f702b1 ("net: phy: micrel: add documentation for Micrel KSZ90x1 binding") added the DTS documentation for the KSZ90x1, changing it from the equivalent file in the Linux kernel to correctly state that for this part the skew value is set in 120ps steps, whereas the Linux documentation and driver continue to this day to use the incorrect value of 200 that came from the original KSZ9021 datasheet before it was corrected in revision 1.2 (Feb 2014). This commit sorts out the resulting confusion in a consistent way by making the following changes: - Update the documentation to be clear about what the skew values mean, in the same was as for the KSZ9031. - Update the Micrel PHY driver to select the appropriate divisor for both parts. - Adjust all the device trees that state skew values for KSZ9021 PHYs to use values based on 120ps steps instead of 200ps steps. This will result in the same values being programmed into the skew registers as the equivalent device trees in the Linux kernel do, where it incorrectly uses 200ps steps (since that's where all these device trees were copied from). Signed-off-by: James Byrne <james.byrne(a)origamienergy.com> --- arch/arm/dts/sama5d3xcm.dtsi | 32 +++++++++---------- arch/arm/dts/sama5d3xcm_cmp.dtsi | 32 +++++++++---------- arch/arm/dts/socfpga_arria5_socdk.dts | 4 +-- arch/arm/dts/socfpga_cyclone5_is1.dts | 4 +-- arch/arm/dts/socfpga_cyclone5_socdk.dts | 4 +-- arch/arm/dts/socfpga_cyclone5_sockit.dts | 4 +-- arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 4 +-- .../net/micrel-ksz90x1.txt | 27 ++++++++++++++++ drivers/net/phy/micrel_ksz90x1.c | 14 +++++--- 9 files changed, 79 insertions(+), 46 deletions(-) diff --git a/arch/arm/dts/sama5d3xcm.dtsi b/arch/arm/dts/sama5d3xcm.dtsi index 2cf9c3611d..d123057f30 100644 --- a/arch/arm/dts/sama5d3xcm.dtsi +++ b/arch/arm/dts/sama5d3xcm.dtsi @@ -44,28 +44,28 @@ reg = <0x1>; interrupt-parent = <&pioB>; interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; + txen-skew-ps = <480>; + txc-skew-ps = <1800>; + rxdv-skew-ps = <240>; + rxc-skew-ps = <1800>; + rxd0-skew-ps = <240>; + rxd1-skew-ps = <240>; + rxd2-skew-ps = <240>; + rxd3-skew-ps = <240>; }; ethernet-phy@7 { reg = <0x7>; interrupt-parent = <&pioB>; interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; + txen-skew-ps = <480>; + txc-skew-ps = <1800>; + rxdv-skew-ps = <240>; + rxc-skew-ps = <1800>; + rxd0-skew-ps = <240>; + rxd1-skew-ps = <240>; + rxd2-skew-ps = <240>; + rxd3-skew-ps = <240>; }; }; }; diff --git a/arch/arm/dts/sama5d3xcm_cmp.dtsi b/arch/arm/dts/sama5d3xcm_cmp.dtsi index 77638c3cbe..332b057e0a 100644 --- a/arch/arm/dts/sama5d3xcm_cmp.dtsi +++ b/arch/arm/dts/sama5d3xcm_cmp.dtsi @@ -43,28 +43,28 @@ reg = <0x1>; interrupt-parent = <&pioB>; interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; + txen-skew-ps = <480>; + txc-skew-ps = <1800>; + rxdv-skew-ps = <240>; + rxc-skew-ps = <1800>; + rxd0-skew-ps = <240>; + rxd1-skew-ps = <240>; + rxd2-skew-ps = <240>; + rxd3-skew-ps = <240>; }; ethernet-phy@7 { reg = <0x7>; interrupt-parent = <&pioB>; interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - txen-skew-ps = <800>; - txc-skew-ps = <3000>; - rxdv-skew-ps = <400>; - rxc-skew-ps = <3000>; - rxd0-skew-ps = <400>; - rxd1-skew-ps = <400>; - rxd2-skew-ps = <400>; - rxd3-skew-ps = <400>; + txen-skew-ps = <480>; + txc-skew-ps = <1800>; + rxdv-skew-ps = <240>; + rxc-skew-ps = <1800>; + rxd0-skew-ps = <240>; + rxd1-skew-ps = <240>; + rxd2-skew-ps = <240>; + rxd3-skew-ps = <240>; }; }; diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 90e676e701..fa972e287f 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -67,9 +67,9 @@ rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; txen-skew-ps = <0>; - txc-skew-ps = <2600>; + txc-skew-ps = <1560>; rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; + rxc-skew-ps = <1200>; }; &gpio0 { diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index b7054bfd5a..31fa8dcfa6 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -46,9 +46,9 @@ rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; txen-skew-ps = <0>; - txc-skew-ps = <2600>; + txc-skew-ps = <1560>; rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; + rxc-skew-ps = <1200>; }; &gpio1 { diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 6f138b2b26..95c7619b8d 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -71,9 +71,9 @@ rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; txen-skew-ps = <0>; - txc-skew-ps = <2600>; + txc-skew-ps = <1560>; rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; + rxc-skew-ps = <1200>; }; &gpio0 { diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts index c155ff02eb..90669cde45 100644 --- a/arch/arm/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts @@ -128,9 +128,9 @@ rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; txen-skew-ps = <0>; - txc-skew-ps = <2600>; + txc-skew-ps = <1560>; rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; + rxc-skew-ps = <1200>; }; &gpio0 { /* GPIO 0..29 */ diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts index 355b3dbf43..ac57f41cb5 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -85,9 +85,9 @@ rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; txen-skew-ps = <0>; - txc-skew-ps = <2600>; + txc-skew-ps = <1560>; rxdv-skew-ps = <0>; - rxc-skew-ps = <2000>; + rxc-skew-ps = <1200>; }; }; }; diff --git a/doc/device-tree-bindings/net/micrel-ksz90x1.txt b/doc/device-tree-bindings/net/micrel-ksz90x1.txt index 307f53f726..a214d35fc9 100644 --- a/doc/device-tree-bindings/net/micrel-ksz90x1.txt +++ b/doc/device-tree-bindings/net/micrel-ksz90x1.txt @@ -14,6 +14,33 @@ KSZ9021: value is 0, the maximum value is 1800, and it is incremented by 120ps steps. + The KSZ9021 hardware supports a range of skew values from negative to + positive, where the specific range is property dependent. All values + specified in the devicetree are offset by the minimum value so they + can be represented as positive integers in the devicetree since it's + difficult to represent a negative number in the devictree. + + The following 4-bit values table applies to all the skew properties: + + Pad Skew Value Delay (ps) Devicetree Value + ------------------------------------------------------ + 0000 -840ps 0 + 0001 -720ps 120 + 0010 -600ps 240 + 0011 -480ps 360 + 0100 -360ps 480 + 0101 -240ps 600 + 0110 -120ps 720 + 0111 0ps 840 + 1000 120ps 960 + 1001 240ps 1080 + 1010 360ps 1200 + 1011 480ps 1320 + 1100 600ps 1440 + 1101 720ps 1560 + 1110 840ps 1680 + 1111 960ps 1800 + Optional properties: - rxc-skew-ps : Skew control of RXC pad diff --git a/drivers/net/phy/micrel_ksz90x1.c b/drivers/net/phy/micrel_ksz90x1.c index 63e7b0242b..1f8d86ab2e 100644 --- a/drivers/net/phy/micrel_ksz90x1.c +++ b/drivers/net/phy/micrel_ksz90x1.c @@ -33,10 +33,14 @@ #define CTRL1000_CONFIG_MASTER (1 << 11) #define CTRL1000_MANUAL_CONFIG (1 << 12) +#define KSZ9021_PS_TO_REG 120 + /* KSZ9031 PHY Registers */ #define MII_KSZ9031_MMD_ACCES_CTRL 0x0d #define MII_KSZ9031_MMD_REG_DATA 0x0e +#define KSZ9031_PS_TO_REG 60 + static int ksz90xx_startup(struct phy_device *phydev) { unsigned phy_ctl; @@ -102,11 +106,11 @@ static const struct ksz90x1_reg_field ksz9031_clk_grp[] = { }; static int ksz90x1_of_config_group(struct phy_device *phydev, - struct ksz90x1_ofcfg *ofcfg) + struct ksz90x1_ofcfg *ofcfg, + int ps_to_regval) { struct udevice *dev = phydev->dev; struct phy_driver *drv = phydev->drv; - const int ps_to_regval = 60; int val[4]; int i, changed = 0, offset, max; u16 regval = 0; @@ -148,7 +152,8 @@ static int ksz9021_of_config(struct phy_device *phydev) int i, ret = 0; for (i = 0; i < ARRAY_SIZE(ofcfg); i++) { - ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); + ret = ksz90x1_of_config_group(phydev, &ofcfg[i], + KSZ9021_PS_TO_REG); if (ret) return ret; } @@ -167,7 +172,8 @@ static int ksz9031_of_config(struct phy_device *phydev) int i, ret = 0; for (i = 0; i < ARRAY_SIZE(ofcfg); i++) { - ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); + ret = ksz90x1_of_config_group(phydev, &ofcfg[i], + KSZ9031_PS_TO_REG); if (ret) return ret; } -- 2.17.1

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[U-Boot] [RESEND PATCH] net: phy: Fix return value check phy_probe
by Michal Simek 05 Mar '19

05 Mar '19

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Don't ignore return value of phy_probe() call as the probe may fail and it needs to be reported. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Joe asked for it. --- drivers/net/phy/phy.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index a508fb550451..e0a925152e8b 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -670,7 +670,10 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, dev->drv = get_phy_driver(dev, interface); - phy_probe(dev); + if (phy_probe(dev)) { + printf("%s, PHY probe failed\n", __func__); + return NULL; + } if (addr >= 0 && addr < PHY_MAX_ADDR) bus->phymap[addr] = dev; -- 1.9.1

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[U-Boot] [RESEND PATCH] net: phy: Reloc next and prev pointers inside phy_drivers
by Michal Simek 05 Mar '19

05 Mar '19

From: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> This patch relocates the pointers inside phy_drivers incase of manual reloc. Without this reloc, these points to invalid pre relocation address and hence causes exception or hang. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- Joe asked for it. --- drivers/net/phy/phy.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index ed4000991165..e0a925152e8b 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -462,6 +462,18 @@ static LIST_HEAD(phy_drivers); int phy_init(void) { +#ifdef CONFIG_NEEDS_MANUAL_RELOC + /* + * The pointers inside phy_drivers also needs to be updated incase of + * manual reloc, without which these points to some invalid + * pre reloc address and leads to invalid accesses, hangs. + */ + struct list_head *head = &phy_drivers; + + head->next = (void *)head->next + gd->reloc_off; + head->prev = (void *)head->prev + gd->reloc_off; +#endif + #ifdef CONFIG_B53_SWITCH phy_b53_init(); #endif -- 1.9.1

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[U-Boot] [PATCH v4 0/7] Add netcp networking support on K2G ICE EVM
by Murali Karicheri 05 Mar '19

05 Mar '19

This patch series add networking capability to K2G ICE EVM based on netcp driver. Networking function has been tested using the latest master branch from u-boot repo. Following boot mode has been tested for networking. Net boot (tftp images over ethernet interface and boot kernel) log at https://pastebin.ubuntu.com/p/b3nyCXPhWc/ MMC boot: (load images from boot folder of rootfs and boot kernel) log at https://pastebin.ubuntu.com/p/FWycmKd9KB/ Used Linux upstream linux kernel version 4.19.9 for the tests. Please review and apply if this looks good. Thanks Revision history: v4: Sorted pins by pin number in patch 1 and 2 as per comment. Collected Acked-by and included in patch v3: Addressed comment to use KConfig for enable TI PHY driver and also netcp driver comment to use proper function as in cpsw driver. Rebased to latest on master branch. v2: Collected Reviewed-by for patch 1 and 2. Rebased to latest on master Murali Karicheri (7): ARM: k2g-gp-evm: update to rgmii pinmux configuration ARM: k2g-ice: Add pinmux support for rgmii interface net: netcp: add support for phy with rgmii ids ARM: k2g: add a workaround to reset the phy ARM: dts: k2g-evm: remove unused phy-mode property from phy node k2g: config enable ti phy dp83867 for k2g ARM: dts: k2g-ice: add dt node for netcp arch/arm/dts/keystone-k2g-evm.dts | 1 - arch/arm/dts/keystone-k2g-ice.dts | 35 +++++++++++++ .../mach-keystone/include/mach/hardware-k2g.h | 3 ++ arch/arm/mach-keystone/include/mach/mux-k2g.h | 5 ++ board/ti/ks2_evm/board_k2g.c | 15 ++++++ board/ti/ks2_evm/mux-k2g.h | 51 +++++++++++++------ configs/k2g_evm_defconfig | 1 + drivers/net/ti/keystone_net.c | 22 +++++++- 8 files changed, 116 insertions(+), 17 deletions(-) -- 2.17.0

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[U-Boot] [PATCH v5 0/3] Add MMD PHY helpers
by Carlo Caione 05 Mar '19

05 Mar '19

Introduce phy_{read|write}_mmd() helpers and modify the mdio command to make good use of them. Fix the ti driver in the same patchset. Carlo Caione (3): net: phy: Add generic helpers to access MMD PHY registers net: phy: ti: use generic helpers to access MMD registers cmd: mdio: Switch to generic helpers when accessing the registers cmd/mdio.c | 27 +++++---- drivers/net/phy/phy.c | 4 ++ drivers/net/phy/ti.c | 130 ++++++++---------------------------------- include/phy.h | 70 +++++++++++++++++++++++ 4 files changed, 115 insertions(+), 116 deletions(-) -- 2.19.1

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[U-Boot] [PATCH] drivers: net: ldpaa_eth: fix resource leak
by Pankaj Bansal 05 Mar '19

05 Mar '19

if an error occurs in ldpaa_eth_init, need to free all resources before returning the error. Threfore, free net_dev before returning from ldpaa_eth_init. Signed-off-by: Pankaj Bansal <pankaj.bansal(a)nxp.com> diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 73b7ba29df..34253e3924 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -1074,6 +1074,7 @@ int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if) priv = (struct ldpaa_eth_priv *)malloc(sizeof(struct ldpaa_eth_priv)); if (!priv) { printf("ldpaa_eth_priv malloc() failed\n"); + free(net_dev); return -ENOMEM; } memset(priv, 0, sizeof(struct ldpaa_eth_priv)); -- 2.17.1

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[U-Boot] [PATCH v3 0/6] net: phy: Allow disabling SmartEEE for Atheros PHYs
by Vladimir Oltean 05 Mar '19

05 Mar '19

The patchset adds support for disabling a PHY feature that may cause packet loss, and also cleans up the atheros.c driver a bit. As part of the cleanup, there are also some functional changes for the AR8035 in the RGMII internal delay area. Due to a mistake, RGMII Tx internal delay used to be implicitly always enabled. This is now corrected. Users of this driver may need to update their bindings to explicitly request the Tx internal delays back. Changes in v3: * Replaced all magic numbers with macros * Squashed "net: phy: ar803x: Use phy_read_mmd and phy_write_mmd functions" into new "net: phy: ar803x: Clarify the configuration of the CLK_25M output pin" patch * Fixed unconditional enabling of RGMII TxID for AR8035 Vladimir Oltean (6): net: phy: ar803x: Address packet drops at low traffic rate due to SmartEEE feature net: phy: ar803x: Make RGMII Tx delays actually configurable for AR8035 net: phy: ar803x: Use common functions for RGMII internal delays net: phy: ar803x: Explicitly disable RGMII delays net: phy: ar803x: Clarify the configuration of the CLK_25M output pin net: phy: ar803x: Clarify the intention of ar8021_config drivers/net/phy/Kconfig | 21 ++++++++ drivers/net/phy/atheros.c | 128 ++++++++++++++++++++++++++++++++-------------- 2 files changed, 111 insertions(+), 38 deletions(-) -- 2.7.4

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