February 2019 - U-Boot

[U-Boot] [PATCH 0/7] AM65x HS device support
by Andrew F. Davis 18 Feb '19

18 Feb '19

Hello all, This series brings up HS device support on the AM65x platform. Support for HS on K3 family devices is a bit different than previous devices but for the most part all that has been abstracted into the SECDEV package, allowing for a rather straight forward implementation here. Thanks, Andrew Andrew F. Davis (7): arm: K3: Avoid use of MCU_PSRAM0 before SYSFW is loaded firmware: ti_sci: Add support for firewall management firmware: ti_sci: Modify auth_boot TI-SCI API to match new version arm: mach-k3: Add secure device support arm: mach-k3: Add secure device build support configs: Add a config for AM65x High Security EVM doc: Update info on using K3 secure devices MAINTAINERS | 4 + arch/arm/Kconfig | 2 +- arch/arm/mach-k3/Makefile | 1 + arch/arm/mach-k3/am6_init.c | 8 +- arch/arm/mach-k3/config.mk | 25 +++ arch/arm/mach-k3/config_secure.mk | 44 ++++ arch/arm/mach-k3/include/mach/am6_hardware.h | 3 - arch/arm/mach-k3/security.c | 63 ++++++ configs/am65x_hs_evm_a53_defconfig | 74 +++++++ configs/am65x_hs_evm_r5_defconfig | 90 +++++++++ doc/README.ti-secure | 20 +- drivers/firmware/ti_sci.c | 202 ++++++++++++++++++- drivers/firmware/ti_sci.h | 139 ++++++++++++- include/linux/soc/ti/ti_sci_protocol.h | 68 ++++++- tools/k3_fit_atf.sh | 8 +- 15 files changed, 722 insertions(+), 29 deletions(-) create mode 100644 arch/arm/mach-k3/config_secure.mk create mode 100644 arch/arm/mach-k3/security.c create mode 100644 configs/am65x_hs_evm_a53_defconfig create mode 100644 configs/am65x_hs_evm_r5_defconfig -- 2.19.1

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[U-Boot] [PATCH v1 0/2] Update pinctrl-uclass
by Patrice Chotard 18 Feb '19

18 Feb '19

This series adds: - For system with multiple pincontroller device, insure probe order to avoid race condition using sequence number (alias) - Avoid to bind child node with gpio-controller properties. Patrice Chotard (1): dm: pinctrl: Avoid race condition on probe for UCLASS_PINCTRL Patrick Delaunay (1): dm: pinctrl: Skip gpio-controller node in pinconfig_post_bind() drivers/pinctrl/pinctrl-uclass.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) -- 1.9.1

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[U-Boot] [PATCH] hsdk: readme: Suggest getting pyelftools with pip
by Alexey Brodkin 18 Feb '19

18 Feb '19

Signed-off-by: Alexey Brodkin <abrodkin(a)synopsys.com> Suggested-by: Yunir Salimzyanov <yunir(a)synopsys.com> --- board/synopsys/hsdk/README | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/board/synopsys/hsdk/README b/board/synopsys/hsdk/README index e29a6a1727..9155f17c6e 100644 --- a/board/synopsys/hsdk/README +++ b/board/synopsys/hsdk/README @@ -83,10 +83,11 @@ Useful notes on bulding and using of U-Boot on ARC HS Development Kit (AKA HSDK) HSDK board. Note that Python3 script is used for generation of a header, thus - to get that done it's required to have Python3 with elftools installed. - On CentOS/RHEL/Fedora this could be installed with: + to get that done it's required to have Python3 with "pyelftools" installed. + + "pyelftools" could be installed with help of "pip" even w/o root rights: ------------------------->8---------------------- - sudo dnf install python3-pyelftools + python3 -m pip install --user pyelftools ------------------------->8---------------------- EXECUTING U-BOOT -- 2.17.1

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[U-Boot] [PATCH] fpga: Add support for getting external data address and length
by tien.fong.chee＠intel.com 18 Feb '19

18 Feb '19

From: Tien Fong Chee <tien.fong.chee(a)intel.com> This function supports getting both data address and length for existing FPGA subimage and FPGA external data. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> --- cmd/fpga.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cmd/fpga.c b/cmd/fpga.c index 88a8e3f..b1f224b 100644 --- a/cmd/fpga.c +++ b/cmd/fpga.c @@ -343,9 +343,9 @@ static int do_fpga_loadmk(cmd_tbl_t *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - /* get fpga subimage data address and length */ - if (fit_image_get_data(fit_hdr, noffset, &fit_data, - &data_size)) { + /* get fpga subimage/external data address and length */ + if (fit_image_get_data_and_size(fit_hdr, noffset, + &fit_data, &data_size)) { puts("Fpga subimage data not found\n"); return CMD_RET_FAILURE; } -- 1.7.7.4

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[U-Boot] [PATCH v1] ARM: socfpga: stratix10: Return valid error code from FPGA driver
by chee.hong.ang＠intel.com 18 Feb '19

18 Feb '19

From: "Ang, Chee Hong" <chee.hong.ang(a)intel.com> This patch prevent the Stratix 10 FPGA driver incorrectly return the transaction ID as the mailbox error code. It should always return the actual mailbox error code from SDM firmware. Signed-off-by: Ang, Chee Hong <chee.hong.ang(a)intel.com> --- drivers/fpga/stratix10.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/fpga/stratix10.c b/drivers/fpga/stratix10.c index aae0521..d8e3250 100644 --- a/drivers/fpga/stratix10.c +++ b/drivers/fpga/stratix10.c @@ -172,7 +172,7 @@ static int send_reconfig_data(const void *rbf_data, size_t rbf_size, u32 resp_windex = 0; u32 resp_count = 0; u32 xfer_count = 0; - u8 resp_err = 0; + int resp_err = 0; u8 cmd_id = 1; u32 args[3]; int ret; @@ -195,11 +195,9 @@ static int send_reconfig_data(const void *rbf_data, size_t rbf_size, rbf_size = 0; } - ret = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA, + resp_err = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA, MBOX_CMD_INDIRECT, 3, args); - if (ret) { - resp_err = 1; - } else { + if (!resp_err) { xfer_count++; cmd_id = add_transfer(xfer_pending, MBOX_RESP_BUFFER_SIZE, @@ -222,11 +220,8 @@ static int send_reconfig_data(const void *rbf_data, size_t rbf_size, /* Check for response's status */ if (!resp_err) { - ret = MBOX_RESP_ERR_GET(resp_hdr); - debug("Response error code: %08x\n", ret); - /* Error in response */ - if (ret) - resp_err = 1; + resp_err = MBOX_RESP_ERR_GET(resp_hdr); + debug("Response error code: %08x\n", resp_err); } ret = get_and_clr_transfer(xfer_pending, @@ -239,7 +234,7 @@ static int send_reconfig_data(const void *rbf_data, size_t rbf_size, } if (resp_err && !xfer_count) - return ret; + return resp_err; } } -- 2.7.4

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[U-Boot] [PATCH v2 0/8] spi: Add Allwinner A31 SPI driver
by Jagan Teki 18 Feb '19

18 Feb '19

This series add support for Allwinner A31 SPI controller driver. Fixed and improved conde when compared to previous series[1] Changes for v2: - use fifo_sta instead ctl reg in readl_poll - use ">=" instead of negotiation in readl_poll condition - use SPI_REG, SPI_BIT, SPI_CS macro for code improvement - use compatible check for A31 register enablement - add allwinner,sun6i-a31-spi compatible - exclude driver enable patches, since it has SPI kconfig dependencies. [1] https://patchwork.ozlabs.org/cover/1039178/ Any inputs? Jagan. Jagan Teki (8): spi: sun4i: Poll for rxfifo empty clk: sunxi: Implement SPI clocks, resets spi: sun4i: Simplify reg writes using set/clrbits_le32 spi: sun4i: Access registers and bits via enum offsets spi: sun4i: Support fifo_depth via drvdata spi: sun4i: Add CLK support spi: sun4: Add A31 spi controller support spi: sun4i: Driver cleanup drivers/clk/sunxi/clk_a10.c | 10 + drivers/clk/sunxi/clk_a10s.c | 7 + drivers/clk/sunxi/clk_a23.c | 7 + drivers/clk/sunxi/clk_a31.c | 13 ++ drivers/clk/sunxi/clk_a64.c | 7 + drivers/clk/sunxi/clk_a80.c | 13 ++ drivers/clk/sunxi/clk_a83t.c | 7 + drivers/clk/sunxi/clk_h3.c | 7 + drivers/clk/sunxi/clk_h6.c | 9 + drivers/clk/sunxi/clk_r40.c | 13 ++ drivers/clk/sunxi/clk_v3s.c | 4 + drivers/spi/Kconfig | 4 +- drivers/spi/sun4i_spi.c | 438 ++++++++++++++++++++++++----------- image.map | 4 + 14 files changed, 407 insertions(+), 136 deletions(-) create mode 100644 image.map -- 2.18.0.321.gffc6fa0e3

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Re: [U-Boot] [PATCH 1/7] riscv: add infrastructure for calling functions on other harts
by Rick Chen 18 Feb '19

18 Feb '19

<rick(a)andestech.com> 於 2019年2月18日週一上午11:00寫道： > > > > > -----Original Message----- > > From: Auer, Lukas [mailto:lukas.auer@aisec.fraunhofer.de] > > Sent: Monday, February 18, 2019 5:55 AM > > To: u-boot(a)lists.denx.de; Anup.Patel(a)wdc.com > > Cc: anup(a)brainfault.org; bmeng.cn(a)gmail.com; schwab(a)suse.de; Rick Jian-Zhi > > Chen(陳建志); palmer(a)sifive.com; Atish.Patra(a)wdc.com; agraf(a)suse.de > > Subject: Re: [PATCH 1/7] riscv: add infrastructure for calling functions on other > > harts > > > > On Tue, 2019-02-12 at 01:44 +0000, Anup Patel wrote: > > > > -----Original Message----- > > > > From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] > > > > Sent: Tuesday, February 12, 2019 3:44 AM > > > > To: u-boot(a)lists.denx.de > > > > Cc: Atish Patra <Atish.Patra(a)wdc.com>; Anup Patel > > > > <Anup.Patel(a)wdc.com>; Bin Meng <bmeng.cn(a)gmail.com>; Andreas > > Schwab > > > > <schwab(a)suse.de>; Palmer Dabbelt <palmer(a)sifive.com>; Alexander Graf > > > > <agraf(a)suse.de>; Lukas Auer <lukas.auer(a)aisec.fraunhofer.de>; Anup > > > > Patel <anup(a)brainfault.org>; Rick Chen <rick(a)andestech.com> > > > > Subject: [PATCH 1/7] riscv: add infrastructure for calling functions > > > > on other harts > > > > > > > > Harts on RISC-V boot independently and U-Boot is responsible for > > > > managing them. Functions are called on other harts with > > > > smp_call_function(), which sends inter-processor interrupts (IPIs) > > > > to all other harts. > > > > Functions are > > > > specified with their address and two function arguments (argument 2 > > > > and 3). > > > > The first function argument is always the hart ID of the hart > > > > calling the function. On the other harts, the IPI interrupt handler > > > > handle_ipi() must be > > > > called on software interrupts to handle the request and call the > > > > specified function. > > > > > > > > Functions are stored in the ipi_data data structure. Every hart has > > > > its own data structure in global data. While this is not required at > > > > the moment (all harts are expected to boot Linux), this does allow > > > > future expansion, where other harts may be used for monitoring or > > > > other tasks. > > > > > > > > Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > > > > --- > > > > > > > > arch/riscv/Kconfig | 19 +++++ > > > > arch/riscv/include/asm/global_data.h | 5 ++ > > > > arch/riscv/include/asm/smp.h | 53 +++++++++++++ > > > > arch/riscv/lib/Makefile | 1 + > > > > arch/riscv/lib/smp.c | 110 > > > > +++++++++++++++++++++++++++ > > > > 5 files changed, 188 insertions(+) > > > > create mode 100644 arch/riscv/include/asm/smp.h create mode > > > > 100644 > > > > arch/riscv/lib/smp.c > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index > > > > c45e4d73a8..c0842178dd 100644 > > > > --- a/arch/riscv/Kconfig > > > > +++ b/arch/riscv/Kconfig > > > > @@ -116,4 +116,23 @@ config RISCV_RDTIME config SYS_MALLOC_F_LEN > > > > default 0x1000 > > > > > > > > +config SMP > > > > + bool "Symmetric Multi-Processing" > > > > + help > > > > + This enables support for systems with more than one CPU. If > > > > + you say N here, U-Boot will run on single and multiprocessor > > > > + machines, but will use only one CPU of a multiprocessor > > > > + machine. If you say Y here, U-Boot will run on many, but not > > > > + all, single processor machines. > > > > + > > > > +config NR_CPUS > > > > + int "Maximum number of CPUs (2-32)" > > > > + range 2 32 > > > > + depends on SMP > > > > + default "8" > > > > + help > > > > + On multiprocessor machines, U-Boot sets up a stack for each > > > > CPU. > > > > + Stack memory is pre-allocated. U-Boot must therefore know the > > > > + maximum number of CPUs that may be present. > > > > + > > > > endmenu > > > > diff --git a/arch/riscv/include/asm/global_data.h > > > > b/arch/riscv/include/asm/global_data.h > > > > index a3a342c6e1..23a5f35af5 100644 > > > > --- a/arch/riscv/include/asm/global_data.h > > > > +++ b/arch/riscv/include/asm/global_data.h > > > > @@ -10,12 +10,17 @@ > > > > #ifndef __ASM_GBL_DATA_H > > > > #define __ASM_GBL_DATA_H > > > > > > > > +#include <asm/smp.h> > > > > + > > > > /* Architecture-specific global data */ struct arch_global_data { > > > > long boot_hart; /* boot hart id */ > > > > #ifdef CONFIG_SIFIVE_CLINT > > > > void __iomem *clint; /* clint base address */ > > > > #endif > > > > +#ifdef CONFIG_SMP > > > > + struct ipi_data ipi[CONFIG_NR_CPUS]; #endif > > > > }; > > > > > > > > #include <asm-generic/global_data.h> > > > > diff --git a/arch/riscv/include/asm/smp.h > > > > b/arch/riscv/include/asm/smp.h > > > > new file mode 100644 index 0000000000..bc863fdbaf > > > > --- /dev/null > > > > +++ b/arch/riscv/include/asm/smp.h > > > > @@ -0,0 +1,53 @@ > > > > +/* SPDX-License-Identifier: GPL-2.0 */ > > > > +/* > > > > + * Copyright (C) 2019 Fraunhofer AISEC, > > > > + * Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> */ > > > > + > > > > +#ifndef _ASM_RISCV_SMP_H > > > > +#define _ASM_RISCV_SMP_H > > > > + > > > > +/** > > > > + * struct ipi_data - Inter-processor interrupt (IPI) data > > > > structure > > > > + * > > > > + * IPIs are used for SMP support to communicate to other harts > > > > what > > > > +function to > > > > + * call. Functions are in the form > > > > + * void (*addr)(ulong hart, ulong arg0, ulong arg1). > > > > + * > > > > + * The function address and the two arguments, arg0 and arg1, are > > > > +stored in the > > > > + * IPI data structure. The hart ID is inserted by the hart > > > > handling the > > > > +IPI and > > > > + * calling the function. > > > > + * > > > > + * @addr: Address of function > > > > + * @arg0: First argument of function > > > > + * @arg1: Second argument of function > > > > + */ > > > > +struct ipi_data { > > > > + ulong addr; > > > > + ulong arg0; > > > > + ulong arg1; > > > > +}; > > > > + > > > > +/** > > > > + * handle_ipi() - interrupt handler for software interrupts > > > > + * > > > > + * The IPI interrupt handler must be called to handle software > > > > +interrupts. It > > > > + * calls the function specified in the hart's IPI data structure. > > > > + * > > > > + * @hart: Hart ID of the current hart > > > > + */ > > > > +void handle_ipi(ulong hart); > > > > + > > > > +/** > > > > + * smp_call_function() - Call a function on all other harts > > > > + * > > > > + * Send IPIs with the specified function call to all harts. > > > > + * > > > > + * @addr: Address of function > > > > + * @arg0: First argument of function > > > > + * @arg1: Second argument of function > > > > + * @return 0 if OK, -ve on error > > > > + */ > > > > +int smp_call_function(ulong addr, ulong arg0, ulong arg1); > > > > + > > > > +#endif > > > > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile > > > > index > > > > edfa61690c..19370f9749 100644 > > > > --- a/arch/riscv/lib/Makefile > > > > +++ b/arch/riscv/lib/Makefile > > > > @@ -14,6 +14,7 @@ obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o > > > > obj-y += interrupts.o > > > > obj-y += reset.o > > > > obj-y += setjmp.o > > > > +obj-$(CONFIG_SMP) += smp.o > > > > > > > > # For building EFI apps > > > > CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI) > > > > diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c new file > > > > mode 100644 > > > > index 0000000000..1266a2a0ef > > > > --- /dev/null > > > > +++ b/arch/riscv/lib/smp.c > > > > @@ -0,0 +1,110 @@ > > > > +// SPDX-License-Identifier: GPL-2.0+ > > > > +/* > > > > + * Copyright (C) 2019 Fraunhofer AISEC, > > > > + * Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> */ > > > > + > > > > +#include <common.h> > > > > +#include <dm.h> > > > > +#include <asm/barrier.h> > > > > +#include <asm/smp.h> > > > > + > > > > +DECLARE_GLOBAL_DATA_PTR; > > > > + > > > > +/** > > > > + * riscv_send_ipi() - Send inter-processor interrupt (IPI) > > > > + * > > > > + * Platform code must provide this function. > > > > + * > > > > + * @hart: Hart ID of receiving hart > > > > + * @return 0 if OK, -ve on error > > > > + */ > > > > +extern int riscv_send_ipi(int hart); > > > > + > > > > +/** > > > > + * riscv_clear_ipi() - Clear inter-processor interrupt (IPI) > > > > + * > > > > + * Platform code must provide this function. > > > > + * > > > > + * @hart: Hart ID of hart to be cleared > > > > + * @return 0 if OK, -ve on error > > > > + */ > > > > +extern int riscv_clear_ipi(int hart); > > > > + > > > > +static int send_ipi_many(struct ipi_data *ipi) { > > > > + ofnode node, cpus; > > > > + u32 reg; > > > > + int ret; > > > > + > > > > + cpus = ofnode_path("/cpus"); > > > > + if (!ofnode_valid(cpus)) { > > > > + pr_err("Can't find cpus node!\n"); > > > > + return -EINVAL; > > > > + } > > > > + > > > > + ofnode_for_each_subnode(node, cpus) { > > > > + if (!ofnode_is_available(node)) > > > > + continue; > > > > > > It is not correct to assume that whatever CPUs are marked > > > available will come online. It is possible that certain available > > > CPUs failed to come online due HW failure. > > > > > > > This was intended so that we don't send IPIs to harts, which have been > > explicitly marked as disabled. > > > > > Better approach would be keep an atomic bitmask of HARTs > > > that have entered U-Boot. All HARTs that enter U-Boot will > > > update the atomic HART available bitmask. We send IPI only > > > to HARTs that are available as-per atomic HART bitmask. > > > > > > > I'm not sure if this is required in U-Boot, since we are not relying on > > all harts to boot for U-Boot to function. We only try to boot all harts > > listed as available in the device tree. > > It may also need to get information from each cpu nodes. The cpu nodes is important, they must be match with the bitmask, or it maybe go wrong. So the bitmask way seem not be necessary. BR Rick > > Is there a situation, in which we would want to avoid sending an IPI to > > an unavailable hart? > > > > Thanks, > > Lukas > > > > > > + > > > > + /* read hart ID of CPU */ > > > > + ret = ofnode_read_u32(node, "reg", &reg); > > > > + if (ret) > > > > + continue; > > > > + > > > > + /* skip if it is the hart we are running on */ > > > > + if (reg == gd->arch.boot_hart) > > > > + continue; > > > > + > > > > + if (reg >= CONFIG_NR_CPUS) { > > > > + pr_err("Hart ID %d is out of range, increase > > > > CONFIG_NR_CPUS\n", > > > > + reg); > > > > + continue; > > > > + } > > > > + > > > > + gd->arch.ipi[reg].addr = ipi->addr; > > > > + gd->arch.ipi[reg].arg0 = ipi->arg0; > > > > + gd->arch.ipi[reg].arg1 = ipi->arg1; > > > > + mb(); > > > > + > > > > + ret = riscv_send_ipi(reg); > > > > + if (ret) > > > > + return ret; > > > > + } > > > > + > > > > + return 0; > > > > +} > > > > + > > > > +void handle_ipi(ulong hart) > > > > +{ > > > > + int ret; > > > > + void (*smp_function)(ulong hart, ulong arg0, ulong arg1); > > > > + > > > > + if (hart >= CONFIG_NR_CPUS) > > > > + return; > > > > + > > > > + ret = riscv_clear_ipi(hart); > > > > + if (ret) { > > > > + pr_err("Cannot clear IPI\n"); > > > > + return; > > > > + } > > > > + > > > > + smp_function = (void (*)(ulong, ulong, ulong))gd- > > > > > arch.ipi[hart].addr; > > > > + invalidate_icache_all(); > > > > + > > > > + smp_function(hart, gd->arch.ipi[hart].arg0, gd- > > > > >arch.ipi[hart].arg1); > > > > +} > > > > + > > > > +int smp_call_function(ulong addr, ulong arg0, ulong arg1) { > > > > + int ret = 0; > > > > + struct ipi_data ipi; > > > > + > > > > + ipi.addr = addr; > > > > + ipi.arg0 = arg0; > > > > + ipi.arg1 = arg1; > > > > + > > > > + ret = send_ipi_many(&ipi); > > > > + > > > > + return ret; > > > > +} > > > > -- > > > > 2.20.1 > > > > > > Regards, > > > Anup

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[U-Boot] [PATCH V2 1/3] sunxi: Use clrsetbits_le32 instead of multiple instruction
by Michael Trimarchi 18 Feb '19

18 Feb '19

Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- V1->V2: none --- arch/arm/mach-sunxi/dram_sun8i_a33.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c b/arch/arm/mach-sunxi/dram_sun8i_a33.c index 1da2727f98..83212aaddf 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c @@ -148,12 +148,8 @@ static void auto_set_timing_para(struct dram_para *para) reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); writel(reg_val, &mctl_ctl->dramtmg5); /* Set two rank timing and exit self-refresh timing */ - reg_val = readl(&mctl_ctl->dramtmg8); - reg_val &= ~(0xff << 8); - reg_val &= ~(0xff << 0); - reg_val |= (0x33 << 8); - reg_val |= (0x8 << 0); - writel(reg_val, &mctl_ctl->dramtmg8); + clrsetbits_le32(&mctl_ctl->dramtmg8, (0xff << 8) | (0xff << 0), + 0x33 << 8 | (0x8 << 0)); /* Set phy interface time */ reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | (wr_latency << 0); -- 2.17.1

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[U-Boot] [PATCH 0/1] GigaDevice id update
by Jiri Kastner 18 Feb '19

18 Feb '19

Vocore2 (mt76x8 device) has g25q128 flash, which is already in kernel's spi-nor.c Jiri Kastner (1): added missing GigaDevice chips drivers/mtd/spi/spi-nor-ids.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.20.1

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[U-Boot] [PATCH] configs: at91: remove SPL_GENERATE_ATMEL_PMECC_HEADER from non-nand configs
by Eugen.Hristev＠microchip.com 18 Feb '19

18 Feb '19

From: Eugen Hristev <eugen.hristev(a)microchip.com> SPL_GENERATE_ATMEL_PMECC_HEADER will generate a header for the SPL for NAND information. The initial stage 1 bootloader will use this header in case the NAND flash doesn't support commands to retrieve sector size, etc. However this header is bad for different boot media, like MMC or SPI. In case SD_BOOT or SPI_BOOT is used, remove the config for this. Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- It's time to fix this after the patches by Derald Woods: "49ad40298cc56" ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig which expose the nand PMECC header to Kconfig configs/at91sam9n12ek_mmc_defconfig | 1 - configs/at91sam9n12ek_spiflash_defconfig | 1 - configs/at91sam9x5ek_mmc_defconfig | 1 - configs/at91sam9x5ek_spiflash_defconfig | 1 - configs/sama5d36ek_cmp_mmc_defconfig | 1 - configs/sama5d36ek_cmp_spiflash_defconfig | 1 - configs/sama5d3_xplained_mmc_defconfig | 1 - configs/sama5d3xek_mmc_defconfig | 1 - configs/sama5d3xek_spiflash_defconfig | 1 - configs/sama5d4_xplained_mmc_defconfig | 1 - configs/sama5d4_xplained_spiflash_defconfig | 1 - configs/sama5d4ek_mmc_defconfig | 1 - configs/sama5d4ek_spiflash_defconfig | 1 - 13 files changed, 13 deletions(-) diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 853a264..6b2cfe9 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -41,7 +41,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index 273f91c..6388935 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -41,7 +41,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 5deabaf..ff86f93 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -43,7 +43,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 5f06231..d0eebcd 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -43,7 +43,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index ced445f..3026cab 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -43,7 +43,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 1f1fc8e..04ca6a8 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -43,7 +43,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index ab5aedc..f0995da 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -61,7 +61,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 404af1f..548b0b8 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -68,7 +68,6 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=4 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 43db387..824fa27 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -63,7 +63,6 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=4 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index cbfb645..9f15c97 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -58,7 +58,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index ef08339..89cfee4 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -59,7 +59,6 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=8 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index a121af4..9e2e1a9 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -58,7 +58,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 87052d5..c6ab3fd 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -56,7 +56,6 @@ CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=8 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y -- 2.7.4

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