February 2019 - U-Boot

[U-Boot] Pull request, u-boot-tegra/master
by Tom Warren 19 Feb '19

19 Feb '19

Tom, Please pull u-boot-tegra/master into U-Boot/master. Thanks! All Tegra builds are OK, and Stephen's automated test system reports that all tests pass. The following changes since commit f14de0014c56093feecf42ca38b8ae5b3878f176: Prepare v2019.04-rc2 (2019-02-18 21:36:39 -0500) are available in the git repository at: git://git.denx.de/u-boot-tegra.git master for you to fetch changes up to 283573fe7b93430e70d9f42f104a91738ea9eb60: ARM: tegra: Reserve 32MB for the Linux kernel (2019-02-19 14:38:08 -0800) ---------------------------------------------------------------- Jonathan Hunter (1): ARM: tegra: Reserve 32MB for the Linux kernel Peter Robinson (2): tegra: cleanup dangling comments in include/configs tegra20: common: fix USB_EHCI_TXFIFO_THRESH value Tristan Bastian (3): nyan-big: change spi delay nyan-big: add padding to its file ARM: tegra: enable ums on nyan boards arch/arm/dts/tegra124-nyan-big-u-boot.dtsi | 2 +- arch/arm/dts/tegra124-nyan.dtsi | 1 + doc/chromium/nyan-big.its | 2 +- include/configs/apalis-tk1.h | 2 -- include/configs/apalis_t30.h | 4 ---- include/configs/beaver.h | 6 ------ include/configs/cardhu.h | 6 ------ include/configs/cei-tk1-som.h | 6 ------ include/configs/colibri_t20.h | 6 ------ include/configs/colibri_t30.h | 2 -- include/configs/dalmore.h | 4 ---- include/configs/e2220-1170.h | 4 ---- include/configs/harmony.h | 4 ---- include/configs/jetson-tk1.h | 6 ------ include/configs/medcom-wide.h | 2 -- include/configs/nyan-big.h | 4 ---- include/configs/p2371-0000.h | 4 ---- include/configs/p2371-2180.h | 6 ------ include/configs/p2571.h | 4 ---- include/configs/p2771-0000.h | 2 -- include/configs/paz00.h | 2 -- include/configs/plutux.h | 4 ---- include/configs/seaboard.h | 2 -- include/configs/tec-ng.h | 4 ---- include/configs/tec.h | 2 -- include/configs/tegra-common.h | 6 ------ include/configs/tegra114-common.h | 14 +++++++------- include/configs/tegra124-common.h | 14 +++++++------- include/configs/tegra20-common.h | 16 ++++++++-------- include/configs/tegra210-common.h | 4 ---- include/configs/tegra30-common.h | 18 +++++++----------- include/configs/trimslice.h | 6 ------ include/configs/venice2.h | 4 ---- include/configs/ventana.h | 2 -- 34 files changed, 32 insertions(+), 143 deletions(-)

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[U-Boot] [PATCH V2] ARM: davinci: da850evm: Enable SPL_OF_CONTROL without PLATDATA
by Adam Ford 19 Feb '19

19 Feb '19

With the memory mapping giving us some more avialable RAM, this updates the da850-evm-u-boot.dtsi to include the serial port, SPI and Flash nodes along with some dependent nodes in the SPL dtb. This also removes the platform data initialization code for the serial port and SPI Flash. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- V2: Add BSS entries to omapl138_lcdk config file, untested as I have no hardware diff --git a/arch/arm/dts/da850-evm-u-boot.dtsi b/arch/arm/dts/da850-evm-u-boot.dtsi index ab1de77954..ab9368b9d3 100644 --- a/arch/arm/dts/da850-evm-u-boot.dtsi +++ b/arch/arm/dts/da850-evm-u-boot.dtsi @@ -6,6 +6,24 @@ * Copyright (C) Adam Ford */ +/ { + soc@1c00000 { + u-boot,dm-spl; + }; +}; + &flash { compatible = "m25p64", "spi-flash"; }; + +&mmc0 { + u-boot,dm-spl; +}; + +&serial2 { + u-boot,dm-spl; +}; + +&spi1 { + u-boot,dm-spl; +}; diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index b0b29b3887..e8ec553f99 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -49,33 +49,6 @@ DECLARE_GLOBAL_DATA_PTR; #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K) -#ifdef CONFIG_SPL_BUILD -#include <ns16550.h> -#include <dm/platform_data/spi_davinci.h> - -static const struct ns16550_platdata da850evm_serial = { - .base = DAVINCI_UART2_BASE, - .reg_shift = 2, - .clock = 150000000, - .fcr = UART_FCR_DEFVAL, -}; - -U_BOOT_DEVICE(da850evm_uart) = { - .name = "ns16550_serial", - .platdata = &da850evm_serial, -}; - -static const struct davinci_spi_platdata davinci_spi_data = { - .regs = (struct davinci_spi_regs *)0x01f0e000, - .num_cs = 4, -}; - -U_BOOT_DEVICE(davinci_spi) = { - .name = "davinci_spi", - .platdata = &davinci_spi_data, -}; -#endif - #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH static int get_mac_addr(u8 *addr) { diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 41dae05fb9..4b09ba10a6 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_DAVINCI=y CONFIG_SYS_TEXT_BASE=0xc1080000 CONFIG_TARGET_DA850EVM=y @@ -13,6 +14,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" CONFIG_BOOTDELAY=3 +CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set @@ -20,6 +22,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " @@ -39,10 +42,11 @@ CONFIG_CMD_DIAG=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="da850-evm" -CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y CONFIG_DM_GPIO=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 48b7c2a97a..af5ba813c2 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_DAVINCI=y CONFIG_SYS_TEXT_BASE=0xc1080000 CONFIG_TARGET_DA850EVM=y @@ -12,12 +13,14 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" CONFIG_BOOTDELAY=3 +CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb" CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y @@ -37,13 +40,15 @@ CONFIG_CMD_DIAG=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="da850-evm" -CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y CONFIG_DM_GPIO=y CONFIG_DA8XX_GPIO=y CONFIG_DM_I2C=y +CONFIG_DM_MMC=y CONFIG_NAND=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index 2002444e42..e592df1aea 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -43,6 +43,9 @@ #define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ +#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE +#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 + /* memtest start addr */ #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) -- 2.17.1

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[U-Boot] [PATCH] ARM: socfpga: Clear PL310 early in SPL
by Marek Vasut 19 Feb '19

19 Feb '19

On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux will result in stale data in PL310 L2 cache controller. Even if the L2 cache controller is disabled via the CTRL register CTRL_EN bit, those data can interfere with operation of devices using DMA, like e.g. the DWMMC controller. This can in turn cause e.g. SPL to fail reading data from SD/MMC. The obvious solution here would be to fully reset the L2 cache controller via the reset manager MPUMODRST L2 bit, however this causes bus hang even if executed entirely from L1 I-cache to avoid generating any bus traffic through the L2 cache controller. This patch thus configures and enables the L2 cache controller very early in the SPL boot process, clears the L2 cache and disables the L2 cache controller again. The reason for doing it in SPL is because we need to avoid accessing any of the potentially stale data in the L2 cache, and we are certain any of the stale data will be below the OCRAM address range. To further reduce bus traffic during the L2 cache invalidation, we enable L1 I-cache and run the invalidation code entirely out of the L1 I-cache. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Dalon Westergreen <dwesterg(a)gmail.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> --- arch/arm/mach-socfpga/spl_gen5.c | 55 ++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index ccdc661d05..12d011e681 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -63,6 +63,60 @@ u32 spl_boot_mode(const u32 boot_device) } #endif +static void socfpga_pl310_clear(void) +{ + u32 mask = 0xff, ena = 0; + + icache_enable(); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + + writel(0x111, &pl310->pl310_tag_latency_ctrl); + writel(0x121, &pl310->pl310_data_latency_ctrl); + + /* enable BRESP, instruction and data prefetch, full line of zeroes */ + setbits_le32(&pl310->pl310_aux_ctrl, + L310_AUX_CTRL_DATA_PREFETCH_MASK | + L310_AUX_CTRL_INST_PREFETCH_MASK | + L310_SHARED_ATT_OVERRIDE_ENABLE); + + /* Enable the L2 cache */ + ena = readl(&pl310->pl310_ctrl); + ena |= L2X0_CTRL_EN; + + /* + * Invalidate the PL310 L2 cache. Keep the invalidation code + * entirely in L1 I-cache to avoid any bus traffic through + * the L2. + */ + asm volatile( + ".align 5 \n" + " b 3f \n" + "1: str %1, [%4] \n" + " dsb \n" + " isb \n" + " str %0, [%2] \n" + " dsb \n" + " isb \n" + "2: ldr %0, [%2] \n" + " cmp %0, #0 \n" + " bne 2b \n" + " str %0, [%3] \n" + " dsb \n" + " isb \n" + " b 4f \n" + "3: b 1b \n" + "4: nop \n" + : "+r"(mask), "+r"(ena) + : "r"(&pl310->pl310_inv_way), + "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl) + : "memory", "cc"); + + /* Disable the L2 cache */ + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); +} + void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); @@ -85,6 +139,7 @@ void board_init_f(ulong dummy) memset(__bss_start, 0, __bss_end - __bss_start); socfpga_sdram_remap_zero(); + socfpga_pl310_clear(); debug("Freezing all I/O banks\n"); /* freeze all IO banks */ -- 2.19.2

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[U-Boot] [PATCH V2 1/2] davinci: da850evm: Move BSS to SDRAM because SRAM is full
by Adam Ford 19 Feb '19

19 Feb '19

In order to fully support SPL_OF_CONTROL, we need BSS to be a bit larger. This patch relocates BSS to SDRAM instead of SRAM which is similar to how ARMv7 boards (like OMAP2+) do it. This means two new variables are required: CONFIG_SPL_BSS_START_ADDR set to DAVINCI_DDR_EMIF_DATA_BASE CONFIG_SPL_BSS_MAX_SIZE is set to 0x1080000 which is 1 byte before the location where U-Boot will load. Signed-off-by: Adam Ford <aford173(a)gmail.com> --- V2: No Change diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index 7b5fab7756..8f04911306 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -10,6 +10,9 @@ MEMORY { .sram : ORIGIN = IMAGE_TEXT_BASE,\ LENGTH = CONFIG_SPL_MAX_FOOTPRINT } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) ENTRY(_start) @@ -42,6 +45,15 @@ SECTIONS __rel_dyn_end = .; } >.sram + __image_copy_end = .; + + .end : + { + *(.__end) + } + + _image_binary_end = .; + .bss : { . = ALIGN(4); @@ -49,12 +61,5 @@ SECTIONS *(.bss*) . = ALIGN(4); __bss_end = .; - } >.sram - - __image_copy_end = .; - - .end : - { - *(.__end) - } + } >.sdram } diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 14a3046f19..bb549e363a 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -48,7 +48,8 @@ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ - +#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE +#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 /* memtest start addr */ #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) -- 2.17.1

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[U-Boot] [PATCH 0/4] Random small sunxi fixes
by megous＠megous.com 19 Feb '19

19 Feb '19

From: Ondrej Jirman <megous(a)megous.com> Patch 1 and 2 are fixes for compilation failures with disabled network support on sunxi platform. Patch 3 is a fix for error path bug in decode_timing_property(), I've found while debugging a missing LCD panel output. Patch 4 is typo fix. regards, Ondřej Jirman Ondrej Jirman (4): sunxi: Fix build when CONFIG_CMD_NET is disabled sunxi: Fix build when CONFIG_CMD_PXE or CONFIG_CMD_DHCP are disabled lib: decode_timing_property should return -NOENT when proprty is not found power: axp818: Fix typo in axp_set_dldo board/sunxi/board.c | 7 ++++++- drivers/power/axp818.c | 2 +- include/configs/sunxi-common.h | 16 ++++++++++++++-- lib/fdtdec.c | 2 +- 4 files changed, 22 insertions(+), 5 deletions(-) -- 2.20.1

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[U-Boot] [PATCH V2] ARM: rmobile: Convert Gen2 Stout, Porter, Silk to DM_SPI{, _FLASH}
by Marek Vasut 19 Feb '19

19 Feb '19

Enable DM_SPI and DM_SPI_FLASH in U-Boot on H2 Stout, M2W Porter and E3 Silk. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- V2: Disable DM_SPI and DM_SPI_FLASH in SPL to save space --- configs/porter_defconfig | 2 ++ configs/silk_defconfig | 2 ++ configs/stout_defconfig | 2 ++ include/configs/rcar-gen2-common.h | 2 ++ 4 files changed, 8 insertions(+) diff --git a/configs/porter_defconfig b/configs/porter_defconfig index ce309b6d86..826f78bb42 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -62,6 +62,7 @@ CONFIG_DM_MMC=y CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_MTD_DEVICE=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y @@ -79,6 +80,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_SH_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 0291a7c981..09196d7bb8 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -64,6 +64,7 @@ CONFIG_SH_MMCIF=y CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_MTD_DEVICE=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y @@ -81,6 +82,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_SH_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index 1c92cb6117..552cf55df5 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -62,6 +62,7 @@ CONFIG_DM_MMC=y CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_MTD_DEVICE=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y @@ -79,6 +80,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_SH_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index d606da8b0e..9213d33e21 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -53,6 +53,8 @@ /* SF MTD */ #if defined(CONFIG_SPI_FLASH_MTD) && !defined(CONFIG_SPL_BUILD) #else +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH #undef CONFIG_SPI_FLASH_MTD #endif -- 2.19.2

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[U-Boot] [PATCH v5 00/15] SiFive FU540 Support
by Anup Patel 19 Feb '19

19 Feb '19

This patchset adds SiFive Freedom Unleashed (FU540) support to RISC-V U-Boot. The patches are based upon latest RISC-V U-Boot tree (git://git.denx.de/u-boot-riscv.git) at commit id 91882c472d8c0aef4db699d3f2de55bf43d4ae4b All drivers namely: SiFive PRCI, SiFive Serial, and Cadance MACB Ethernet work fine on actual SiFive Unleashed board and QEMU sifive_u machine. Changes since v4: - Removed #ifndef from macb_enable_clk() in PATCH7 - Updated test/dm/clk.c in PATCH10 to test fixed factor clock using sandbox Changes since v3: - Added patch to un-ignore arch/riscv/include/asm/arch - Added patch to fix mrproper make target to only remove arch/*/include/asm/arch paths which are symlinks - Added patch to have place-holder asm/arch/clk.h for RISC-V - Removed "#ifndef CONFIG_RISCV" from macb clk API patch Changes since v2: - Fixed typo in PATCH3 comments - Removed "#if" from clk_fixed_factor_ofdata_to_platdata() in PATCH7 - Added PATCH12 for SiFive FU540 README guide Changes since v1: - Re-ordered SoB in patches with multiple SoB - Simplified board_get_usable_ram_top() added by PATCH3 Anup Patel (10): .gitignore: Don't ignore arch/riscv/include/asm/arch Makefile: Fix mrproper make target riscv: Rename cpu/qemu to cpu/generic riscv: Add asm/dma-mapping.h for DMA mappings riscv: Add place-holder asm/arch/clk.h for driver compilation riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems net: macb: Fix clk API usage for RISC-V systems clk: Add SiFive FU540 PRCI clock driver clk: Add fixed-factor clock driver riscv: Add SiFive FU540 board support Atish Patra (5): net: macb: Fix GEM hardware detection drivers: serial_sifive: Fix baud rate calculation drivers: serial_sifive: Skip baudrate config if no input clock cpu: Bind timer driver for boot hart doc: Add a readme guide for SiFive FU540 Makefile | 2 +- arch/.gitignore | 1 + arch/riscv/Kconfig | 6 +- arch/riscv/cpu/{qemu => generic}/Kconfig | 2 +- arch/riscv/cpu/{qemu => generic}/Makefile | 0 arch/riscv/cpu/{qemu => generic}/cpu.c | 0 arch/riscv/cpu/generic/dram.c | 37 ++ arch/riscv/cpu/qemu/dram.c | 17 - arch/riscv/include/asm/arch/clk.h | 14 + arch/riscv/include/asm/dma-mapping.h | 38 ++ arch/sandbox/dts/test.dts | 8 + board/emulation/qemu-riscv/Kconfig | 4 +- .../qemu-riscv => sifive/fu540}/Kconfig | 36 +- board/sifive/fu540/MAINTAINERS | 9 + board/sifive/fu540/Makefile | 5 + board/sifive/fu540/fu540.c | 17 + configs/sifive_fu540_defconfig | 11 + doc/README.sifive-fu540 | 302 +++++++++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 5 +- drivers/clk/clk_fixed_factor.c | 72 +++ drivers/clk/sifive/Kconfig | 19 + drivers/clk/sifive/Makefile | 5 + .../clk/sifive/analogbits-wrpll-cln28hpc.h | 101 +++ drivers/clk/sifive/fu540-prci.c | 604 ++++++++++++++++++ drivers/clk/sifive/wrpll-cln28hpc.c | 390 +++++++++++ drivers/cpu/riscv_cpu.c | 7 +- drivers/net/macb.c | 11 +- drivers/serial/serial_sifive.c | 60 +- include/configs/sifive-fu540.h | 43 ++ include/dt-bindings/clk/sifive-fu540-prci.h | 29 + test/dm/clk.c | 5 +- 32 files changed, 1794 insertions(+), 67 deletions(-) rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%) rename arch/riscv/cpu/{qemu => generic}/Makefile (100%) rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%) create mode 100644 arch/riscv/cpu/generic/dram.c delete mode 100644 arch/riscv/cpu/qemu/dram.c create mode 100644 arch/riscv/include/asm/arch/clk.h create mode 100644 arch/riscv/include/asm/dma-mapping.h copy board/{emulation/qemu-riscv => sifive/fu540}/Kconfig (57%) create mode 100644 board/sifive/fu540/MAINTAINERS create mode 100644 board/sifive/fu540/Makefile create mode 100644 board/sifive/fu540/fu540.c create mode 100644 configs/sifive_fu540_defconfig create mode 100644 doc/README.sifive-fu540 create mode 100644 drivers/clk/clk_fixed_factor.c create mode 100644 drivers/clk/sifive/Kconfig create mode 100644 drivers/clk/sifive/Makefile create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h create mode 100644 drivers/clk/sifive/fu540-prci.c create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c create mode 100644 include/configs/sifive-fu540.h create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h -- 2.17.1

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[U-Boot] [PATCH] fs: ext4: Unmount FS in do_fs_type()
by Marek Vasut 19 Feb '19

19 Feb '19

Unlike other generic FS accessors, fs_get_info() does not call fs_close() at the end of it's operation. Thus, using fs_get_info() in do_fs_type() without calling fs_close() causes potential memory leak by creating new filesystem structures on each call of do_fs_type(). The test case to trigger this problem is as follows. It is required to have ext4 filesystem on the first partition of the SDMMC device, since ext4 requires stateful mount and causes memory allocation. => while true ; do mmc rescan ; fstype mmc 1 ; done Eventually, the mounting of ext4 will fail due to malloc failures and the filesystem will not be correctly detected. This patch fixes the problem by adding the missing fs_close(). Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> --- fs/fs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/fs.c b/fs/fs.c index 0e9c2f1062..c5c35ebf5f 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -801,6 +801,8 @@ int do_fs_type(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) else printf("%s\n", info->name); + fs_close(); + return CMD_RET_SUCCESS; } -- 2.19.2

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[U-Boot] [PATCH] arm: fix hvc call
by Ibai Erkiaga 19 Feb '19

19 Feb '19

HVC call makes use of 6 arguments rather than 7 in the same way as SMC calls. The 7th argument is optional for both HVC and SMC but is implemented as 16-bit parameter and register R7 or W7. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza(a)xilinx.com> --- The issue does not report any error in a normal build as hvc_call is not used at all and is optimized by the compiler. Using -O0 triggers the error so the patch is intended to fix issues on a ongoing effor to build U-Boot with -O0. arch/arm/cpu/armv8/fwcall.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c index 9957c29..b0aca1b 100644 --- a/arch/arm/cpu/armv8/fwcall.c +++ b/arch/arm/cpu/armv8/fwcall.c @@ -28,7 +28,6 @@ static void hvc_call(struct pt_regs *args) "ldr x4, %4\n" "ldr x5, %5\n" "ldr x6, %6\n" - "ldr x7, %7\n" "hvc #0\n" "str x0, %0\n" "str x1, %1\n" @@ -37,7 +36,7 @@ static void hvc_call(struct pt_regs *args) : "+m" (args->regs[0]), "+m" (args->regs[1]), "+m" (args->regs[2]), "+m" (args->regs[3]) : "m" (args->regs[4]), "m" (args->regs[5]), - "m" (args->regs[6]), "m" (args->regs[7]) + "m" (args->regs[6]) : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17"); -- 1.8.3.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

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[U-Boot] i.MX HAB: U-Boot loading from SPI NOR flash
by Fernando AE 19 Feb '19

19 Feb '19

Hello all, I'm trying to make the High Assurance Boot (HAB) work in an iMX6UL-based board. Here is the context of my experiment: 0) Reference documentation: [1] Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using HABv4, Document Number: AN4581, Rev. 2 , 05/2018 [2] i.MX 6UltraLite Applications Processor Reference Manual, Document Number: IMX6ULRM Rev. 1, 04/2016 1) i.MX6UL-based board 2) Fuses set to boot from "Serial ROM though SPI", in reality there is a NOR flash there 3) Compiled/tried NXP U-Boot 2017.03 and 2018.03 with CONFIG_SECURE_BOOT=y 4) Both versions boot properly, I can use themselves to reflash and iterate a new U-Boot in NOR Flash As far I've understood, the ROM code loads the first 4KB in SRAM to first check the U-Boot header values, [2] 8.5.4.2 ECSPI Boot. If the header is ok, the whole U-Boot image in copied from NOR SPI to "application destination". **First question**: I assume that some code in the first 4KB have to be executed in order to turn on the external DRAM, otherwise the ROM code could not copy data to the "application destination". With this assumption, I cannot understand how the HAB can check the signature of the whole U-Boot image before running any code inside it. **Second question**: Basically what I need to know is what address should I tell HAB to start checking the signature. In the application note [1], the address is set to the DRAM (external bus). Thanks for your help, Fernando

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