February 2019 - U-Boot

[U-Boot] [PATCH] ARM: at91: Apply PMECC header for NAND_BOOT only
by Derald D. Woods 18 Feb '19

18 Feb '19

This commit guards against applying the PMECC header in a non-NAND_BOOT scenario. This a modified version of a previous patch found here: https://patchwork.ozlabs.org/patch/1009885/ Now that SPL_GENERATE_ATMEL_PMECC_HEADER has been converted to Kconfig, this provides an additional guard for building and using the 'atmel_pmecc_params' tool. Signed-off-by: Derald D. Woods <woods.technical(a)gmail.com> --- scripts/Makefile.spl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 9d5921606e..8732479f39 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -177,10 +177,12 @@ ifeq ($(CONFIG_SYS_SOC),"at91") MKIMAGEFLAGS_boot.bin = -T atmelimage ifeq ($(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER),y) +ifeq ($(CONFIG_NAND_BOOT),y) MKIMAGEFLAGS_boot.bin += -n $(shell $(obj)/../tools/atmel_pmecc_params) boot.bin: $(obj)/../tools/atmel_pmecc_params endif +endif boot.bin: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) -- 2.20.1

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[U-Boot] [PATCH 0/2] efi_loader: rework loading (continued)
by AKASHI Takahiro 18 Feb '19

18 Feb '19

Heinrich, I like your patch[1], but the resulting code looks a bit sloppy. Can you add those patches to yours? Then, I will rework my own "run -e" patch[2] on top of them. [1] https://lists.denx.de/pipermail/u-boot/2019-February/358042.html [2] https://lists.denx.de/pipermail/u-boot/2019-January/354611.html AKASHI Takahiro (2): cmd: bootefi: move bootefi_test_prepare() forward cmd: bootefi: rework do_bootefi() cmd/bootefi.c | 186 +++++++++++++++++++++++++------------------------- 1 file changed, 94 insertions(+), 92 deletions(-) -- 2.19.1

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[U-Boot] PMIC initialization
by Jeroen van der Laan 17 Feb '19

17 Feb '19

Hi there, I'm working on a board that is based on a i.Mx6soloX it has a PFUZE3000 PMIC the u-boot version we're using is 2016-03. The PMIC is by default configured with a voltage for our DRAM that is too low. We've discovered that this is an issue with some boards some of the time. The voltage is just below the bare minimum so I think the board has no big issue most of the time. I want to adjust the voltage in u-boot in time for the board bring up. I'm afraid that a lot of issues will disappear but our tests will not cover if the initialization is too late. I want to be absolutely certain that it happens on time before the memory initialization. what is the place to do this? Should I use an SPL bootloader? Is power_init_board soon enough, or does code in this place require RAM? Are there any other options? Best regards, Jeroen van der Laan [ICT zorgt voor mensen]<https://www.zorg-en-ict.nl/default.aspx> Dit e-mailbericht is uitsluitend bestemd voor de geadresseerde. Als dit bericht niet voor u bestemd is, wordt u vriendelijk verzocht dit aan de afzender te melden. Van Breda BV staat door de elektronische verzending van dit bericht niet in voor de juiste en volledige overbrenging van de inhoud, noch voor tijdige ontvangst daarvan. Voor informatie over Van Breda BV raadpleegt u www.vanbreda.nl<http://www.vanbreda.nl>. This e-mail is intended for the addressee's eyes only. If you are not the intended recipient, you are hereby kindly requested to inform the sender of this. In view of the electronic nature of this communication, Van Breda BV is neither liable for the proper and complete transmission of the information contained therein nor for any delay in its receipt. For information about Van Breda BV, please visit www.vanbreda.nl<http://www.vanbreda.nl>.

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[U-Boot] [PATCH v2 0/9] arm: exynos: Fix reboot on Odroid HC1
by Krzysztof Kozlowski 17 Feb '19

17 Feb '19

Hi, Changes since v1 ================ 1. Move fixes to beginning of patchset. 2. Patch 3: Rework the idea - split revision detection to be executed later. 3. Patch 4: New patch. 4. Patch 6: Apply Simon's comments. 5. Patch 6: Do not delay when changing voltage if regulator is disabled. 6. Patch 6: Do not delay when disabling the regulator. Description =========== Odroid HC1 does not reboot properly (at least from SD card but I do not expect difference on eMMC), if LDO4/VDD_ADC was turned off by Linux kernel. This condition happens so far always, because Linux kernel did not enable ADC on Odroid HC1, therefore the VDD_ADC regulator was turned off as unused. The issue is in detection of revision which later is used to load proper DTB. The revision is obtained by ADC read of a voltage depending on VDD_ADC. Therefore: 1. VDD_ADC has to be turned on (but board detection happens before power is initialized), 2. Turning VDD_ADC should wait with ramp delay, 3. Reading the value from ADC should wait for it to stabilize. Tested on Odroid XU3-Lite and Odroid HC1. Commends and testing are welcomed. Best regards, Krzysztof Krzysztof Kozlowski (9): adc: exynos-adc: Fix wrong bit operation used to stop the ADC power: regulator: s2mps11: Fix step for LDO27 and LDO35 arm: exynos: Detect revision later, when all resources are ready arm: exynos: odroid-xu3: Display info late to have proper type arm: exynos: Wait till ADC stabilizes before checking Odroid HC1 revision regulator: Add support for ramp delay power: regulator: s2mps11: Add enable delay arm: dts: exynos: Add supply for ADC block to Odroid XU3 family arm: dts: exynos: Add ramp delay property to LDO regulators to Odroid XU3 family arch/arm/dts/exynos5422-odroidxu3.dts | 20 +++++++ board/samsung/common/board.c | 15 ++++- board/samsung/common/exynos5-dt-types.c | 58 +++++++++++++++++-- board/samsung/odroid/odroid.c | 8 +++ configs/odroid-xu3_defconfig | 2 + .../regulator/regulator.txt | 2 + drivers/adc/exynos-adc.c | 2 +- drivers/power/regulator/regulator-uclass.c | 47 ++++++++++++++- drivers/power/regulator/s2mps11_regulator.c | 13 ++++- include/power/regulator.h | 2 + include/samsung/misc.h | 1 + 11 files changed, 160 insertions(+), 10 deletions(-) -- 2.17.1

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[U-Boot] [PATCH] riscv: fu540: enable SMP
by Lukas Auer 17 Feb '19

17 Feb '19

Hart 0 on the SiFive FU540 is meant for monitoring tasks. It is a E51 core, whereas all other cores are U54 cores. Select hart 1 as the main hart to run U-Boot. Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> --- This patch depends on the SMP support [1] and the SiFive FU540 support patch series [2]. I have submitted it independently from the SMP support patch series to allow the series to be merged independently from the SiFive FU540 support patch series. [1]: https://patchwork.ozlabs.org/project/uboot/list/?series=91320 [2]: https://patchwork.ozlabs.org/project/uboot/list/?series=91125 board/sifive/fu540/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig index 6be3d88144..d8a6020cf8 100644 --- a/board/sifive/fu540/Kconfig +++ b/board/sifive/fu540/Kconfig @@ -16,6 +16,9 @@ config SYS_TEXT_BASE default 0x80000000 if !RISCV_SMODE default 0x80200000 if RISCV_SMODE +config MAIN_HART + default 1 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select GENERIC_RISCV @@ -38,5 +41,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply PHY_LIB imply PHY_MSCC imply SIFIVE_SERIAL + imply SMP endif -- 2.20.1

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Re: [U-Boot] [PATCH 5/7] riscv: add support for multi-hart systems
by Rick Chen 17 Feb '19

17 Feb '19

Hi Lukas > > From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] > > Sent: Tuesday, February 12, 2019 6:14 AM > > To: u-boot(a)lists.denx.de > > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer Dabbelt; > > Alexander Graf; Lukas Auer; Anup Patel; Rick Jian-Zhi Chen(陳建志); Baruch Siach; > > Stefan Roese > > Subject: [PATCH 5/7] riscv: add support for multi-hart systems > > > > On RISC-V, all harts boot independently. To be able to run on a multi-hart system, > > U-Boot must be extended with the functionality to manage all harts in the > > system. A new config option, CONFIG_MAIN_HART, is used to select the hart > > U-Boot runs on. All other harts are halted. > > U-Boot can delegate functions to them using smp_call_function(). > > > > Every hart has a valid pointer to the global data structure and a 8KiB stack by > > default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. > > > > Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > > --- > > > > arch/riscv/Kconfig | 12 +++++ > > arch/riscv/cpu/start.S | 102 ++++++++++++++++++++++++++++++++++- > > arch/riscv/include/asm/csr.h | 1 + > > 3 files changed, 114 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3a51339c4d..af8d0f8d67 > > 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -140,4 +140,16 @@ config SBI_IPI > > default y if RISCV_SMODE > > depends on SMP > > > > +config MAIN_HART > > + int "Main hart in system" > > + default 0 > > + help > > + Some SoCs include harts of various sizes, some of which might not > > + be suitable for running U-Boot. CONFIG_MAIN_HART is used to select > > + the hart U-Boot runs on. > > + > > +config STACK_SIZE_SHIFT > > + int > > + default 13 > > + > > endmenu > > diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index > > a30f6f7194..ce7230df37 100644 > > --- a/arch/riscv/cpu/start.S > > +++ b/arch/riscv/cpu/start.S > > @@ -13,6 +13,7 @@ > > #include <config.h> > > #include <common.h> > > #include <elf.h> > > +#include <asm/csr.h> > > #include <asm/encoding.h> > > #include <generated/asm-offsets.h> > > If u-boot boot from flash by itself in M-mode without any FSBL or gdb, in this case there will be no chance to assign a0. Can we add some code as below : _start: +#ifdef CONFIG_RISCV_MMODE + csrr a0, mhartid +#endif /* save hart id and dtb pointer */ mv s0, a0 mv s1, a1 How do you think about it ? Thanks Rick > > @@ -45,6 +46,23 @@ _start: > > /* mask all interrupts */ > > csrw MODE_PREFIX(ie), zero > > > > +#ifdef CONFIG_SMP > > + /* check if hart is within range */ > > + /* s0: hart id */ > > + li t0, CONFIG_NR_CPUS > > + bge s0, t0, hart_out_of_bounds_loop > > +#endif

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[U-Boot] [PATCH] ARM: imx6q_logic: Enable MTD and NAND_MXS_DT
by Adam Ford 17 Feb '19

17 Feb '19

This patch supports enabling MTD, and the corresponding CMD_MTD along with enabling the MXS NAND Controller with device tree support. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 5017e5831b..8a875a8716 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -39,6 +39,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y @@ -58,8 +59,10 @@ CONFIG_PCF8575_GPIO=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_FSL_ESDHC=y +CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y -- 2.17.1

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[U-Boot] [PATCH v3 0/3] x530: Enable watchdog
by Chris Packham 17 Feb '19

17 Feb '19

We've seen some issues with the x530 under extreme conditions where the DDR gets into a bad state. Generally this results in an application crash followed by a lock-up in u-boot. Enabling the watchdog prevents the lock up and will let the DDR training have another go. Sometimes this recovers but even a reboot loop is better than a complete lockup. Changes in v3: - new - specify timeout in milliseconds Changes in v2: - update commit message Chris Packham (3): watchdog: orion_wdt: support SPL usage watchdog: orion_wdt: take timeout value in ms arm: mvebu: x530: Enable watchdog in SPL and U-Boot arch/arm/dts/armada-385-atl-x530-u-boot.dtsi | 4 ++ board/CZ.NIC/turris_omnia/turris_omnia.c | 2 +- board/alliedtelesis/x530/x530.c | 48 ++++++++++++++++++++ configs/x530_defconfig | 5 ++ drivers/watchdog/Kconfig | 1 + drivers/watchdog/orion_wdt.c | 26 ++++++++--- 6 files changed, 78 insertions(+), 8 deletions(-) -- 2.20.1

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[U-Boot] [PATCH 00/33] x86: Add support for sound
by Simon Glass 17 Feb '19

17 Feb '19

At present no x86 boards support sound. This series adds several options: - legacy beep - Intel HDA - I2S with codec These are enabled on coreboot, link and samus, respectively. A number of related patches are included to make the above work. Simon Glass (33): log: Add a Kconfig option to set the default log level log: Add documentation for convenience functions log: Allow #define LOG_DEBUG to enable logging in a file dm: syscon: Don't require a regmap for PCI devices i2c: designware: Add error checking on init pci: Don't export pci_hose_config_device() pci: Fix comment in struct pci_child_platdata gpio: Show inactive GPIOs when explicitly requested gpio: Use case-insentive matching on the GPIO name pci: Add IDs for Intel high-definition audio sandbox: Add a note about the growing state_info struct x86: Adjust I/O macros to work on 64-bit machines x86: samus: Increase the pre-reloc memory x86: link: Increase malloc size and decrease code size x86: sandbox: pch: Add a CONFIG option for PCH sandbox: pch: Add a test for the PCH uclass pch: Add ioctl support x86: ivybridge: Add a way to get the HDA config setting sound: Mark sound_setup() as optional sound: Add uclass operations for beeping sound: Add support for Intel HDA sandbox: sound: Silence sound for testing sound: x86: link: Add sound support sound: x86: Add beeping support in i8254 sound: Add a driver for the i8254 beep x86: coreboot: Enable the beeper sound driver x86: broadwell: Add support for the ADSP x86: broadwell: Don't bother probing the PCH for pinctrl x86: broadwell: Add support for serial I/O devices x86: sound: Add support for broadwell I2S sound: Add a driver for RealTek RT5677 x86: sound: Add sound support for samus (broadwell) x86: Add sound support for samus arch/Kconfig | 2 + arch/sandbox/dts/test.dts | 5 + arch/sandbox/include/asm/state.h | 9 + arch/sandbox/include/asm/test.h | 24 + arch/x86/cpu/broadwell/Makefile | 1 + arch/x86/cpu/broadwell/adsp.c | 157 ++ arch/x86/cpu/broadwell/pch.c | 110 ++ arch/x86/cpu/broadwell/pinctrl_broadwell.c | 3 +- arch/x86/cpu/ivybridge/Kconfig | 1 + arch/x86/cpu/ivybridge/bd82x6x.c | 19 + arch/x86/cpu/ivybridge/northbridge.c | 27 + arch/x86/dts/chromebook_link.dts | 91 ++ arch/x86/dts/chromebook_samus.dts | 49 +- arch/x86/include/asm/arch-broadwell/adsp.h | 46 + arch/x86/include/asm/arch-broadwell/pch.h | 3 + arch/x86/include/asm/arch-broadwell/rcb.h | 2 + .../x86/include/asm/arch-broadwell/serialio.h | 82 + .../include/asm/arch-ivybridge/sandybridge.h | 3 + arch/x86/include/asm/i8254.h | 18 + arch/x86/include/asm/io.h | 16 +- arch/x86/lib/i8254.c | 36 +- cmd/gpio.c | 10 +- common/Kconfig | 9 + common/log.c | 2 +- configs/chromebook_link_defconfig | 5 +- configs/chromebook_samus_defconfig | 11 +- configs/coreboot_defconfig | 3 + doc/README.log | 40 + doc/device-tree-bindings/sound/intel-hda.txt | 26 + drivers/Kconfig | 2 + drivers/Makefile | 2 +- drivers/core/syscon-uclass.c | 4 + drivers/i2c/designware_i2c.c | 29 +- drivers/pch/Kconfig | 9 + drivers/pch/Makefile | 1 + drivers/pch/pch-uclass.c | 10 + drivers/pch/sandbox_pch.c | 86 + drivers/pci/pci.c | 7 +- drivers/sound/Kconfig | 40 + drivers/sound/Makefile | 5 + drivers/sound/broadwell_i2s.c | 306 ++++ drivers/sound/broadwell_i2s.h | 301 ++++ drivers/sound/broadwell_sound.c | 65 + drivers/sound/hda_codec.c | 545 +++++++ drivers/sound/i8254_beep.c | 38 + drivers/sound/ivybridge_sound.c | 137 ++ drivers/sound/rt5677.c | 334 ++++ drivers/sound/rt5677.h | 1428 +++++++++++++++++ drivers/sound/sandbox.c | 69 +- drivers/sound/sound-uclass.c | 36 +- include/dt-bindings/sound/azalia.h | 29 + include/hda_codec.h | 103 ++ include/log.h | 7 +- include/pch.h | 51 +- include/pci.h | 8 +- include/pci_ids.h | 4 + include/sound.h | 46 +- test/dm/Makefile | 1 + test/dm/pch.c | 55 + test/dm/sound.c | 21 + 60 files changed, 4531 insertions(+), 58 deletions(-) create mode 100644 arch/x86/cpu/broadwell/adsp.c create mode 100644 arch/x86/include/asm/arch-broadwell/adsp.h create mode 100644 arch/x86/include/asm/arch-broadwell/serialio.h create mode 100644 doc/device-tree-bindings/sound/intel-hda.txt create mode 100644 drivers/pch/Kconfig create mode 100644 drivers/pch/sandbox_pch.c create mode 100644 drivers/sound/broadwell_i2s.c create mode 100644 drivers/sound/broadwell_i2s.h create mode 100644 drivers/sound/broadwell_sound.c create mode 100644 drivers/sound/hda_codec.c create mode 100644 drivers/sound/i8254_beep.c create mode 100644 drivers/sound/ivybridge_sound.c create mode 100644 drivers/sound/rt5677.c create mode 100644 drivers/sound/rt5677.h create mode 100644 include/dt-bindings/sound/azalia.h create mode 100644 include/hda_codec.h create mode 100644 test/dm/pch.c -- 2.20.1.321.g9e740568ce-goog

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[U-Boot] [PATCH v2 1/1] configs: rk3288: Tinker Board SPL file must fit into 32 KiB
by Heinrich Schuchardt 17 Feb '19

17 Feb '19

The SPL image for the Tinker Board has to fit into 32 KiB. This includes 4 KiB for the device tree and up to 2 KiB for the file header. A new configuration variable CONFIG_SPL_WITH_DTB_SIZE_LIMIT is introduced to define the board specific limit. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- v2 Instead of using CONFIG_SPL_MAX_SIZE with an estimate of the FDT size introduce a new test in scripts/Makefile.spl. --- Kconfig | 8 ++++++++ configs/tinker-rk3288_defconfig | 1 + scripts/Makefile.spl | 16 ++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/Kconfig b/Kconfig index 512c7beb89..7cce53da74 100644 --- a/Kconfig +++ b/Kconfig @@ -172,6 +172,14 @@ config TPL_SYS_MALLOC_F_LEN particular needs this to operate, so that it can allocate the initial serial device and any others that are needed. +config SPL_WITH_DTB_SIZE_LIMIT + int "Maximum size of SPL image including device tree" + depends on SPL + default 0 + help + Specifies the maximum length of the U-Boot SPL image including the + device tree. If this value is zero, it is ignored. + menuconfig EXPERT bool "Configure standard U-Boot features (expert users)" default y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index fdcab28185..cc5e59bcf1 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y +CONFIG_SPL_WITH_DTB_SIZE_LIMIT=32700 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y CONFIG_TARGET_TINKER_RK3288=y CONFIG_DEBUG_UART_BASE=0xff690000 diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 9d5921606e..afc329a410 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -254,11 +254,27 @@ FINAL_DTB_CONTAINER = $(obj)/$(SPL_BIN).multidtb.fit endif +ifneq ($(CONFIG_SPL_WITH_DTB_SIZE_LIMIT),0) +SPL_WITH_DTB_SIZE_CHECK = \ + @actual=`wc -c $@ | awk '{print $$1}'`; \ + limit=`printf "%d" $(CONFIG_SPL_WITH_DTB_SIZE_LIMIT)`; \ + if test $$actual -gt $$limit; then \ + echo "$@ exceeds file size limit:" >&2 ; \ + echo " limit: $$limit bytes" >&2 ; \ + echo " actual: $$actual bytes" >&2 ; \ + echo " excess: $$((actual - limit)) bytes" >&2; \ + exit 1; \ + fi +else +SPL_WITH_DTB_SIZE_CHECK = +endif + ifeq ($(CONFIG_$(SPL_TPL_)OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy) $(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \ $(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \ $(FINAL_DTB_CONTAINER) FORCE $(call if_changed,cat) + $(SPL_WITH_DTB_SIZE_CHECK) $(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN)-dtb.bin FORCE $(call if_changed,copy) -- 2.20.1

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