November 2019 - U-Boot

[U-Boot] [PATCH v2 00/10] rockchip: rk3399: Add fastboot support
by Jagan Teki 23 Nov '19

23 Nov '19

This is v2 set for fastboot support on rk3399, tested on rock960 and rebased on u-boot-rockchip/master Changes for v2: - collect Levin Du Tested-by - fix rk3399 product number (Thanks to Levin Du) - add patch to fix fastboot flash device num for rk3328 - add patch to enable gadget on rock960 - rebased on u-boot-rockchip/master [1] https://patchwork.ozlabs.org/cover/1181569/ Any inputs? Jagan. Jagan Teki (10): gadget: Select USB_GADGET_MANUFACTURER for rockchip gadget: Select USB_GADGET_VENDOR_NUM for rockchip gadget: rockchip: USB_GADGET_PRODUCT_NUM gadget: rockchip: Add rk3128 USB_GADGET_PRODUCT_NUM fastboot: rockchip: Select FASTBOOT_FLASH[_MMC_DEV] fastboot: rockchip: Fix rk3328 default mmc device usb: dwc3: Add phy interface for dwc3_uboot gadget: rockchip: Add rk3399 USB_GADGET_PRODUCT_NUM rockchip: Setup dwc3_device (for non-dm gadgets) rock960: Enable USB Gadget arch/arm/mach-rockchip/board.c | 32 +++++++++++++++++++++++++++++-- configs/elgin-rv1108_defconfig | 2 -- configs/evb-rk3036_defconfig | 5 ----- configs/evb-rk3128_defconfig | 2 -- configs/evb-rk3229_defconfig | 5 ----- configs/evb-rk3288_defconfig | 5 ----- configs/evb-rk3328_defconfig | 5 ----- configs/evb-rv1108_defconfig | 2 -- configs/firefly-rk3288_defconfig | 5 ----- configs/kylin-rk3036_defconfig | 5 ----- configs/miqi-rk3288_defconfig | 5 ----- configs/phycore-rk3288_defconfig | 5 ----- configs/popmetal-rk3288_defconfig | 5 ----- configs/rock2_defconfig | 2 -- configs/rock64-rk3328_defconfig | 5 ----- configs/rock960-rk3399_defconfig | 2 ++ configs/tinker-rk3288_defconfig | 5 ----- configs/tinker-s-rk3288_defconfig | 5 ----- configs/vyasa-rk3288_defconfig | 3 --- drivers/fastboot/Kconfig | 3 ++- drivers/usb/dwc3/core.c | 27 ++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 12 ++++++++++++ drivers/usb/gadget/Kconfig | 7 +++++++ include/dwc3-uboot.h | 2 ++ include/linux/usb/phy.h | 19 ++++++++++++++++++ 25 files changed, 101 insertions(+), 74 deletions(-) create mode 100644 include/linux/usb/phy.h -- 2.18.0.321.gffc6fa0e3

3 22

[U-Boot] [PATCH 1/4] arm64: dts: sync Allwinner H6 files
by Andre Heider 23 Nov '19

23 Nov '19

Taken from the kernel tag v5.4-rc8. Drop the /omit-if-no-ref/ keyword as it's not supported by u-boot. Signed-off-by: Andre Heider <a.heider(a)gmail.com> --- arch/arm/dts/sun50i-h6-beelink-gs1.dts | 27 +++++ arch/arm/dts/sun50i-h6-orangepi.dtsi | 4 + arch/arm/dts/sun50i-h6-pine-h64.dts | 4 + arch/arm/dts/sun50i-h6.dtsi | 137 ++++++++++++++++++++++--- 4 files changed, 155 insertions(+), 17 deletions(-) diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts index 0dc33c90dd..1d05d57014 100644 --- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -25,6 +25,7 @@ connector { compatible = "hdmi-connector"; type = "a"; + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */ port { hdmi_con_in: endpoint { @@ -51,6 +52,24 @@ regulator-max-microvolt = <5000000>; regulator-always-on; }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "sun50i-h6-spdif"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; }; &de { @@ -232,6 +251,10 @@ }; }; +&r_ir { + status = "okay"; +}; + &r_pio { /* * PL0 and PL1 are used for PMIC I2C @@ -243,6 +266,10 @@ vcc-pm-supply = <&reg_aldo1>; }; +&spdif { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi index 62e27948a3..ec9b6a578e 100644 --- a/arch/arm/dts/sun50i-h6-orangepi.dtsi +++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi @@ -189,6 +189,10 @@ }; }; +&r_ir { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_ph_pins>; diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts index 1898345183..30102daf83 100644 --- a/arch/arm/dts/sun50i-h6-pine-h64.dts +++ b/arch/arm/dts/sun50i-h6-pine-h64.dts @@ -255,6 +255,10 @@ }; }; +&r_ir { + status = "okay"; +}; + &r_pio { vcc-pm-supply = <&reg_aldo1>; }; diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi index a117f479ae..bdba221a67 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -56,14 +56,6 @@ status = "disabled"; }; - iosc: internal-osc-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <16000000>; - clock-accuracy = <300000000>; - clock-output-names = "iosc"; - }; - osc24M: osc24M_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -71,11 +63,11 @@ clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + ext_osc32k: ext_osc32k_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; - clock-output-names = "osc32k"; + clock-output-names = "ext_osc32k"; }; psci { @@ -197,7 +189,7 @@ ccu: clock@3001000 { compatible = "allwinner,sun50i-h6-ccu"; reg = <0x03001000 0x1000>; - clocks = <&osc24M>, <&osc32k>, <&iosc>; + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; clock-names = "hosc", "losc", "iosc"; #clock-cells = <1>; #reset-cells = <1>; @@ -215,7 +207,7 @@ #dma-cells = <1>; }; - sid: sid@3006000 { + sid: efuse@3006000 { compatible = "allwinner,sun50i-h6-sid"; reg = <0x03006000 0x400>; }; @@ -225,6 +217,7 @@ "allwinner,sun6i-a31-wdt"; reg = <0x030090a0 0x20>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; /* Broken on some H6 boards */ status = "disabled"; }; @@ -236,7 +229,7 @@ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -256,6 +249,21 @@ function = "hdmi"; }; + i2c0_pins: i2c0-pins { + pins = "PD25", "PD26"; + function = "i2c0"; + }; + + i2c1_pins: i2c1-pins { + pins = "PH5", "PH6"; + function = "i2c1"; + }; + + i2c2_pins: i2c2-pins { + pins = "PD23", "PD24"; + function = "i2c2"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -285,6 +293,11 @@ bias-pull-up; }; + spdif_tx_pin: spdif-tx-pin { + pins = "PH7"; + function = "spdif"; + }; + uart0_ph_pins: uart0-ph-pins { pins = "PH0", "PH1"; function = "uart0"; @@ -394,6 +407,48 @@ status = "disabled"; }; + i2c0: i2c@5002000 { + compatible = "allwinner,sun50i-h6-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002000 0x400>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@5002400 { + compatible = "allwinner,sun50i-h6-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002400 0x400>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@5002800 { + compatible = "allwinner,sun50i-h6-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x05002800 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + emac: ethernet@5020000 { compatible = "allwinner,sun50i-h6-emac", "allwinner,sun50i-a64-emac"; @@ -414,6 +469,21 @@ }; }; + spdif: spdif@5093000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-h6-spdif"; + reg = <0x05093000 0x400>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; + clock-names = "apb", "spdif"; + resets = <&ccu RST_BUS_SPDIF>; + dmas = <&dma 2>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pin>; + status = "disabled"; + }; + usb2otg: usb@5100000 { compatible = "allwinner,sun50i-h6-musb", "allwinner,sun8i-a33-musb"; @@ -480,6 +550,7 @@ resets = <&ccu RST_BUS_OHCI3>, <&ccu RST_BUS_EHCI3>; phys = <&usb2phy 3>; + phy-names = "usb"; status = "disabled"; }; @@ -491,6 +562,7 @@ <&ccu CLK_USB_OHCI3>; resets = <&ccu RST_BUS_OHCI3>; phys = <&usb2phy 3>; + phy-names = "usb"; status = "disabled"; }; @@ -507,7 +579,7 @@ resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; reset-names = "ctrl", "hdcp"; phys = <&hdmi_phy>; - phy-names = "hdmi-phy"; + phy-names = "phy"; pinctrl-names = "default"; pinctrl-0 = <&hdmi_pins>; status = "disabled"; @@ -636,10 +708,20 @@ }; }; + rtc: rtc@7000000 { + compatible = "allwinner,sun50i-h6-rtc"; + reg = <0x07000000 0x400>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clock-output-names = "osc32k", "osc32k-out", "iosc"; + clocks = <&ext_osc32k>; + #clock-cells = <1>; + }; + r_ccu: clock@7010000 { compatible = "allwinner,sun50i-h6-r-ccu"; reg = <0x07010000 0x400>; - clocks = <&osc24M>, <&osc32k>, <&iosc>, + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu CLK_PLL_PERIPH0>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; @@ -651,6 +733,7 @@ "allwinner,sun6i-a31-wdt"; reg = <0x07020400 0x20>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; }; r_intc: interrupt-controller@7021000 { @@ -667,7 +750,7 @@ reg = <0x07022000 0x400>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; clock-names = "apb", "hosc", "losc"; gpio-controller; #gpio-cells = <3>; @@ -678,10 +761,30 @@ pins = "PL0", "PL1"; function = "s_i2c"; }; + + r_ir_rx_pin: r-ir-rx-pin { + pins = "PL9"; + function = "s_cir_rx"; + }; + }; + + r_ir: ir@7040000 { + compatible = "allwinner,sun50i-h6-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x07040000 0x400>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_R_APB1_IR>, + <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_R_APB1_IR>; + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "disabled"; }; r_i2c: i2c@7081400 { - compatible = "allwinner,sun6i-a31-i2c"; + compatible = "allwinner,sun50i-h6-i2c", + "allwinner,sun6i-a31-i2c"; reg = <0x07081400 0x400>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&r_ccu CLK_R_APB2_I2C>; -- 2.24.0

3 8

[U-Boot] [PATCH v4 000/100] x86: Add initial support for apollolake
by Simon Glass 23 Nov '19

23 Nov '19

Apollo Lake is an Intel SoC generation aimed at relatively low-end embedded systems. It was released in 2016 but has become more popular recently with some embedded boards using it. This series adds support for Apollo Lake. As an example it adds an implementation of chromebook_coral (a large range of Chromebooks released in 2017). The series provides enough support to boot to a prompt. with LCD display, storage, USB, EC and keyboard. Since this is the first time U-Boot has used FSP2 there is quite a bit of refactoring needed. This series is available at u-boot-dm/coral-working Changes in v4: - Add a LOG_CATEGORY for silicon init - Add a binding file - Add a comment about the speed logic in __dw_i2c_set_bus_speed() - Add a comment for enable_bios_reset_cpl() - Add a comment in the commit message about why has_max_speed is added - Add a patch to explain of-platdata and header files - Add an extra comment to apl_uart_init() - Add comments about MRC-cache records being the same size - Add comments for exported functions - Add comments to functions - Add more documentation for pci_ofplat_get_devfn() - Add new patch to allow designware I2C driver to work in SPL - Add new patch to drop static data in designware i2c driver - Add new patch to make mrccache_update() static - Add new patch to move early-timer init later - Add support for updating power state - Add u-boot,skip-auto-config-until-reloc property to PCI - Adjust - Adjust condition for binding children - Adjust the comment for struct dw_i2c_speed_config - Allow pinctrl nodes to have subnodes (i.e. GPIO nodes) - Avoid needing to know internals of pinctrl in this driver - Change apollolake to apl - Change the behaviour to be a device-tree option - Detect zero mmio address - Disable SPL_DM_GPIO on omap35_logic to avoid a build error - Drop 'if (0)' call to deep_magic_nexgen_probe() and use #ifndef instead - Drop GPIO_NUM_PAD_CFG_REGS - Drop TCO_BASE_ADDRESS - Drop change to message about a missing uclass - Drop duplicate VBT file CONFIG - Drop duplicate commit 'Create a new sandbox_pci_read_bar() function' - Drop empty operations struct since p2sb does not need it - Drop incorrect coreboot reference from header file - Drop itss uclass change in Makefile (now in previous patch) - Drop itss uclass in Makefile - Drop pmic_pm8916 driver name and use a sandbox name instead - Drop sandbox defconfig change now that p2sb change is correct - Drop the whole interrupt file for TPL - Drop unwanted debug printf("bad\n") - Enable HAVE_VBT for FSP2 also - Enable HAVE_X86_FIT - Enable INTEL_GPIO - Enable IRQ for sandbox64 too to avoid build error - Enable option for slimbootloader, coreboot, efi - Expand commit message to better explain the need to checksum functions - Explain the 'twisty headers' comment - Explain why FSP-M cannot be shown - Fix 'enabled' typo - Fix 'what' typo - Fix FSP_M reference to refer to FSP_S in commit message - Fix Makefile copyright message - Fix alpha order in Kconfig - Fix comment for exec_sync_hwseq_xfer() - Fix comment on fsp_silicon_init() - Fix incorrect mask check in pmc_gpe_init() - Fix indentation nit - Fix up license header - Fix various code-style problems - Mention that the return value is pci_dev_t - Move code to pinctrl driver - Move this to intel_common - Name this P-Unit instead of power unit, in the commit message - New GPIO driver binding - One last desperate attempt to try to explain the purpose of this commit - Rename arch_fsp_s_preinit() to arch_fsps_preinit() - Rename get_coreboot_fsp() and add comments - Rename new file to designware_i2c_pci.c - Rename option to HAVE_SYS_TEXT_BASE - Rename pci_x86_ofplat_get_devfn() to pci_ofplat_get_devfn() - Reverse the sense of the CONFIG option - Set up LPC pads early - Split out GPIO code from the pinctrl driver - Split out into a separate patch - Split out mmio changes into a separate patch - Switch over to use pinctrl for pad init/config - Tidy up header guards - Tidy up mixed case in FSP code - Tidy up the header file a little - Update SPI flash protection only in SPL - Update commit message to indicate that CPU-identity bug is fixed - Update documentation with more detailed memory map - Update the commit message to be clearer, fix 'correct' typo - Update the message to mention the preprocessed file, not un-preprocessed - Use 'Apollo Lake' - Use BIT() macro a bit more - Use BIT() macro bit more - Use CONFIG_INTEL_CAR_CQOS to control car2.S inclusion - Use car_init_ret to return - Use existing VBT Kconfig option - Use hex for size values also - Use hyphen for device-tree properties - Use lower-case pinctrl in arch_cpu_init_dm() - Use pci_ofplat_get_devfn() - Use post_code() calls consistent with car.S - Use priv->pch instead of dev->parent - Use tabs instead of spaces - Use the new pci_ofplat_get_devfn() function - apollolake -> Apollo Lake - use GENMASK() for VTBAR_MASK Changes in v3: - Ad FSP-S support - Add CONFIG_TPL_X86_ASSUME_CPUID to reduce code size - Add Chrome OS EC support - Add FSP-S and VBT also - Add MMC, video, USB configs - Add SPL condition to the option - Add VBT signature - Add a driver for APL SPI for TPL (using of-platdata) - Add a proper SPI node and make the SPI flash node a child - Add a proper implementation of fsp_notify - Add a weak function to avoid errors on other platforms - Add an APL_SPI_FLASH_BOOT option to enable non-mmap boot - Add an extra size parameter to the find_next_mrc_cache() function - Add an fsp: tag - Add bootstage support - Add bootstage timing for memory-mapped reads - Add bootstage timing for reading vbt - Add fsp_locate_fsp to locate an fsp component - Add fspm_done() hook - Add fspm_done() hook to handle FSP-S wierdness (it breaks SPI flash) - Add help to CONFIG_FIT and don't make it 'default y' - Add more documentation - Add snapshot/restore for IRQs - Add spi alias in device tree - Add structures for FSP-S also - Add support for FSP-S component and VBT - Add support for of-platdata for TPL - Add the missing header file - Add two more defines for the CPU driver - Add two more operations to IRQ - Add various minor tidy-ups - Adjust fast_spi_cache_bios_region() to avoid using SPI driver - Change Fast-SPI driver into a helper file used by ICH SPI - Change the sandbox test from ITSS to IRQ - Convert code to use hex increased of decimal - Disable the bootcommand since it does nothing useful on coral - Don't allow BOOT_FROM_FAST_SPI_FLASH with FSP-S - Don't enable SPI flash in TPL by default - Don't imply SPI flash either - Don't include write() and erase() in TPL - Drop 'a4' comment for register offset - Drop CONFIG_SPL_NET_SUPPORT - Drop VBT as we already have it elsewhere - Drop calls to x86_cpu_init_f(), x86_cpu_reinit_f() - Drop dead code - Drop patch '86: timer: Reduce timer code size in TPL on Intel CPUs' - Drop patch 'dm: core: Don't include ofnode functions with of-platdata' - Drop patch 'spi: sandbox: Add a test driver for sandbox SPI flash' - Drop patch 'spl: Allow SPL/TPL to use of-platdata without libfdt' - Drop patch 'x86: apollolake: Add definitions for the Intel Fast SPI interface' - Drop patch 'x86: timer: Set up the timer in timer_early_get_count()' - Drop struct fsp_usp_header as it is now in the API file - Drop unnecessary #else part of CONFIG_HAVE_MICROCODE - Drop unneeded Kconfig file - Drop unused code in lpc_configure_pads() - Enable video and USB3 - Expand comments for BOOT_FROM_FAST_SPI_FLASH - Fix build error when debug UART is disabled - Fix build errors in sandbox_spl, etc - Fix mixed case in GPIO defines - Fix the incorrect value of CPU_ADDR_BITS - Fix value of LPC_BC_LE - Init the p2sb before the northbridge since the latter so it can use GPIOs - Merge in patch "x86: Add support for booting from Fast SPI" - Move an additional error handling fix from a future patch - Move line related to variable-cache into the next patch - Move location of fast_spi.h header file - Move mtrr_add_request() call into this patch - Move mtrr_add_request() call to next patch - Move pad programming into the hostbridge to reduce TPL device-tree size - Move the function to a common file instead of duplicating it - Move the mrccache_get_region() change into this patch - Move write_pirq_routing_table() to avoid 64-bit build error - Only supress the 'MAC address from ROM' warning on sandbox - Reduce amount of early-pad data in TPL - Rename X86_HAS_FIT to HAVE_X86_FIT - Rename power-mgr uclass to acpi-pmc - Reorder file so that write() and erase() are together - Rework how pads configuration is defined in TPL and SPL - Rewrite commit message - Set boot_loader_tolum_size to 0 - Set the environment variables at runtime to avoid other warnings - Shorten log_msg_ret() calls since the function name is always printed - Simplify types for fsp_locate_fsp() - Support TPL without CONFIG_TPL_SPI_SUPPORT - Support TPL without CONFIG_TPL_SPI_SUPPORT (reduces code size) - Support bootstage timing - Switch mmap to use SPI instead of SPI flash - Tidy up Makefile rules to reduce duplication - Tidy up the pad settings in the device tree - Update commit message to explain why HAVE_FIT woudl be confusing - Update device type to pci_dev_t - Update example error message to better show the intended purpose - Update mrccache livetree patch to just convert to livetree - Update the 'fsp' command for FSP2, instead of disabling it - Use a macro for is-power-of-two - Use a zero-based tsc timer - Use pci_get_devfn() - Use the IRQ uclass instead of ITSS - Use the IRQ uclass instead of creating a new ITSS uclass - Use the LPSS code from a separate file Changes in v2: - Change 'queensbay' to 'baytrail' in help - Drop probe() function - Fix 'proides' typo - Fix the Kconfig condition to avoid build errors on snow - Implement set_spi_protect() - Use SPI mmap() instead of SPI flash Simon Glass (100): binman: Add a library to access binman entries dm: gpio: Allow control of GPIO uclass in SPL dm: core: Fix offset_to_ofnode() with invalid offset dm: pci: Allow delaying auto-config until after relocation dm: pci: Move pci_get_devfn() into a common file net: Move the checksum functions to lib/ i2c: designware: Tidy up PCI support i2c: designware: Avoid using static data i2c: designware: Support use in SPL x86: spi: Add helper functions for Intel Fast SPI fdt: Show the preprocessed .dts file on error board_r: Move early-timer init later RFC: sandbox: net: Suppress the MAC-address warnings Revert "RFC: sandbox: net: Suppress the MAC-address warnings" x86: timer: use a timer base of 0 x86: timer: Reduce timer code size in TPL on Intel CPUs x86: Drop unnecessary cpu code for TPL x86: Drop unnecessary interrupt code for TPL x86: power: Add an ACPI PMC uclass x86: sandbox: Add a PMC emulator and test x86: power: Add a 'pmc' command pci: Add support for p2sb uclass sandbox: Disable mmio by default in tests sandbox: Add PCI driver and test for p2sb x86: Move UCLASS_IRQ into a separate file sandbox: Add a test for IRQ x86: Define the SPL image start x86: Reduce mrccache record alignment size x86: Correct mrccache find_next_mrc_cache() calculation x86: Adjust mrccache_get_region() to use livetree x86: Adjust mrccache_get_region() to support get_mmap() x86: Add a new global_data member for the cache record x86: Tidy up error handling in mrccache_save() x86: Update mrccache to support multiple caches x86: Add mrccache support for a 'variable' cache x86: Don't export mrccache_update() x86: Move fsp_prepare_mrc_cache() to fsp1 directory x86: Set the DRAM banks to reflect real location x86: Set up the MTRR for SDRAM x86: Don't imply libfdt or SPI flash in TPL x86: Allow removal of standard PCH drivers x86: Allow interrupt to happen once x86: fsp: Make graphics support common to FSP1/2 x86: fsp: Correct wrong header inlude in fsp_support.c x86: fsp: Add FSP2 base support x86: fsp: Set up an MTRR for the graphics frame buffer x86: fsp: Add a new arch_fsp_init_r() hook x86: fsp: Allow remembering the location of FSP-S x86: fsp: Make the notify API call common x86: Don't include the BIOS emulator in TPL x86: Add an option to include a FIT x86: Add support for newer CAR schemes x86: Disable microcode section for FSP2 x86: Update the fsp command for FSP2 x86: Update .dtsi file for FSP2 x86: Add an option to control the position of U-Boot x86: Add an option to control the position of SPL x86: Add an fdtmap and image-header x86: Don't repeat microcode in U-Boot if not needed x86: Separate out U-Boot and device tree in ROM image x86: Make MSR_PKG_POWER_SKU common spi: Correct operations check in dm_spi_xfer() x86: spi: Don't enable SPI_FLASH_BAR by default spi: ich: Move init function just above probe() spi: ich: Move the protection/lockdown code into a function spi: ich: Convert to livetree spi: ich: Fix header order spi: ich: Various small tidy-ups spi: ich: Add mmio_base to struct ich_spi_platdata dm: doc: Add a note about of-platdata and header files spi: ich: Correct max-size bug in ich_spi_adjust_size() spi: ich: Support of-platdata for fast-spi spi: ich: Support hardware sequencing spi: ich: Add support for get_mmap() method spi: ich: Add TPL support spi: ich: Add Apollo Lake support mtd: spi: Export spi_flash_std_probe() x86: Enable pinctrl in SPL and TPL x86: Add low-power subsystem (lpss) support x86: Add a generic Intel pinctrl driver x86: Add a generic Intel GPIO driver x86: apl: Add basic IO addresses x86: apl: Add PMC driver x86: apl: Add UART driver x86: apl: Add pinctrl driver i2c: designware: Add Apollo Lake support x86: apl: Add systemagent driver x86: apl: Add hostbridge driver x86: apl: Add ITSS driver x86: apl: Add LPC driver x86: apl: Add PCH driver x86: apl: Add PUNIT driver x86: apl: Add SPL loaders x86: apl: Add a CPU driver x86: apl: Add SPL/TPL init x86: apl: Add P2SB driver x86: apl: Add Kconfig and Makefile x86: apl: Add FSP structures x86: apl: Add FSP support x86: Add chromebook_coral Kconfig | 9 +- arch/Kconfig | 9 +- arch/arm/include/asm/omap_gpio.h | 2 +- arch/arm/mach-at91/include/mach/at91sam9260.h | 2 +- arch/arm/mach-davinci/include/mach/gpio.h | 2 +- arch/arm/mach-omap2/am33xx/board.c | 4 +- arch/arm/mach-omap2/omap3/board.c | 2 +- arch/arm/mach-omap2/omap5/hwinit.c | 2 +- arch/sandbox/cpu/state.c | 1 + arch/sandbox/dts/sandbox.dtsi | 14 + arch/sandbox/dts/test.dts | 31 + arch/sandbox/include/asm/test.h | 2 + arch/x86/Kconfig | 93 +- arch/x86/cpu/Makefile | 3 +- arch/x86/cpu/apollolake/Kconfig | 86 ++ arch/x86/cpu/apollolake/Makefile | 26 + arch/x86/cpu/apollolake/cpu.c | 51 ++ arch/x86/cpu/apollolake/cpu_spl.c | 274 ++++++ arch/x86/cpu/apollolake/fsp_m.c | 210 +++++ arch/x86/cpu/apollolake/fsp_s.c | 664 ++++++++++++++ arch/x86/cpu/apollolake/hostbridge.c | 179 ++++ arch/x86/cpu/apollolake/itss.c | 214 +++++ arch/x86/cpu/apollolake/lpc.c | 141 +++ arch/x86/cpu/apollolake/p2sb.c | 167 ++++ arch/x86/cpu/apollolake/pch.c | 36 + arch/x86/cpu/apollolake/pmc.c | 216 +++++ arch/x86/cpu/apollolake/punit.c | 121 +++ arch/x86/cpu/apollolake/spl.c | 202 +++++ arch/x86/cpu/apollolake/systemagent.c | 19 + arch/x86/cpu/apollolake/uart.c | 141 +++ arch/x86/cpu/broadwell/sdram.c | 8 +- arch/x86/cpu/coreboot/Kconfig | 1 + arch/x86/cpu/cpu.c | 4 + arch/x86/cpu/i386/Makefile | 2 + arch/x86/cpu/i386/cpu.c | 41 +- arch/x86/cpu/intel_common/Makefile | 10 + arch/x86/cpu/intel_common/car2.S | 448 ++++++++++ arch/x86/cpu/intel_common/car2_uninit.S | 87 ++ arch/x86/cpu/intel_common/fast_spi.c | 73 ++ arch/x86/cpu/intel_common/lpss.c | 44 + arch/x86/cpu/irq.c | 13 - arch/x86/cpu/ivybridge/sdram.c | 8 +- arch/x86/cpu/quark/dram.c | 8 +- arch/x86/cpu/slimbootloader/Kconfig | 1 + arch/x86/cpu/u-boot-spl.lds | 5 +- arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebook_coral.dts | 823 ++++++++++++++++++ arch/x86/dts/u-boot.dtsi | 81 +- arch/x86/include/asm/arch-apollolake/cpu.h | 27 + .../asm/arch-apollolake/fsp/fsp_configs.h | 14 + .../asm/arch-apollolake/fsp/fsp_m_upd.h | 123 +++ .../asm/arch-apollolake/fsp/fsp_s_upd.h | 292 +++++++ .../include/asm/arch-apollolake/fsp/fsp_vpd.h | 11 + arch/x86/include/asm/arch-apollolake/gpio.h | 490 +++++++++++ arch/x86/include/asm/arch-apollolake/iomap.h | 25 + arch/x86/include/asm/arch-apollolake/itss.h | 43 + arch/x86/include/asm/arch-apollolake/lpc.h | 82 ++ arch/x86/include/asm/arch-apollolake/pch.h | 9 + arch/x86/include/asm/arch-apollolake/pm.h | 19 + .../include/asm/arch-apollolake/systemagent.h | 37 + arch/x86/include/asm/arch-apollolake/uart.h | 20 + arch/x86/include/asm/arch-broadwell/cpu.h | 1 - .../include/asm/arch-ivybridge/model_206ax.h | 1 - arch/x86/include/asm/fast_spi.h | 68 ++ arch/x86/include/asm/fsp/fsp_api.h | 24 + arch/x86/include/asm/fsp/fsp_support.h | 7 - arch/x86/include/asm/fsp1/fsp_api.h | 21 +- arch/x86/include/asm/fsp2/fsp_api.h | 63 ++ arch/x86/include/asm/fsp2/fsp_internal.h | 97 +++ arch/x86/include/asm/global_data.h | 25 +- arch/x86/include/asm/intel_pinctrl.h | 293 +++++++ arch/x86/include/asm/intel_pinctrl_defs.h | 386 ++++++++ arch/x86/include/asm/lpss.h | 36 + arch/x86/include/asm/mrccache.h | 29 +- arch/x86/include/asm/msr-index.h | 9 +- arch/x86/include/asm/processor.h | 12 +- arch/x86/include/asm/spl.h | 1 + arch/x86/lib/Makefile | 2 + arch/x86/lib/fsp/Makefile | 3 + arch/x86/lib/fsp/fsp_common.c | 20 - arch/x86/lib/fsp/fsp_dram.c | 35 +- arch/x86/lib/{fsp1 => fsp}/fsp_graphics.c | 6 +- arch/x86/lib/fsp/fsp_support.c | 2 +- arch/x86/lib/fsp1/Makefile | 1 - arch/x86/lib/fsp1/fsp_common.c | 20 + arch/x86/lib/fsp1/fsp_dram.c | 8 +- arch/x86/lib/fsp2/Makefile | 10 + arch/x86/lib/fsp2/fsp_common.c | 13 + arch/x86/lib/fsp2/fsp_dram.c | 77 ++ arch/x86/lib/fsp2/fsp_init.c | 174 ++++ arch/x86/lib/fsp2/fsp_meminit.c | 97 +++ arch/x86/lib/fsp2/fsp_silicon_init.c | 54 ++ arch/x86/lib/fsp2/fsp_support.c | 135 +++ arch/x86/lib/mrccache.c | 204 +++-- arch/x86/lib/pirq_routing.c | 10 + board/freescale/imx8qm_mek/imx8qm_mek.c | 2 +- board/freescale/imx8qxp_mek/imx8qxp_mek.c | 2 +- board/gateworks/gw_ventana/Kconfig | 3 + board/google/Kconfig | 15 + board/google/chromebook_coral/Kconfig | 43 + board/google/chromebook_coral/MAINTAINERS | 6 + board/google/chromebook_coral/Makefile | 5 + board/google/chromebook_coral/coral.c | 18 + board/toradex/apalis-imx8/apalis-imx8.c | 2 +- cmd/Kconfig | 8 + cmd/Makefile | 1 + cmd/pmc.c | 81 ++ cmd/x86/fsp.c | 65 +- common/board_r.c | 32 +- configs/chromebook_coral_defconfig | 102 +++ configs/chromebook_samus_tpl_defconfig | 1 + configs/omap35_logic_defconfig | 1 + configs/sandbox64_defconfig | 3 + configs/sandbox_defconfig | 2 + configs/sandbox_flattree_defconfig | 4 + configs/sandbox_spl_defconfig | 4 + configs/tools-only_defconfig | 2 + doc/board/google/chromebook_coral.rst | 241 +++++ .../gpio/intel,apl-gpio.txt | 55 ++ doc/device-tree-bindings/pci/x86-pci.txt | 24 + .../pinctrl/intel,apl-pinctrl.txt | 39 + doc/driver-model/of-plat.rst | 6 + drivers/Makefile | 1 + drivers/core/util.c | 20 + drivers/gpio/Kconfig | 31 + drivers/gpio/Makefile | 5 +- drivers/gpio/at91_gpio.c | 6 +- drivers/gpio/atmel_pio4.c | 2 +- drivers/gpio/da8xx_gpio.c | 7 +- drivers/gpio/da8xx_gpio.h | 2 +- drivers/gpio/intel_gpio.c | 161 ++++ drivers/gpio/mxc_gpio.c | 4 +- drivers/gpio/mxs_gpio.c | 4 +- drivers/gpio/omap_gpio.c | 6 +- drivers/gpio/sunxi_gpio.c | 8 +- drivers/i2c/Makefile | 3 + drivers/i2c/designware_i2c.c | 106 +-- drivers/i2c/designware_i2c.h | 35 + drivers/i2c/designware_i2c_pci.c | 144 +++ drivers/i2c/i2c-uclass.c | 6 +- drivers/i2c/muxes/pca954x.c | 4 +- drivers/misc/Kconfig | 42 + drivers/misc/Makefile | 5 + drivers/misc/irq-uclass.c | 53 ++ drivers/misc/irq_sandbox.c | 55 ++ drivers/misc/p2sb-uclass.c | 209 +++++ drivers/misc/p2sb_emul.c | 272 ++++++ drivers/misc/p2sb_sandbox.c | 40 + drivers/misc/sandbox_adder.c | 60 ++ drivers/mmc/fsl_esdhc_imx.c | 13 +- drivers/mmc/omap_hsmmc.c | 2 +- drivers/mtd/spi/sf_probe.c | 2 +- drivers/net/designware.c | 10 +- drivers/net/designware.h | 4 +- drivers/net/fec_mxc.c | 6 +- drivers/net/fec_mxc.h | 2 +- drivers/net/mvneta.c | 4 +- drivers/net/mvpp2.c | 8 +- drivers/net/sun8i_emac.c | 12 +- drivers/pch/Kconfig | 18 + drivers/pch/Makefile | 4 +- drivers/pci/pci-aardvark.c | 4 +- drivers/pci/pci-uclass.c | 31 +- drivers/pci/pcie_dw_mvebu.c | 4 +- drivers/pinctrl/Kconfig | 23 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/intel/Kconfig | 24 + drivers/pinctrl/intel/Makefile | 6 + drivers/pinctrl/intel/pinctrl.c | 615 +++++++++++++ drivers/pinctrl/intel/pinctrl_apl.c | 192 ++++ drivers/power/Kconfig | 2 + drivers/power/acpi_pmc/Kconfig | 34 + drivers/power/acpi_pmc/Makefile | 6 + drivers/power/acpi_pmc/acpi-pmc-uclass.c | 244 ++++++ drivers/power/acpi_pmc/pmc_emul.c | 246 ++++++ drivers/power/acpi_pmc/sandbox.c | 97 +++ drivers/spi/Kconfig | 1 - drivers/spi/atmel_spi.c | 10 +- drivers/spi/designware_spi.c | 4 +- drivers/spi/ich.c | 528 ++++++++--- drivers/spi/ich.h | 46 +- drivers/spi/spi-uclass.c | 5 +- drivers/timer/Kconfig | 23 + drivers/timer/tsc_timer.c | 10 +- drivers/tpm/tpm2_tis_spi.c | 2 +- include/binman.h | 45 + include/bootstage.h | 3 + include/config_uncmd_spl.h | 1 - include/configs/at91-sama5_common.h | 5 +- include/configs/chromebook_coral.h | 32 + include/configs/gw_ventana.h | 1 - include/configs/mx6ul_14x14_evk.h | 1 + include/dm/ofnode.h | 2 +- include/dm/pci.h | 43 + include/dm/uclass-id.h | 2 + include/init.h | 11 + include/irq.h | 88 ++ include/p2sb.h | 127 +++ include/pci.h | 21 +- include/power/acpi_pmc.h | 185 ++++ include/spi.h | 2 +- include/spi_flash.h | 12 + lib/Kconfig | 10 + lib/Makefile | 3 +- lib/binman.c | 48 + lib/efi/Kconfig | 1 + lib/net_utils.c | 48 + net/Makefile | 1 - net/checksum.c | 59 -- scripts/Makefile.lib | 4 +- scripts/Makefile.uncmd_spl | 1 - test/dm/Makefile | 3 + test/dm/irq.c | 32 + test/dm/p2sb.c | 28 + test/dm/pmc.c | 33 + 215 files changed, 12234 insertions(+), 636 deletions(-) create mode 100644 arch/x86/cpu/apollolake/Kconfig create mode 100644 arch/x86/cpu/apollolake/Makefile create mode 100644 arch/x86/cpu/apollolake/cpu.c create mode 100644 arch/x86/cpu/apollolake/cpu_spl.c create mode 100644 arch/x86/cpu/apollolake/fsp_m.c create mode 100644 arch/x86/cpu/apollolake/fsp_s.c create mode 100644 arch/x86/cpu/apollolake/hostbridge.c create mode 100644 arch/x86/cpu/apollolake/itss.c create mode 100644 arch/x86/cpu/apollolake/lpc.c create mode 100644 arch/x86/cpu/apollolake/p2sb.c create mode 100644 arch/x86/cpu/apollolake/pch.c create mode 100644 arch/x86/cpu/apollolake/pmc.c create mode 100644 arch/x86/cpu/apollolake/punit.c create mode 100644 arch/x86/cpu/apollolake/spl.c create mode 100644 arch/x86/cpu/apollolake/systemagent.c create mode 100644 arch/x86/cpu/apollolake/uart.c create mode 100644 arch/x86/cpu/intel_common/car2.S create mode 100644 arch/x86/cpu/intel_common/car2_uninit.S create mode 100644 arch/x86/cpu/intel_common/fast_spi.c create mode 100644 arch/x86/cpu/intel_common/lpss.c create mode 100644 arch/x86/dts/chromebook_coral.dts create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h create mode 100644 arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h create mode 100644 arch/x86/include/asm/arch-apollolake/gpio.h create mode 100644 arch/x86/include/asm/arch-apollolake/iomap.h create mode 100644 arch/x86/include/asm/arch-apollolake/itss.h create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h create mode 100644 arch/x86/include/asm/arch-apollolake/pch.h create mode 100644 arch/x86/include/asm/arch-apollolake/pm.h create mode 100644 arch/x86/include/asm/arch-apollolake/systemagent.h create mode 100644 arch/x86/include/asm/arch-apollolake/uart.h create mode 100644 arch/x86/include/asm/fast_spi.h create mode 100644 arch/x86/include/asm/fsp/fsp_api.h create mode 100644 arch/x86/include/asm/fsp2/fsp_api.h create mode 100644 arch/x86/include/asm/fsp2/fsp_internal.h create mode 100644 arch/x86/include/asm/intel_pinctrl.h create mode 100644 arch/x86/include/asm/intel_pinctrl_defs.h create mode 100644 arch/x86/include/asm/lpss.h rename arch/x86/lib/{fsp1 => fsp}/fsp_graphics.c (95%) create mode 100644 arch/x86/lib/fsp2/Makefile create mode 100644 arch/x86/lib/fsp2/fsp_common.c create mode 100644 arch/x86/lib/fsp2/fsp_dram.c create mode 100644 arch/x86/lib/fsp2/fsp_init.c create mode 100644 arch/x86/lib/fsp2/fsp_meminit.c create mode 100644 arch/x86/lib/fsp2/fsp_silicon_init.c create mode 100644 arch/x86/lib/fsp2/fsp_support.c create mode 100644 board/google/chromebook_coral/Kconfig create mode 100644 board/google/chromebook_coral/MAINTAINERS create mode 100644 board/google/chromebook_coral/Makefile create mode 100644 board/google/chromebook_coral/coral.c create mode 100644 cmd/pmc.c create mode 100644 configs/chromebook_coral_defconfig create mode 100644 doc/board/google/chromebook_coral.rst create mode 100644 doc/device-tree-bindings/gpio/intel,apl-gpio.txt create mode 100644 doc/device-tree-bindings/pci/x86-pci.txt create mode 100644 doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt create mode 100644 drivers/gpio/intel_gpio.c create mode 100644 drivers/i2c/designware_i2c_pci.c create mode 100644 drivers/misc/irq-uclass.c create mode 100644 drivers/misc/irq_sandbox.c create mode 100644 drivers/misc/p2sb-uclass.c create mode 100644 drivers/misc/p2sb_emul.c create mode 100644 drivers/misc/p2sb_sandbox.c create mode 100644 drivers/misc/sandbox_adder.c create mode 100644 drivers/pinctrl/intel/Kconfig create mode 100644 drivers/pinctrl/intel/Makefile create mode 100644 drivers/pinctrl/intel/pinctrl.c create mode 100644 drivers/pinctrl/intel/pinctrl_apl.c create mode 100644 drivers/power/acpi_pmc/Kconfig create mode 100644 drivers/power/acpi_pmc/Makefile create mode 100644 drivers/power/acpi_pmc/acpi-pmc-uclass.c create mode 100644 drivers/power/acpi_pmc/pmc_emul.c create mode 100644 drivers/power/acpi_pmc/sandbox.c create mode 100644 include/binman.h create mode 100644 include/configs/chromebook_coral.h create mode 100644 include/dm/pci.h create mode 100644 include/irq.h create mode 100644 include/p2sb.h create mode 100644 include/power/acpi_pmc.h create mode 100644 lib/binman.c delete mode 100644 net/checksum.c create mode 100644 test/dm/irq.c create mode 100644 test/dm/p2sb.c create mode 100644 test/dm/pmc.c -- 2.24.0.432.g9d3f5f5b63-goog

3 103

[U-Boot] [PATCH 0/3] Introduce APIs for multi PCIe host controller platforms
by Vladimir Olovyannikov 23 Nov '19

23 Nov '19

This patch set contains proposed API changes to the pci uclass for multi PCIe host controller platforms. 1. Add changes to fix bus number of a host bridge Differentiate bus numbers hierarchy for root bridges. All bus numbers are device sequence numbers minus root bridge sequence number. This way, every root bridge and its downstream EPs bus numbers start from 0. Thus, root bridges are different hierarchy of bus numbers. 2. Get next device fail with driver probe fail In Multi PCIe host controller platforms, if one PCIe host driver probe fails for any reason, the next PCIe host controller device pointer should be tried with its driver probe. Instead, currently the code simply stops enumeration. Add the feature described above. 3. Add ability to parse dma-regions given in PCIe host controller's DT node. Srinath Mannam (3): drivers: pci: Fix Host bridge bus number issue drivers: core: uclass: Get next device fail with driver probe fail drivers: pci: pci-uclass: Get PCI dma regions support drivers/core/uclass.c | 2 +- drivers/pci/pci-uclass.c | 49 +++++++++++++++++++++++++++++++++++++--- drivers/pci/pci_auto.c | 6 ++++- include/pci.h | 2 ++ 4 files changed, 54 insertions(+), 5 deletions(-) -- 2.17.1

2 6

[U-Boot] [PATCH 1/9] mmc: tmio: sdhi: Track current tap number in private data
by Marek Vasut 23 Nov '19

23 Nov '19

Retain the tap number from last calibration in private data. This will be later used for SCC error checking after each command. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- drivers/mmc/renesas-sdhi.c | 31 ++++++++++++++++--------------- drivers/mmc/tmio-common.h | 1 + 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 0cb65b480d..acc44e5b90 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -289,8 +289,7 @@ static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv) } static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, - unsigned int tap_num, unsigned int taps, - unsigned int smpcmp) + unsigned int taps, unsigned int smpcmp) { unsigned long tap_cnt; /* counter of tuning success */ unsigned long tap_start;/* start position of tuning success */ @@ -307,14 +306,14 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); /* Merge the results */ - for (i = 0; i < tap_num * 2; i++) { + for (i = 0; i < priv->tap_num * 2; i++) { if (!(taps & BIT(i))) { - taps &= ~BIT(i % tap_num); - taps &= ~BIT((i % tap_num) + tap_num); + taps &= ~BIT(i % priv->tap_num); + taps &= ~BIT((i % priv->tap_num) + priv->tap_num); } if (!(smpcmp & BIT(i))) { - smpcmp &= ~BIT(i % tap_num); - smpcmp &= ~BIT((i % tap_num) + tap_num); + smpcmp &= ~BIT(i % priv->tap_num); + smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num); } } @@ -327,7 +326,7 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, ntap = 0; tap_start = 0; tap_end = 0; - for (i = 0; i < tap_num * 2; i++) { + for (i = 0; i < priv->tap_num * 2; i++) { if (taps & BIT(i)) ntap++; else { @@ -350,12 +349,12 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, * If all of the TAP is OK, the sampling clock position is selected by * identifying the change point of data. */ - if (tap_cnt == tap_num * 2) { + if (tap_cnt == priv->tap_num * 2) { match_cnt = 0; ntap = 0; tap_start = 0; tap_end = 0; - for (i = 0; i < tap_num * 2; i++) { + for (i = 0; i < priv->tap_num * 2; i++) { if (smpcmp & BIT(i)) ntap++; else { @@ -378,7 +377,7 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, select = true; if (select) - priv->tap_set = ((tap_start + tap_end) / 2) % tap_num; + priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num; else return -EIO; @@ -419,15 +418,17 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) /* Tuning is not supported */ goto out; - if (tap_num * 2 >= sizeof(taps) * 8) { + priv->tap_num = tap_num; + + if (priv->tap_num * 2 >= sizeof(taps) * 8) { dev_err(dev, "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n"); goto out; } /* Issue CMD19 twice for each tap */ - for (i = 0; i < 2 * tap_num; i++) { - renesas_sdhi_prepare_tuning(priv, i % tap_num); + for (i = 0; i < 2 * priv->tap_num; i++) { + renesas_sdhi_prepare_tuning(priv, i % priv->tap_num); /* Force PIO for the tuning */ caps = priv->caps; @@ -447,7 +448,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) mdelay(1); } - ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp); + ret = renesas_sdhi_select_tuning(priv, taps, smpcmp); out: if (ret < 0) { diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index 51607de142..da89cc90c2 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -138,6 +138,7 @@ struct tmio_sd_priv { #endif #if CONFIG_IS_ENABLED(RENESAS_SDHI) u8 tap_set; + u8 tap_num; u8 nrtaps; bool needs_adjust_hs400; bool adjust_hs400_enable; -- 2.24.0.rc1

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[U-Boot] [PATCH V2 1/9] mmc: tmio: sdhi: Track current tap number in private data
by Marek Vasut 23 Nov '19

23 Nov '19

Retain the tap number from last calibration in private data. This will be later used for SCC error checking after each command. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Masahiro Yamada <yamada.masahiro(a)socionext.com> --- V2: Rebase on u-boot/master, no other change --- drivers/mmc/renesas-sdhi.c | 31 ++++++++++++++++--------------- drivers/mmc/tmio-common.h | 1 + 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 0cb65b480d..acc44e5b90 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -289,8 +289,7 @@ static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv) } static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, - unsigned int tap_num, unsigned int taps, - unsigned int smpcmp) + unsigned int taps, unsigned int smpcmp) { unsigned long tap_cnt; /* counter of tuning success */ unsigned long tap_start;/* start position of tuning success */ @@ -307,14 +306,14 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ); /* Merge the results */ - for (i = 0; i < tap_num * 2; i++) { + for (i = 0; i < priv->tap_num * 2; i++) { if (!(taps & BIT(i))) { - taps &= ~BIT(i % tap_num); - taps &= ~BIT((i % tap_num) + tap_num); + taps &= ~BIT(i % priv->tap_num); + taps &= ~BIT((i % priv->tap_num) + priv->tap_num); } if (!(smpcmp & BIT(i))) { - smpcmp &= ~BIT(i % tap_num); - smpcmp &= ~BIT((i % tap_num) + tap_num); + smpcmp &= ~BIT(i % priv->tap_num); + smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num); } } @@ -327,7 +326,7 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, ntap = 0; tap_start = 0; tap_end = 0; - for (i = 0; i < tap_num * 2; i++) { + for (i = 0; i < priv->tap_num * 2; i++) { if (taps & BIT(i)) ntap++; else { @@ -350,12 +349,12 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, * If all of the TAP is OK, the sampling clock position is selected by * identifying the change point of data. */ - if (tap_cnt == tap_num * 2) { + if (tap_cnt == priv->tap_num * 2) { match_cnt = 0; ntap = 0; tap_start = 0; tap_end = 0; - for (i = 0; i < tap_num * 2; i++) { + for (i = 0; i < priv->tap_num * 2; i++) { if (smpcmp & BIT(i)) ntap++; else { @@ -378,7 +377,7 @@ static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv, select = true; if (select) - priv->tap_set = ((tap_start + tap_end) / 2) % tap_num; + priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num; else return -EIO; @@ -419,15 +418,17 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) /* Tuning is not supported */ goto out; - if (tap_num * 2 >= sizeof(taps) * 8) { + priv->tap_num = tap_num; + + if (priv->tap_num * 2 >= sizeof(taps) * 8) { dev_err(dev, "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n"); goto out; } /* Issue CMD19 twice for each tap */ - for (i = 0; i < 2 * tap_num; i++) { - renesas_sdhi_prepare_tuning(priv, i % tap_num); + for (i = 0; i < 2 * priv->tap_num; i++) { + renesas_sdhi_prepare_tuning(priv, i % priv->tap_num); /* Force PIO for the tuning */ caps = priv->caps; @@ -447,7 +448,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode) mdelay(1); } - ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp); + ret = renesas_sdhi_select_tuning(priv, taps, smpcmp); out: if (ret < 0) { diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index 51607de142..da89cc90c2 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -138,6 +138,7 @@ struct tmio_sd_priv { #endif #if CONFIG_IS_ENABLED(RENESAS_SDHI) u8 tap_set; + u8 tap_num; u8 nrtaps; bool needs_adjust_hs400; bool adjust_hs400_enable; -- 2.24.0.359.ga6e4e5af0a

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[U-Boot] Memory Tests in U-Boot
by devendra.devadiga＠iwavesystems.com 23 Nov '19

23 Nov '19

Hi, In U-Boot I found some generic memory tests commands like mtest and POST tests. But I need to do complete DDR4 memory test with below algorithms: * Checkerboard Test * March C- Test * Neighborhood Pattern Sensitive Fault Can I get any reference code for these algorithms in U-Boot ? Implementation for these algorithms available in any of U-Boot version ? For Checkerboard algorithm, based on the explanation from below link (got by web search) I tried to implement https://www.design-reuse.com/articles/45915/memory-testing-self-repair-mech… Attached the file: cmd_checkerboard.c Is the implementation I did is proper ? Can you verify once? Similarly for March C- test based on explanation from these docs (got by web search) I tried to implement March C- test https://eecs.ceas.uc.edu/~jonewb/Memory.pdf http://www.ee.ncu.edu.tw/~jfli/memtest/lecture/ch03.pdf Attached the file: cmd_marchc_min.c Please can you verify once? For Active Neighborhood Pattern Sensitive Fault test, still I didn't get the proper algorithms. Can you refer me the any link or source codes for this test? Thanks and Regards, Devendra

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[U-Boot] [PATCH 1/1] drivers: mmc: rpmb: Use R1 response
by Vladimir Olovyannikov 23 Nov '19

23 Nov '19

From: Bharat Kumar Reddy Gooty <bharat.gooty(a)broadcom.com> If the host has Broken R1B, use only R1 response type. Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty(a)broadcom.com> Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov(a)broadcom.com> --- drivers/mmc/rpmb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c index 33371fe562..ee6dbe30db 100644 --- a/drivers/mmc/rpmb.c +++ b/drivers/mmc/rpmb.c @@ -11,6 +11,7 @@ #include <common.h> #include <memalign.h> #include <mmc.h> +#include <sdhci.h> #include <u-boot/sha256.h> #include "mmc_private.h" @@ -91,6 +92,7 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, { struct mmc_cmd cmd = {0}; struct mmc_data data; + struct sdhci_host *host = mmc->priv; int ret; ret = mmc_set_blockcount(mmc, count, is_rel_write); @@ -105,6 +107,9 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, cmd.cmdarg = 0; cmd.resp_type = MMC_RSP_R1; + if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) + cmd.resp_type = MMC_RSP_R1; + data.src = (const char *)s; data.blocks = 1; data.blocksize = MMC_MAX_BLOCK_LEN; -- 2.17.1

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[U-Boot] [PATCH 0/3] Extend pinctrl-single driver with APIs
by Vladimir Olovyannikov 22 Nov '19

22 Nov '19

This patch set adds APIs for pinctrl-single driver. 1. Support to use different register read/write api's based on register width. 2. pinctrl_ops->request api to configure pctrl pad register in gpio mode. 3. Parse different gpio properties from dt as part of the probe function. This is required to enable pinctrl pad. Rayagonda Kokatanur (3): pinctrl: pinctrl-single: Handle different register width pinctrl: pinctrl-single: Add request api pinctrl: pinctrl-single: Parse gpio details from dt drivers/pinctrl/pinctrl-single.c | 200 ++++++++++++++++++++++++++----- 1 file changed, 169 insertions(+), 31 deletions(-) -- 2.17.1

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[U-Boot] [PULL] u-boot-socfpga/master
by Marek Vasut 22 Nov '19

22 Nov '19

The following changes since commit 8d8ee47e03ef23b0d0e842ea455a30bf0d2023b9: env: Add CONFIG_SYS_RELOC_GD_ENV_ADDR symbol (2019-11-20 12:24:50 -0500) are available in the Git repository at: git://git.denx.de/u-boot-socfpga.git master for you to fetch changes up to 0c14bb5ad3311de2c26e66e88f8a6886773b8e0a: arm: socfpga: stratix10: Add alias for gmac0 in S10 dts (2019-11-22 03:08:12 +0100) ---------------------------------------------------------------- Ley Foon Tan (2): arm: dts: Stratix10: Fix memory node address and size cells configs: Stratix10: Disable CONFIG_SPL_USE_TINY_PRINTF Marek Vasut (1): ARM: socfpga: Fix default mtdparts Ooi, Joyce (2): arm: dts: Stratix10: change pad skew values for EMAC0 PHY driver arm: socfpga: stratix10: Add alias for gmac0 in S10 dts Simon Goldschmidt (4): ddr: socfpga: gen5: constify altera_gen5_sdram_ops socfpga: fix include guard in misc.h (arch vs. global) timer: dw-apb: add reset handling spi: cadence_qspi: support DM_CLK arch/arm/dts/socfpga_stratix10_socdk.dts | 5 ++++- arch/arm/mach-socfpga/include/mach/misc.h | 6 +++--- configs/socfpga_arria5_defconfig | 2 +- configs/socfpga_cyclone5_defconfig | 2 +- configs/socfpga_de0_nano_soc_defconfig | 2 +- configs/socfpga_is1_defconfig | 2 +- configs/socfpga_mcvevk_defconfig | 2 +- configs/socfpga_sockit_defconfig | 2 +- configs/socfpga_socrates_defconfig | 2 +- configs/socfpga_sr1500_defconfig | 2 +- configs/socfpga_stratix10_defconfig | 1 + drivers/ddr/altera/sdram_gen5.c | 2 +- drivers/spi/cadence_qspi.c | 21 +++++++++++++++++++-- drivers/spi/cadence_qspi.h | 1 + drivers/timer/dw-apb-timer.c | 18 +++++++++++++++++- 15 files changed, 54 insertions(+), 16 deletions(-)

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