November 2019 - U-Boot

[U-Boot] [PATCH v2] travis: rework NXP layerscape jobs
by Heiko Schocher 21 Nov '19

21 Nov '19

remove from NXP arm32 all layerscape boards and build them instead in already existing layerscape jobs (which now not only build aarch64 boards) Signed-off-by: Heiko Schocher <hs(a)denx.de> --- travis build: https://travis-ci.org/hsdenx/u-boot-test/builds/614396275?utm_medium=notifi… Changes in v2: - collect in the layerscape jobs not only aarch64 based boards as Tom suggested. - change subject, old was "travis: split NXP ARM32 job" .travis.yml | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/.travis.yml b/.travis.yml index f6aec96770..d5f34f96cc 100644 --- a/.travis.yml +++ b/.travis.yml @@ -183,27 +183,27 @@ matrix: - name: "buildman ARM bcm" env: - BUILDMAN="bcm -x mips" - - name: "buildman NXP ARM32" + - name: "buildman NXP ARM32 (catch-all)" env: - - BUILDMAN="freescale -x powerpc,m68k,aarch64" - - name: "buildman NXP AArch64 LS101x" + - BUILDMAN="freescale -x powerpc,m68k,aarch64,ls101,ls102,ls104,ls108,ls20,lx216" + - name: "buildman NXP LS101x" env: - - BUILDMAN="freescale&aarch64&ls101" - - name: "buildman NXP AArch64 LS102x" + - BUILDMAN="freescale&ls101" + - name: "buildman NXP LS102x" env: - - BUILDMAN="freescale&aarch64&ls102" - - name: "buildman NXP AArch64 LS104x" + - BUILDMAN="freescale&ls102" + - name: "buildman NXP LS104x" env: - - BUILDMAN="freescale&aarch64&ls104" - - name: "buildman NXP AArch64 LS108x" + - BUILDMAN="freescale&ls104" + - name: "buildman NXP LS108x" env: - - BUILDMAN="freescale&aarch64&ls108" - - name: "buildman NXP AArch64 LS20xx" + - BUILDMAN="freescale&ls108" + - name: "buildman NXP LS20xx" env: - - BUILDMAN="freescale&aarch64&ls20" - - name: "buildman NXP AArch64 LX216x" + - BUILDMAN="freescale&ls20" + - name: "buildman NXP LX216x" env: - - BUILDMAN="freescale&aarch64&lx216" + - BUILDMAN="freescale&lx216" - name: "buildman i.MX6 tqc" env: - BUILDMAN="mx6&tqc" -- 2.21.0

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[U-Boot] IO Error Propagation on Armada-385
by Chris Packham 21 Nov '19

21 Nov '19

Hi Stefan and Luka, I was wondering if you could shed some light on this commit https://gitlab.denx.de/u-boot/u-boot/commit/501c098a1f2cdaa930cb1a7166d3724… At $dayjob we're running into an issue where certain invalid PCI accesses when running Linux lead to the CPU hanging. Setting the IO Err Prop bit back to 1 seems to prevent the hang. Can you recall why u-boot needs this bit cleared? We'll probably need to make the kernel restore the setting but I'd expect the kernel maintainers to point out that we're essentially restoring the hardware default so we'd need to explain that u-boot clears it because X but the kernel needs it set. Thanks, Chris

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[U-Boot] [PATCH 0/6] J721e: Add networking support
by Vignesh Raghavendra 21 Nov '19

21 Nov '19

This patch enables networking support for TI's J721e SoC. Patch 1 adds a new interface to DMA uclass to get channel specific private/configuration data. Patch 2 to 4 use this interface to pass data from J721e's UDMA driver to CPSW ethernet driver. Last two patches add DMA and CPSW DT nodes and configs. Vignesh Raghavendra (6): dma: Introduce dma_get_cfg() interface dma: ti: k3-udma: Implement dma_get_cfg() interface net: ti: am65-cpsw-nuss: Rework RX flow ID handling net: ti: am65-cpsw-nuss: Add new compatible for J721e arm: dts: k3-j721e-common-proc-board: Add DMA and CPSW related DT nodes configs: j721e_evm_a72_defconfig: Enable DMA and Ethernet .../k3-j721e-common-proc-board-u-boot.dtsi | 268 ++++++++++++++++++ configs/j721e_evm_a72_defconfig | 8 + drivers/dma/dma-uclass.c | 12 + drivers/dma/ti/k3-udma.c | 28 ++ drivers/net/ti/am65-cpsw-nuss.c | 14 +- include/dma-uclass.h | 11 + include/dma.h | 11 + include/linux/soc/ti/ti-udma.h | 19 ++ 8 files changed, 362 insertions(+), 9 deletions(-) -- 2.24.0

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[U-Boot] [Patch v5 1/4] fsl-lsch3: Add FlexSPI address space in immap_lsch3
by Kuldeep Singh 21 Nov '19

21 Nov '19

Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> Signed-off-by: Rajat Srivastava <rajat.srivastava(a)nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- v5: Rebased to top v4: Remove unnecessary dependencies of FSPI_AHB_EN_4BYTE config arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index d46477d..d79516c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -23,7 +23,13 @@ #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#ifndef CONFIG_NXP_LSCH3_2 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) +#else +#define SYS_NXP_FSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) +#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR 0x18 +#define SYS_NXP_FSPI_LUT_BASE_ADDR 0x200 +#endif #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) #define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR #define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000) -- 2.7.4

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[U-Boot] [PATCH] ARM: socfpga: Introduce u-boot-with-nand-spl.sfp target
by Marek Vasut 21 Nov '19

21 Nov '19

The NAND devices with 128 kiB erase blocks require extra 64 kiB padding between each SPL image. Generate U-Boot image with such a padding using this new target. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dalon Westergreen <dwesterg(a)gmail.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tien Fong Chee <tien.fong.chee(a)intel.com> --- Makefile | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Makefile b/Makefile index 7485bc2594..d3038cf665 100644 --- a/Makefile +++ b/Makefile @@ -1476,6 +1476,17 @@ cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \ u-boot.img > $@ || rm -f $@ u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE $(call if_changed,socboot) + +quiet_cmd_socnandboot = SOCNANDBOOT $@ +cmd_socnandboot = dd if=/dev/zero of=spl/u-boot-spl.pad bs=64 count=1024 ; \ + cat spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + spl/u-boot-spl.sfp spl/u-boot-spl.pad \ + u-boot.img > $@ || rm -f $@ spl/u-boot-spl.pad +u-boot-with-nand-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE + $(call if_changed,socnandboot) + endif ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy) -- 2.24.0.432.g9d3f5f5b63

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[U-Boot] [PATCH 1/2] ARM: socfpga: Actually put bridges into reset on Gen5 in bridge disable
by Marek Vasut 21 Nov '19

21 Nov '19

On Gen5, the 'bridge disable' command write 0x0 to brgmodrst register, which releases all bridges from reset, instead of putting all bridges into reset. Fix this by inverting the mask and actually putting the bridges into reset. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dalon Westergreen <dwesterg(a)gmail.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tien Fong Chee <tien.fong.chee(a)intel.com> --- arch/arm/mach-socfpga/misc_gen5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 31681b799d..36f00aee31 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -231,7 +231,7 @@ void do_bridge_reset(int enable, unsigned int mask) } else { writel(0, &sysmgr_regs->fpgaintfgrp_module); writel(0, &sdr_ctrl->fpgaport_rst); - writel(0, &reset_manager_base->brg_mod_reset); + writel(0x7, &reset_manager_base->brg_mod_reset); writel(1, &nic301_regs->remap); } } -- 2.24.0.432.g9d3f5f5b63

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[U-Boot] [PATCH] ARM: socfpga: Add ArriaV ST/SX ID
by Marek Vasut 21 Nov '19

21 Nov '19

Add new FPGA ID for ArriaV ST/D3 or SX/B3 . Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Chin Liang See <chin.liang.see(a)intel.com> Cc: Dalon Westergreen <dwesterg(a)gmail.com> Cc: Dinh Nguyen <dinguyen(a)kernel.org> Cc: Ley Foon Tan <ley.foon.tan(a)intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tien Fong Chee <tien.fong.chee(a)intel.com> --- arch/arm/mach-socfpga/misc_gen5.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 65d3485bc5..22042d0de0 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -79,6 +79,8 @@ static const struct { { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" }, /* Arria V */ { 0x2d03, "Arria V, D5", "av_d5" }, + /* Arria V ST/SX */ + { 0x2d13, "Arria V, ST/D3 or SX/B3", "av_st_d3" }, }; static int socfpga_fpga_id(const bool print_id) -- 2.24.0.432.g9d3f5f5b63

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[U-Boot] [PATCH] usb: increase USB control timeout value
by Christian Gmeiner 21 Nov '19

21 Nov '19

Increase USB control timeout value to 5000 milliseconds, matching the value used in Linux kernel. This improves communication stability with some USB devices. In the concrete case a Apacer AP8GAH322B gets not deteced in a silent console configuration. Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- include/usb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/usb.h b/include/usb.h index bcad552f85..cd3f1d8225 100644 --- a/include/usb.h +++ b/include/usb.h @@ -38,7 +38,7 @@ #define USB_MAXCHILDREN 8 /* This is arbitrary */ #define USB_MAX_HUB 16 -#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */ +#define USB_CNTL_TIMEOUT 5000 /* 5000ms timeout */ /* * This is the timeout to allow for submitting an urb in ms. We allow more -- 2.23.0

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[U-Boot] [PATCH v6 00/19] Add Intel Agilex SoC support
by Ley Foon Tan 21 Nov '19

21 Nov '19

This is 6th version of patchset to add Intel Agilex SoC[1] support. Most of changes are related to use agilex-clock.h from Linux instead of using stratix10-clock.h and rebase on top of patchset in [2]. Detail changelog can find in commit message. This patchset needs to apply after patchset in [2] for manager driver struct to defines conversion and [3] for enable cache driver build in SPL. Patch status: No change: Patch 1, 2, 3, 4, 5, 6, 11, 15, 16 Have changes: Patch 7, 8, 9, 10, 13, 14, 17, 19 New: Patch 18 Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Agilex are CCU, clock manager and SDRAM, other IPs have minor changes compared to Stratix 10. Intel Agilex HPS TRM: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb… v5->v6: ------- - Patch 7: Move #include <asm/arch/clock_manager_soc64.h> to top of header file. - Patch 8: Remove unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ. - Patch 9, 10, 17: Use agilex-clock.h from Linux instead of using stratix10-clock.h. - Patch 13: Remove compatible "intel,sdr-ctl-agilex" from this patch. - Patch 14: Add compatible "intel,sdr-ctl-agilex". - Patch 19: Include socfpga_soc64_common.h. History: --------- [v1]: https://patchwork.ozlabs.org/cover/1097830/ [v2]: https://patchwork.ozlabs.org/cover/1127440/ [v3]: https://patchwork.ozlabs.org/cover/1149863/ [v4]: https://patchwork.ozlabs.org/cover/1161483/ [v5]: https://patchwork.ozlabs.org/cover/1175076/ [1]: https://www.intel.com/content/www/us/en/products/programmable/fpga/agilex.h… [2]: https://patchwork.ozlabs.org/cover/1191562/ ("arm: socfpga: Convert drivers from struct to defines") [3]: https://patchwork.ozlabs.org/patch/1191569/ ("spl: Allow cache drivers to be used in SPL") Ley Foon Tan (19): arm: socfpga: agilex: Add base address for Intel Agilex SoC arm: socfpga: Move firewall code to firewall file arm: socfpga: Move Stratix10 and Agilex reset manager common code arm: socfpga: agilex: Add reset manager support arm: socfpga: Move Stratix10 and Agilex system manager common code arm: socfpga: agilex: Add system manager support arm: socfpga: Move Stratix10 and Agilex clock manager common code arm: socfpga: Fix CLKMGR_INTOSC_HZ to 400MHz clk: agilex: Add clock driver for Agilex arm: socfpga: agilex: Add clock wrapper functions cache: Add Arteris Ncore cache coherent unit driver arm: agilex: Add clock handoff offset for Agilex ddr: altera: Restructure Stratix 10 SDRAM driver ddr: altera: agilex: Add SDRAM driver for Agilex board: intel: agilex: Add socdk board support for Intel Agilex SoC arm: socfpga: agilex: Add SPL for Agilex SoC arm: dts: agilex: Add base dtsi and devkit dts configs: socfpga: Move Stratix10 and Agilex common CONFIGs arm: socfpga: agilex: Enable Agilex SoC build arch/arm/Kconfig | 4 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex.dtsi | 500 +++++++++++++++ arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 79 +++ arch/arm/dts/socfpga_agilex_socdk.dts | 138 +++++ arch/arm/mach-socfpga/Kconfig | 16 + arch/arm/mach-socfpga/Makefile | 17 + arch/arm/mach-socfpga/clock_manager_agilex.c | 85 +++ arch/arm/mach-socfpga/clock_manager_s10.c | 3 +- .../mach-socfpga/{spl_s10.c => firewall.c} | 122 +--- .../mach-socfpga/include/mach/base_addr_s10.h | 4 + .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/clock_manager_agilex.h | 14 + .../include/mach/clock_manager_s10.h | 16 +- .../include/mach/clock_manager_soc64.h | 21 + .../mach/{firewall_s10.h => firewall.h} | 10 +- .../mach-socfpga/include/mach/handoff_s10.h | 9 +- .../mach-socfpga/include/mach/reset_manager.h | 5 +- .../include/mach/reset_manager_s10.h | 95 --- .../include/mach/reset_manager_soc64.h | 38 ++ .../include/mach/system_manager.h | 5 +- .../include/mach/system_manager_s10.h | 124 ---- .../include/mach/system_manager_soc64.h | 123 ++++ arch/arm/mach-socfpga/mailbox_s10.c | 2 +- arch/arm/mach-socfpga/misc.c | 5 + arch/arm/mach-socfpga/misc_s10.c | 2 +- arch/arm/mach-socfpga/reset_manager_s10.c | 35 +- arch/arm/mach-socfpga/spl_agilex.c | 98 +++ arch/arm/mach-socfpga/spl_s10.c | 95 +-- arch/arm/mach-socfpga/system_manager_s10.c | 26 +- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 15 +- board/intel/agilex-socdk/MAINTAINERS | 7 + board/intel/agilex-socdk/Makefile | 7 + board/intel/agilex-socdk/socfpga.c | 7 + configs/socfpga_agilex_defconfig | 58 ++ drivers/cache/Kconfig | 8 + drivers/cache/Makefile | 1 + drivers/cache/cache-ncore.c | 164 +++++ drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex.c | 579 ++++++++++++++++++ drivers/clk/altera/clk-agilex.h | 237 +++++++ drivers/ddr/altera/Kconfig | 6 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_agilex.c | 168 +++++ drivers/ddr/altera/sdram_s10.c | 298 +-------- drivers/ddr/altera/sdram_s10.h | 148 +---- drivers/ddr/altera/sdram_soc64.c | 304 +++++++++ .../ddr/altera/{sdram_s10.h => sdram_soc64.h} | 71 ++- include/configs/socfpga_agilex_socdk.h | 15 + ...ratix10_socdk.h => socfpga_soc64_common.h} | 8 +- include/configs/socfpga_stratix10_socdk.h | 202 +----- include/dt-bindings/clock/agilex-clock.h | 70 +++ 52 files changed, 2905 insertions(+), 1166 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c copy arch/arm/mach-socfpga/{spl_s10.c => firewall.c} (53%) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} (94%) delete mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h delete mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h create mode 100644 arch/arm/mach-socfpga/spl_agilex.c create mode 100644 board/intel/agilex-socdk/MAINTAINERS create mode 100644 board/intel/agilex-socdk/Makefile create mode 100644 board/intel/agilex-socdk/socfpga.c create mode 100644 configs/socfpga_agilex_defconfig create mode 100644 drivers/cache/cache-ncore.c create mode 100644 drivers/clk/altera/clk-agilex.c create mode 100644 drivers/clk/altera/clk-agilex.h create mode 100644 drivers/ddr/altera/sdram_agilex.c create mode 100644 drivers/ddr/altera/sdram_soc64.c copy drivers/ddr/altera/{sdram_s10.h => sdram_soc64.h} (79%) create mode 100644 include/configs/socfpga_agilex_socdk.h copy include/configs/{socfpga_stratix10_socdk.h => socfpga_soc64_common.h} (96%) create mode 100644 include/dt-bindings/clock/agilex-clock.h -- 2.19.0

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[U-Boot] [BUG] usb: drivers/usb/gadget/composite.c fails to build
by Heinrich Schuchardt 21 Nov '19

21 Nov '19

Hello Marek, I tried to reproduce the problem with tbs2910_defconfig but unfortunately the USB sub-system does not build at all with GCC 9.2.1. The comments in include/linux/usb/ch9.h say that the __packed attribute is needed. The problem could be solved by replacing cpu_to_le16() by a function working on byte buffers. What are your thoughts? In file included from drivers/usb/gadget/g_dnl.c:24: drivers/usb/gadget/composite.c: In function ‘get_string’: drivers/usb/gadget/composite.c:545:23: error: taking address of packed member of ‘struct usb_string_descriptor’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 545 | collect_langs(sp, s->wData); | ~^~~~~~~ drivers/usb/gadget/composite.c:550:24: error: taking address of packed member of ‘struct usb_string_descriptor’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 550 | collect_langs(sp, s->wData); | ~^~~~~~~ drivers/usb/gadget/composite.c:555:25: error: taking address of packed member of ‘struct usb_string_descriptor’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 555 | collect_langs(sp, s->wData); | ~^~~~~~~ drivers/usb/gadget/composite.c: In function ‘bos_desc’: drivers/usb/gadget/composite.c:708:15: error: taking address of packed member of ‘struct usb_bos_descriptor’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 708 | le16_add_cpu(&bos->wTotalLength, USB_DT_USB_EXT_CAP_SIZE); | ^~~~~~~~~~~~~~~~~~ drivers/usb/gadget/composite.c:724:16: error: taking address of packed member of ‘struct usb_bos_descriptor’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 724 | le16_add_cpu(&bos->wTotalLength, USB_DT_USB_SS_CAP_SIZE); | Best regards Heinrich

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