November 2019 - U-Boot

[U-Boot] [PATCH 1/6] ARM: imx: vining2000: Convert to SPL framework
by Marek Vasut 26 Nov '19

26 Nov '19

In preparation for use of DDR DRAM fine-tuning upon boot, convert the board to SPL framework instead of using DCD tables to bring up DRAM and pinmux. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Silvio Fricke <silvio.fricke(a)softing.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/mach-imx/mx6/Kconfig | 1 + board/softing/vining_2000/vining_2000.c | 182 ++++++++++++++++++++++++ configs/vining_2000_defconfig | 12 +- include/configs/vining_2000.h | 4 + 4 files changed, 198 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 607210520f..ef816a24ff 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -558,6 +558,7 @@ config TARGET_SOFTING_VINING_2000 select DM select DM_THERMAL select MX6SX + select SUPPORT_SPL imply CMD_DM config TARGET_WANDBOARD diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c index 51985b91c2..086de1eaf5 100644 --- a/board/softing/vining_2000/vining_2000.c +++ b/board/softing/vining_2000/vining_2000.c @@ -432,3 +432,185 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_SPL_BUILD +#include <linux/libfdt.h> +#include <spl.h> +#include <asm/arch/mx6-ddr.h> + +static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR }; + +static iomux_v3_cfg_t const uart_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static void vining2000_spl_setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); +} + +int board_mmc_init(bd_t *bis) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + if ((val & 0xc0) != 0x40) { + printf("Not boot from USDHC!\n"); + return -EINVAL; + } + + port = (val >> 11) & 0x3; + printf("port %d\n", port); + switch (port) { + case 3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR; + break; + } + + gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_ras = 0x00000028, + .dram_cas = 0x00000028, + .dram_odt0 = 0x00000028, + .dram_odt1 = 0x00000028, + .dram_sdba2 = 0x00000000, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_reset = 0x00000028, +}; + +const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000028, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, + .grp_ctlds = 0x00000028, + .grp_ddr_type = 0x000c0000, + .grp_ddrmode = 0x00020000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x0022001C, + .p0_mpwldectrl1 = 0x001F001A, + .p0_mpdgctrl0 = 0x01380134, + .p0_mpdgctrl1 = 0x0124011C, + .p0_mprddlctl = 0x42404444, + .p0_mpwrdlctl = 0x36383C38, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 32, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1391, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xF000000F, &ccm->CCGR0); /* AIPS_TZ{1,2,3} */ + writel(0x303C0000, &ccm->CCGR1); /* GPT, OCRAM */ + writel(0x00FFFCC0, &ccm->CCGR2); /* IPMUX, I2C1, I2C3 */ + writel(0x3F300030, &ccm->CCGR3); /* OCRAM, MMDC, ENET */ + writel(0x0000C003, &ccm->CCGR4); /* PCI, PL301 */ + writel(0x0F0330C3, &ccm->CCGR5); /* UART, ROM */ + writel(0x00000F00, &ccm->CCGR6); /* SDHI4, EIM */ +} + +static void vining2000_spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + .dsize = mem_ddr.width / 32, + .cs_density = 24, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, /* RTT_wr = RZQ/4 */ + .rtt_nom = 1, /* RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ + }; + + mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* iomux setup */ + vining2000_spl_setup_iomux_uart(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + vining2000_spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 32ef01b639..4f9f538189 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -1,18 +1,29 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_TARGET_SOFTING_VINING_2000=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x80000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set +CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/softing/vining_2000/imximage.cfg" CONFIG_BOOTDELAY=0 CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set @@ -53,7 +64,6 @@ CONFIG_DM_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_PWM_IMX=y -CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 54c8c2f62e..377406f842 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -91,4 +91,8 @@ #define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */ #endif +#ifdef CONFIG_SPL_BUILD +#define CONFIG_MXC_UART_BASE UART1_BASE +#endif + #endif /* __CONFIG_H */ -- 2.24.0

1 5

[U-Boot] [PATCH] configs/lx2160a: Add CONFIG_ENV_SECT_SIZE in defconfig
by Priyanka Jain 26 Nov '19

26 Nov '19

Define CONFIG_ENV_SECT_SIZE as 0x20000 in lx2160a related defconfigs: lx2160ardb_tfa_defconfig, lx2160ardb_tfa_SECURE_BOOT_defconfig, lx2160aqds_tfa_defconfig, lx2160aqds_tfa_SECURE_BOOT_defconfig Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 4ab7582fc7..19635d4ac6 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NXP_ESBC=y CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index a35f1cc38d..8f2cfad3b3 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -4,6 +4,7 @@ CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 87c54b00f6..f490d10da1 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_NXP_ESBC=y CONFIG_EMC2305=y CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 18057b20b1..4122fb3d1f 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_SYS_MALLOC_F_LEN=0x6000 CONFIG_EMC2305=y CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 CONFIG_NR_DRAM_BANKS=3 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y -- 2.17.1

1 0

[U-Boot] [PATCH v3 01/20] arch: powerpc: add eSDHC node to p1020 dts
by Yinbo Zhu 26 Nov '19

26 Nov '19

Add eSDHC node to p1020 dts Signed-off-by: Yinbo Zhu <yinbo.zhu(a)nxp.com> --- arch/powerpc/dts/p1020-post.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1e5e678..fb3b203 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -24,6 +24,13 @@ single-cpu-affinity; last-interrupt-source = <255>; }; + + esdhc: esdhc@2e000 { + compatible = "fsl,esdhc"; + reg = <0x2e000 0x1000>; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; }; /* PCIe controller base address 0x9000 */ -- 2.9.5

2 23

[U-Boot] [PATCH v3] armv8: ls1046afrwy: Add support for LS1046AFRWY Rev B board
by Pramod Kumar 26 Nov '19

26 Nov '19

Add rev B board support Signed-off-by: Pramod Kumar <pramod.kumar_1(a)nxp.com> --- board/freescale/ls1046afrwy/ls1046afrwy.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c index ac2f8ee..3134feb 100644 --- a/board/freescale/ls1046afrwy/ls1046afrwy.c +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -24,7 +24,7 @@ #define LS1046A_PORSR1_REG 0x1EE0000 #define BOOT_SRC_SD 0x20000000 #define BOOT_SRC_MASK 0xFF800000 -#define BOARD_REV_GPIO 13 +#define BOARD_REV_GPIO_SHIFT 17 #define USB2_SEL_MASK 0x00000100 #define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \ @@ -88,9 +88,14 @@ int board_early_init_f(void) static inline uint8_t get_board_version(void) { u8 val; + u32 gpio_val; struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR); - val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03; + /* GPIO 13 and GPIO 14 are use for Board Rev */ + gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT)) & 0x03; + + /* GPIO's are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */ + val = ((gpio_val >> 1) | (gpio_val << 1)) & 0x03; return val; } -- 2.7.4

2 1

[U-Boot] [PATCH v5] armv8: Add workaround for USB erratum A-050106
by Ran Wang 26 Nov '19

26 Nov '19

USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar to erratum A-009007, but this one is for LX2160A, and the register value is different. Signed-off-by: Ran Wang <ran.wang_1(a)nxp.com> --- Change in v5: - Add paragraph to describe config SYS_FSL_ERRATUM_A050106 in Kconfig Change in v4: - Include defines of USB_PHY_RX_EQ_VAL_3 and USB_PHY_RX_EQ_VAL_4 for LS1028A to fix compile failure. Change in v3: - Rebase patch for latest U-Boot (v2019.10) Change in v2: - Move function erratum_a050106() under the scope of CONFIG_FSL_LSCH3 to avoid compilation warning of 'defined but not used'. arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 9 +++++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 12 +++++++++++- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 6 ++++++ 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f1578b1..0de840a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -219,6 +219,7 @@ config ARCH_LX2160A select SYS_FSL_DDR_VER_50 select SYS_FSL_EC1 select SYS_FSL_EC2 + select SYS_FSL_ERRATUM_A050106 select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_SEC select SYS_FSL_HAS_CCN508 @@ -348,6 +349,14 @@ config SYS_FSL_ERRATUM_A009008 config SYS_FSL_ERRATUM_A009798 bool "Workaround for USB PHY erratum A009798" +config SYS_FSL_ERRATUM_A050106 + bool "Workaround for USB PHY erratum A050106" + help + USB3.0 Receiver needs to enable fixed equalization + for each of PHY instances in an SOC. This is similar + to erratum A-009007, but this one is for LX2160A, + and the register value is different. + config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index adfa51b..1fece3e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -146,7 +146,7 @@ static void erratum_a008997(void) out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ - defined(CONFIG_ARCH_LS1028A) + defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ @@ -180,6 +180,15 @@ static void erratum_a009007(void) } #if defined(CONFIG_FSL_LSCH3) +static void erratum_a050106(void) +{ +#if defined(CONFIG_ARCH_LX2160A) + void __iomem *dcsr = (void __iomem *)DCSR_BASE; + + PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); + PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2); +#endif +} /* * This erratum requires setting a value to eddrtqcr1 to * optimal the DDR performance. @@ -331,6 +340,7 @@ void fsl_lsch3_early_init_f(void) erratum_a009798(); erratum_a008997(); erratum_a009007(); + erratum_a050106(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index d46477d..7670b56 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -252,8 +252,14 @@ #define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C #define USB_PHY_RX_EQ_VAL_1 0x0000 #define USB_PHY_RX_EQ_VAL_2 0x0080 +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ + defined(CONFIG_ARCH_LS1028A) #define USB_PHY_RX_EQ_VAL_3 0x0380 #define USB_PHY_RX_EQ_VAL_4 0x0b80 +#elif defined(CONFIG_ARCH_LX2160A) +#define USB_PHY_RX_EQ_VAL_3 0x0080 +#define USB_PHY_RX_EQ_VAL_4 0x0880 +#endif #define DCSR_USB_IOCR1 0x108004 #define DCSR_USB_PCSTXSWINGFULL 0x71 -- 2.7.4

1 0

[U-Boot] [PATCH v2 0/5] board: ti: beagleboneai: add initial support
by Caleb Robey 26 Nov '19

26 Nov '19

The following patches 1) Introduce the emmc based board detection for BBAI due to a lack of eeprom onboard the BBAI (to be fixed in future revision of the board). 2) Minor changes to files to support dts and bbai boot overall 3) Add structures in the pinctrl to detect the beaglebone AI and add checks for the beaglebone AI in the board detection scheme 4) Add device tree file for BeagleBone AI 5) Enable beaglebone ai in am57xx_evm_defconfig Device tree has gone to mainline kernel found here: https://patchwork.kernel.org/patch/11254903/ v2 Changes: - Introduced missed additions in board.c that allow the actual configuration of the BBAI when detected. I also removed the hardcoded change of uart0 serial confirution and added a CONFIG_PREBOOT variable to do the board detect and setenv of the console variable Caleb Robey (5): board: ti: beagleboneai: emmc read changes board: ti: beagleboneai: add initial support board: ti: beagleboneai: IODELAY and pinmux changes board: ti: beagleboneai: add dts file board: ti: beagleboneai: enable in am57xx_evm_defconfig arch/arm/dts/Makefile | 1 + arch/arm/dts/am5729-beagleboneai.dts | 737 +++++++++++++++++++++++++++ arch/arm/dts/dra7.dtsi | 2 +- arch/arm/mach-omap2/omap5/hw_data.c | 1 + board/ti/am57xx/board.c | 61 ++- board/ti/am57xx/mux_data.h | 280 ++++++++++ board/ti/common/board_detect.c | 80 ++- board/ti/common/board_detect.h | 9 + configs/am57xx_evm_defconfig | 3 +- include/configs/am57xx_evm.h | 1 - include/environment/ti/boot.h | 2 + 11 files changed, 1170 insertions(+), 7 deletions(-) create mode 100644 arch/arm/dts/am5729-beagleboneai.dts -- 2.17.1

2 10

[U-Boot] [PATCH v2] cmd: efidebug: fix a build error in show_efi_boot_opt()
by AKASHI Takahiro 26 Nov '19

26 Nov '19

I detected the following error in sandbox with Clang on Travis CI: +cmd/efidebug.c:703:15: error: result of comparison of constant 9223372036854775822 with expression of type 'int' is always false [-Werror,-Wtautological-constant-out-of-range-compare] + else if (ret == EFI_NOT_FOUND) + ~~~ ^ ~~~~~~~~~~~~~ Simply changing a type of 'ret' to efi_status_t will fix this error. Signed-off-by: AKASHI Takahiro <takahiro.akashi(a)linaro.org> --- cmd/efidebug.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmd/efidebug.c b/cmd/efidebug.c index ef97e19d0735..1fff4390deae 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -684,7 +684,7 @@ static void show_efi_boot_opt(int id) efi_guid_t guid; void *data = NULL; efi_uintn_t size; - int ret; + efi_status_t ret; sprintf(var_name, "Boot%04X", id); p = var_name16; @@ -693,7 +693,7 @@ static void show_efi_boot_opt(int id) size = 0; ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size, NULL)); - if (ret == (int)EFI_BUFFER_TOO_SMALL) { + if (ret == EFI_BUFFER_TOO_SMALL) { data = malloc(size); ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size, data)); -- 2.24.0

2 1

[U-Boot] [PATCH] cmd: efidebug: fix a build error in show_efi_boot_opt()
by AKASHI Takahiro 26 Nov '19

26 Nov '19

I detected the following error in sandbox with Clang on Travis CI: +cmd/efidebug.c:703:15: error: result of comparison of constant 9223372036854775822 with expression of type 'int' is always false [-Werror,-Wtautological-constant-out-of-range-compare] + else if (ret == EFI_NOT_FOUND) + ~~~ ^ ~~~~~~~~~~~~~ Simply changing a type of 'ret' to efi_status_t will fix this error. Signed-off-by: AKASHI Takahiro <takahiro.akashi(a)linaro.org> --- cmd/efidebug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/efidebug.c b/cmd/efidebug.c index ef97e19d0735..09ac84e5ef0a 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -684,7 +684,7 @@ static void show_efi_boot_opt(int id) efi_guid_t guid; void *data = NULL; efi_uintn_t size; - int ret; + efi_status_t ret; sprintf(var_name, "Boot%04X", id); p = var_name16; -- 2.24.0

2 2

[U-Boot] Please pull u-boot-video
by Anatolij Gustschin 25 Nov '19

25 Nov '19

Hi Tom, The following changes since commit 9a0cbae22a613dfd55e15565785749b74c19fdf0: Merge tag 'u-boot-rockchip-20191124' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip (2019-11-23 20:50:11 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-video.git tags/fixes-for-v2020.01 for you to fetch changes up to beeb57f0a66658aacad3f12f1a31e65f5d22e46d: Revert "video: mxsfb: Configure the clock after eLCDIF reset" (2019-11-24 21:50:44 +0100) ---------------------------------------------------------------- - fix mxsfb regression on pico-imx7d and imx7d-sabre ---------------------------------------------------------------- Fabio Estevam (1): Revert "video: mxsfb: Configure the clock after eLCDIF reset" drivers/video/mxsfb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Please pull. Thanks! Anatolij

2 1

[U-Boot] [GIT PULL resed] Raspberry Pi updates for v2020.01
by Matthias Brugger 25 Nov '19

25 Nov '19

Hi Tom, This is a new pull request for the RPi updates for v2020.01. After you noticed that the first pull request broke FAT implementation I deleted the corresponding patch series from the pull request. In the meantime the one binary support for RPi is ready to be merged, so I added the series. Please have a look, you can find the travis-ci here: https://travis-ci.org/mbgg/u-boot/builds/616217762 Regards, Matthias --- The following changes since commit d4a31e8ee5592072d8d5208b3e950cba2d89b6bd: Prepare v2020.01-rc3 (2019-11-18 21:31:49 -0500) are available in the Git repository at: https://github.com/mbgg/u-boot tags/rpi-next-2020.01 for you to fetch changes up to 5694090670e262b038377bf196188d8089dc90c4: ARM: defconfig: add unified config for RPi3 and RPi4 (2019-11-24 10:46:28 +0100) ---------------------------------------------------------------- - add RPi4 upstream compatible to pinctrl - fix boot banner on RPi3/4 - add support for one binary on RPi3/4 ---------------------------------------------------------------- Matthias Brugger (9): pinctrl: bcm283x: Add compatible for RPi4 fdt: fix bcm283x dm-pre-reloc definitions arm: dts: bcm283x: Rename U-Boot file drivers: bcm283x: Set pre-location flag for OF_BOARD rpi: push fw_dtb_pointer in the .data section ARM: bcm283x: Move BCM283x_BASE to a global variable ARM: bcm283x: Set rpi_bcm283x_base at run-time ARM: bcm283x: Set memory map at run-time ARM: defconfig: add unified config for RPi3 and RPi4 .../{bcm283x-uboot.dtsi => bcm283x-u-boot.dtsi} | 4 - arch/arm/mach-bcm283x/Kconfig | 13 +-- arch/arm/mach-bcm283x/include/mach/base.h | 11 ++ arch/arm/mach-bcm283x/include/mach/mbox.h | 4 +- arch/arm/mach-bcm283x/include/mach/sdhci.h | 5 +- arch/arm/mach-bcm283x/include/mach/timer.h | 7 +- arch/arm/mach-bcm283x/include/mach/wdog.h | 5 +- arch/arm/mach-bcm283x/init.c | 116 +++++++++++++++++++++ arch/arm/mach-bcm283x/mbox.c | 1 + arch/arm/mach-bcm283x/reset.c | 20 +++- board/raspberrypi/rpi/lowlevel_init.S | 12 +-- board/raspberrypi/rpi/rpi.c | 52 +-------- configs/rpi_arm64_defconfig | 45 ++++++++ drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 3 +- drivers/serial/serial_bcm283x_mu.c | 2 +- drivers/serial/serial_bcm283x_pl011.c | 2 +- include/configs/rpi.h | 4 + 17 files changed, 227 insertions(+), 79 deletions(-) rename arch/arm/dts/{bcm283x-uboot.dtsi => bcm283x-u-boot.dtsi} (90%) create mode 100644 arch/arm/mach-bcm283x/include/mach/base.h create mode 100644 configs/rpi_arm64_defconfig

2 1