January 2019 - U-Boot

[U-Boot] [PATCH 0/5] efi_loader: run a specific efi application more easily
by AKASHI Takahiro 07 Jan '19

07 Jan '19

This patch is a result from re-organizing my previous patches; a combination of [1] and part of [2] so as solely to provide several ways of executing a specific efi application explicitly. * bootmanager via BootNext variable * bootefi with boot id * run -e [1] https://lists.denx.de/pipermail/u-boot/2018-November/349281.html [2] https://lists.denx.de/pipermail/u-boot/2018-November/346450.html AKASHI Takahiro (5): efi_loader: bootmgr: support BootNext and BootCurrent variable behavior efi_loader: bootmgr: allow for running a given load option cmd: bootefi: carve out fdt parameter handling cmd: bootefi: run an EFI application of a specific load option cmd: run: add "-e" option to run an EFI application cmd/bootefi.c | 71 +++++++++++++++++++++++++----------- cmd/bootefi.h | 3 ++ cmd/nvedit.c | 5 +++ common/cli.c | 31 ++++++++++++++++ include/command.h | 3 ++ include/efi_loader.h | 3 +- lib/efi_loader/efi_bootmgr.c | 46 ++++++++++++++++++++++- 7 files changed, 138 insertions(+), 24 deletions(-) create mode 100644 cmd/bootefi.h -- 2.19.1

3 22

[U-Boot] [PATCH] mtd: spi: Add 4bytes extend address support
by Ye Li 07 Jan '19

07 Jan '19

Current SPI flash framework only supports to set bank register (CONFIG_SPI_FLASH_BAR) for flash with size > 16MiB. But some new flash device (for example, mt35xu512g) does not support this way, it only supports 4bytes extend address. To access the whole memory size for such flash device, we add the support for this 4bytes extend address mode to SPI flash framework. The configuration CONFIG_SPI_FLASH_4BYTES_ADDR is used to enable the feature. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/mtd/spi/Kconfig | 7 ++++ drivers/mtd/spi/sf_internal.h | 8 +++++ drivers/mtd/spi/spi_flash.c | 75 ++++++++++++++++++++++++++++++++++++++----- 3 files changed, 82 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 76d5a1d..ffc80dd 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -42,6 +42,13 @@ config SPI_FLASH_BAR Bank/Extended address registers are used to access the flash which has size > 16MiB in 3-byte addressing. +config SPI_FLASH_4BYTES_ADDR + bool "SPI flash 4bytes (32) address mode support" + depends on SPI_FLASH && !SPI_FLASH_BAR + help + Enable the SPI flash 4bytes extend address mode support to access the flash + which has size > 16MiB. + config SF_DUAL_FLASH bool "SPI DUAL flash memory support" depends on SPI_FLASH diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h index 46a5044..50d0863 100644 --- a/drivers/mtd/spi/sf_internal.h +++ b/drivers/mtd/spi/sf_internal.h @@ -63,6 +63,14 @@ enum spi_nor_option_flags { #define CMD_READ_CONFIG 0x35 #define CMD_FLAG_STATUS 0x70 +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR +#define CMD_READ_ARRAY_FAST_4B 0x0c +#define CMD_PAGE_PROGRAM_4B 0x12 +#define CMD_ERASE_64K_4B 0xdc +#define CMD_ERASE_4K_4B 0x21 +#define CMD_EN4B 0xB7 +#endif + /* Bank addr access commands */ #ifdef CONFIG_SPI_FLASH_BAR # define CMD_BANKADDR_BRWR 0x17 diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 0c2392f..312bedb 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -28,6 +28,17 @@ static void spi_flash_addr(u32 addr, u8 *cmd) cmd[3] = addr >> 0; } +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR +static void spi_flash_addr_4b(u32 addr, u8 *cmd) +{ + /* cmd[0] is actual command */ + cmd[1] = addr >> 24; + cmd[2] = addr >> 16; + cmd[3] = addr >> 8; + cmd[4] = addr >> 0; +} +#endif + static int read_sr(struct spi_flash *flash, u8 *rs) { int ret; @@ -325,8 +336,8 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) { - u32 erase_size, erase_addr; - u8 cmd[SPI_FLASH_CMD_LEN]; + u32 erase_size, erase_addr, cmd_len; + u8 cmd[SPI_FLASH_CMD_LEN + 1]; int ret = -1; erase_size = flash->erase_size; @@ -357,11 +368,19 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) return ret; #endif spi_flash_addr(erase_addr, cmd); + cmd_len = SPI_FLASH_CMD_LEN; + +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR + if (flash->size > SPI_FLASH_16MB_BOUN) { + spi_flash_addr_4b(erase_addr, cmd); + cmd_len = SPI_FLASH_CMD_LEN + 1; + } +#endif debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], erase_addr); - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); + ret = spi_flash_write_common(flash, cmd, cmd_len, NULL, 0); if (ret < 0) { debug("SF: erase failed\n"); break; @@ -384,8 +403,8 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, struct spi_slave *spi = flash->spi; unsigned long byte_addr, page_size; u32 write_addr; - size_t chunk_len, actual; - u8 cmd[SPI_FLASH_CMD_LEN]; + size_t chunk_len, actual, cmd_len; + u8 cmd[SPI_FLASH_CMD_LEN + 1]; int ret = -1; page_size = flash->page_size; @@ -419,11 +438,19 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, spi->max_write_size - sizeof(cmd)); spi_flash_addr(write_addr, cmd); + cmd_len = SPI_FLASH_CMD_LEN; + +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR + if (flash->size > SPI_FLASH_16MB_BOUN) { + spi_flash_addr_4b(write_addr, cmd); + cmd_len = SPI_FLASH_CMD_LEN + 1; + } +#endif debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); - ret = spi_flash_write_common(flash, cmd, sizeof(cmd), + ret = spi_flash_write_common(flash, cmd, cmd_len, buf + actual, chunk_len); if (ret < 0) { debug("SF: write failed\n"); @@ -500,6 +527,10 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, } cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR + if (flash->size > SPI_FLASH_16MB_BOUN) + cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte + 1; +#endif u8 cmd[cmdsz]; cmd[0] = flash->read_cmd; @@ -528,6 +559,12 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, spi_flash_addr(read_addr, cmd); +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR + if (flash->size > SPI_FLASH_16MB_BOUN) { + spi_flash_addr_4b(read_addr, cmd); + read_len = len; /* Not care remain len for current bank */ + } +#endif ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); if (ret < 0) { debug("SF: read failed\n"); @@ -1114,6 +1151,13 @@ static int set_quad_mode(struct spi_flash *flash, } } +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR +static int enter_4bytes_addr(struct spi_flash *flash) +{ + return spi_flash_cmd(flash->spi, CMD_EN4B, NULL, 0); +} +#endif + #if CONFIG_IS_ENABLED(OF_CONTROL) int spi_flash_decode_fdt(struct spi_flash *flash) { @@ -1262,6 +1306,21 @@ int spi_flash_scan(struct spi_flash *flash) /* Go for default supported write cmd */ flash->write_cmd = CMD_PAGE_PROGRAM; +#ifdef CONFIG_SPI_FLASH_4BYTES_ADDR + if (flash->size > SPI_FLASH_16MB_BOUN) { + flash->read_cmd = CMD_READ_ARRAY_FAST_4B; + flash->write_cmd = CMD_PAGE_PROGRAM_4B; + + if (flash->erase_cmd == CMD_ERASE_4K) + flash->erase_cmd = CMD_ERASE_4K_4B; + else + flash->erase_cmd = CMD_ERASE_64K_4B; + + enter_4bytes_addr(flash); + } +#endif + + /* Set the quad enable bit - only for quad commands */ if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || @@ -1323,13 +1382,13 @@ int spi_flash_scan(struct spi_flash *flash) puts("\n"); #endif -#ifndef CONFIG_SPI_FLASH_BAR +#if !defined(CONFIG_SPI_FLASH_BAR) && !defined(CONFIG_SPI_FLASH_4BYTES_ADDR) if (((flash->dual_flash == SF_SINGLE_FLASH) && (flash->size > SPI_FLASH_16MB_BOUN)) || ((flash->dual_flash > SF_SINGLE_FLASH) && (flash->size > SPI_FLASH_16MB_BOUN << 1))) { puts("SF: Warning - Only lower 16MiB accessible,"); - puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); + puts(" Full access #define CONFIG_SPI_FLASH_BAR or #define CONFIG_SPI_FLASH_4BYTES_ADDR\n"); } #endif -- 2.7.4

1 0

[U-Boot] [PATCH] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue
by Ye Li 07 Jan '19

07 Jan '19

When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode, the output clock rate is half of the internal clock rate. This patch set the DDR_EN bit first for DDR mode, hardware divide the usdhc clock automatically, then follow the original sdr clock setting method. Signed-off-by: Haibo Chen <haibo.chen(a)nxp.com> Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/mmc/fsl_esdhc.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 74007e2..87273c8 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -585,18 +585,31 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) #else int pre_div = 2; #endif - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; int sdhc_clk = priv->sdhc_clk; uint clk; + /* + * For ddr mode, usdhc need to enable DDR mode first, after select + * this DDR mode, usdhc will automatically divide the usdhc clock + */ + if (mmc->ddr_mode) { + writel(readl(&regs->mixctrl) | MIX_CTRL_DDREN, &regs->mixctrl); + sdhc_clk >>= 1; + } + if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min; - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) - pre_div *= 2; + if (sdhc_clk / 16 > clock) { + for (; pre_div < 256; pre_div *= 2) + if ((sdhc_clk / pre_div) <= (clock * 16)) + break; + } else + pre_div = 1; - while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) - div++; + for (div = 1; div <= 16; div++) + if ((sdhc_clk / (div * pre_div)) <= clock) + break; pre_div >>= 1; div -= 1; -- 2.7.4

1 0

[U-Boot] [PATCH] exynos: Leave the compiler to choose the register to avoid possible r0 corruption
by Guillaume GARDET 07 Jan '19

07 Jan '19

Reported-by: Siarhei Siamashka <siarhei.siamashka(a)gmail.com> Signed-off-by: Guillaume GARDET <guillaume.gardet(a)free.fr> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Minkyu Kang <mk7.kang(a)samsung.com> Cc: Tom Rini <trini(a)konsulko.com> --- arch/arm/mach-exynos/include/mach/system.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 81fa9800b4..48f13c7648 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -58,8 +58,7 @@ struct exynos5_sysreg { /* Move 0xd3 value to CPSR register to enable SVC mode */ #define svc32_mode_en() __asm__ __volatile__ \ ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ - "mov r0, #0x13|0xC0\n\t" \ - "msr cpsr_c, r0\n\t" : : ) + "msr cpsr_c, %0\n\t" : : "r"(0x13|0xC0)) /* Set program counter with the given value */ #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) -- 2.20.1

2 1

[U-Boot] [PATCH v5.1 19/26] musb-new: sunxi: Use CLK and RESET support
by Jagan Teki 06 Jan '19

06 Jan '19

Now clock and reset drivers are available for respective SoC's so use clk and reset ops on musb driver. Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard(a)bootlin.com> --- Changes for v5.1: - use dev_err instead of pr_err drivers/usb/musb-new/sunxi.c | 79 ++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 40 deletions(-) diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index f542a181fa..45eecfeee6 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -16,9 +16,11 @@ * This file is part of the Inventra Controller Driver for Linux. */ #include <common.h> +#include <clk.h> #include <dm.h> #include <generic-phy.h> #include <phy-sun4i-usb.h> +#include <reset.h> #include <asm/arch/cpu.h> #include <asm/arch/clock.h> #include <asm/arch/gpio.h> @@ -80,16 +82,12 @@ struct sunxi_musb_config { struct musb_hdrc_config *config; - bool has_reset; - u8 rst_bit; - u8 clkgate_bit; - u32 off_reset0; }; struct sunxi_glue { struct musb_host_data mdata; - struct sunxi_ccm_reg *ccm; - u32 *reg_reset0; + struct clk clk; + struct reset_ctl rst; struct sunxi_musb_config *cfg; struct device dev; struct phy phy; @@ -296,24 +294,27 @@ static int sunxi_musb_init(struct musb *musb) pr_debug("%s():\n", __func__); - ret = generic_phy_init(&glue->phy); + ret = clk_enable(&glue->clk); if (ret) { - pr_err("failed to init USB PHY\n"); + dev_err(dev, "failed to enable clock\n"); return ret; } - musb->isr = sunxi_musb_interrupt; - - setbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->clkgate_bit) - setbits_le32(&glue->ccm->ahb_gate0, - BIT(glue->cfg->clkgate_bit)); + if (reset_valid(&glue->rst)) { + ret = reset_deassert(&glue->rst); + if (ret) { + dev_err(dev, "failed to deassert reset\n"); + goto err_clk; + } + } - if (glue->cfg->has_reset) - setbits_le32(glue->reg_reset0, BIT(AHB_GATE_OFFSET_USB0)); + ret = generic_phy_init(&glue->phy); + if (ret) { + dev_err(dev, "failed to init USB PHY\n"); + goto err_rst; + } - if (glue->cfg->rst_bit) - setbits_le32(glue->reg_reset0, BIT(glue->cfg->rst_bit)); + musb->isr = sunxi_musb_interrupt; USBC_ConfigFIFO_Base(); USBC_EnableDpDmPullUp(musb->mregs); @@ -329,6 +330,13 @@ static int sunxi_musb_init(struct musb *musb) USBC_ForceVbusValidToHigh(musb->mregs); return 0; + +err_rst: + if (reset_valid(&glue->rst)) + reset_assert(&glue->rst); +err_clk: + clk_disable(&glue->clk); + return ret; } static int sunxi_musb_exit(struct musb *musb) @@ -344,16 +352,9 @@ static int sunxi_musb_exit(struct musb *musb) } } - if (glue->cfg->has_reset) - clrbits_le32(glue->reg_reset0, BIT(AHB_GATE_OFFSET_USB0)); - - if (glue->cfg->rst_bit) - clrbits_le32(glue->reg_reset0, BIT(glue->cfg->rst_bit)); - - clrbits_le32(&glue->ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_USB0)); - if (glue->cfg->clkgate_bit) - clrbits_le32(&glue->ccm->ahb_gate0, - BIT(glue->cfg->clkgate_bit)); + if (reset_valid(&glue->rst)) + reset_assert(&glue->rst); + clk_disable(&glue->clk); return 0; } @@ -450,11 +451,17 @@ static int musb_usb_probe(struct udevice *dev) if (!glue->cfg) return -EINVAL; - glue->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (IS_ERR(glue->ccm)) - return PTR_ERR(glue->ccm); + ret = clk_get_by_index(dev, 0, &glue->clk); + if (ret) { + dev_err(dev, "failed to get clock\n"); + return ret; + } - glue->reg_reset0 = (void *)glue->ccm + glue->cfg->off_reset0; + ret = reset_get_by_index(dev, 0, &glue->rst); + if (ret && ret != -ENOENT) { + dev_err(dev, "failed to get reset\n"); + return ret; + } ret = generic_phy_get_by_name(dev, "usb", &glue->phy); if (ret) { @@ -462,7 +469,6 @@ static int musb_usb_probe(struct udevice *dev) return ret; } - memset(&pdata, 0, sizeof(pdata)); pdata.power = 250; pdata.platform_ops = &sunxi_musb_ops; @@ -505,21 +511,14 @@ static int musb_usb_remove(struct udevice *dev) static const struct sunxi_musb_config sun4i_a10_cfg = { .config = &musb_config, - .has_reset = false, }; static const struct sunxi_musb_config sun6i_a31_cfg = { .config = &musb_config, - .has_reset = true, - .off_reset0 = OFF_SUN6I_AHB_RESET0, }; static const struct sunxi_musb_config sun8i_h3_cfg = { .config = &musb_config_h3, - .has_reset = true, - .rst_bit = 23, - .clkgate_bit = 23, - .off_reset0 = OFF_SUN6I_AHB_RESET0, }; static const struct udevice_id sunxi_musb_ids[] = { -- 2.18.0.321.gffc6fa0e3

2 1

[U-Boot] [PATCH 0/7] MSCC: Add Jaguar2 SOC family
by Horatiu Vultur 06 Jan '19

06 Jan '19

This patch series add support for MSCC Jaguar2 SOC family. In this family there are following boards: Jaguar2(pcb110), Jaguar2-48(pcb111) and Serval2(pcb112). This is based off the u-boot-mips/next repository Horatiu Vultur (7): pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC family MSCC: Add support for Jaguar2 SOC family MSCC: Add device tree for Jaguar2 board MSCC: Add device tree for Jaguar2-48 board MSCC: add device tree for Serval2 board MSCC: add configuration for Jaguar2 SOC family. MSCC: Add board support for Jaguar2 SOC family. MAINTAINERS | 3 + arch/mips/dts/Makefile | 1 + arch/mips/dts/jr2_pcb110.dts | 74 +++++ arch/mips/dts/jr2_pcb111.dts | 74 +++++ arch/mips/dts/mscc,jr2.dtsi | 187 ++++++++++++ arch/mips/dts/serval2_pcb112.dts | 60 ++++ arch/mips/mach-mscc/Kconfig | 9 + arch/mips/mach-mscc/Makefile | 5 +- arch/mips/mach-mscc/cpu.c | 7 + arch/mips/mach-mscc/dram.c | 2 +- arch/mips/mach-mscc/include/mach/common.h | 5 + arch/mips/mach-mscc/include/mach/ddr.h | 40 ++- arch/mips/mach-mscc/include/mach/jr2/jr2.h | 24 ++ .../mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h | 20 ++ .../include/mach/jr2/jr2_devcpu_gcb_miim_regs.h | 25 ++ .../mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h | 321 +++++++++++++++++++++ arch/mips/mach-mscc/reset.c | 17 ++ board/mscc/common/spi.c | 31 ++ board/mscc/jr2/Kconfig | 15 + board/mscc/{ocelot => jr2}/Makefile | 2 +- board/mscc/jr2/jr2.c | 117 ++++++++ board/mscc/ocelot/Makefile | 2 +- board/mscc/ocelot/ocelot.c | 22 -- configs/mscc_jr2_defconfig | 59 ++++ drivers/pinctrl/mscc/Kconfig | 9 + drivers/pinctrl/mscc/Makefile | 1 + drivers/pinctrl/mscc/mscc-common.c | 122 ++++++-- drivers/pinctrl/mscc/pinctrl-jr2.c | 302 +++++++++++++++++++ 28 files changed, 1498 insertions(+), 58 deletions(-) create mode 100644 arch/mips/dts/jr2_pcb110.dts create mode 100644 arch/mips/dts/jr2_pcb111.dts create mode 100644 arch/mips/dts/mscc,jr2.dtsi create mode 100644 arch/mips/dts/serval2_pcb112.dts create mode 100644 arch/mips/mach-mscc/include/mach/jr2/jr2.h create mode 100644 arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/jr2/jr2_devcpu_gcb_miim_regs.h create mode 100644 arch/mips/mach-mscc/include/mach/jr2/jr2_icpu_cfg.h create mode 100644 board/mscc/common/spi.c create mode 100644 board/mscc/jr2/Kconfig copy board/mscc/{ocelot => jr2}/Makefile (50%) create mode 100644 board/mscc/jr2/jr2.c create mode 100644 configs/mscc_jr2_defconfig create mode 100644 drivers/pinctrl/mscc/pinctrl-jr2.c -- 2.7.4

2 11

[U-Boot] [PATCH 1/1] efi_driver: simplify error message
by Heinrich Schuchardt 06 Jan '19

06 Jan '19

Stating the function module is sufficient. We don't need file and line number. Anyway the format code for the line number was incorrect (should be %d). Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_driver/efi_uclass.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/lib/efi_driver/efi_uclass.c b/lib/efi_driver/efi_uclass.c index bb86ffd399..7cdf81f40c 100644 --- a/lib/efi_driver/efi_uclass.c +++ b/lib/efi_driver/efi_uclass.c @@ -233,8 +233,7 @@ static efi_status_t EFIAPI efi_uc_stop( } ret = EFI_CALL(systab.boottime->free_pool(entry_buffer)); if (ret != EFI_SUCCESS) - printf("%s(%u) %s: ERROR: Cannot free pool\n", - __FILE__, __LINE__, __func__); + printf("%s: ERROR: Cannot free pool\n", __func__); /* Detach driver from controller */ ret = EFI_CALL(systab.boottime->close_protocol( -- 2.20.1

1 0

[U-Boot] [PATCH 1/1] efi_selftest: tpl unit test, check return values
by Heinrich Schuchardt 06 Jan '19

06 Jan '19

For some API calls checks for the return values are missing. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_selftest/efi_selftest_tpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/efi_selftest/efi_selftest_tpl.c b/lib/efi_selftest/efi_selftest_tpl.c index 97d256abe4..70a355eae6 100644 --- a/lib/efi_selftest/efi_selftest_tpl.c +++ b/lib/efi_selftest/efi_selftest_tpl.c @@ -151,7 +151,7 @@ static int execute(void) return EFI_ST_FAILURE; } ret = boottime->set_timer(event_notify, EFI_TIMER_STOP, 0); - if (index != 0) { + if (ret != EFI_SUCCESS) { efi_st_error("Could not cancel timer\n"); return EFI_ST_FAILURE; } @@ -164,7 +164,7 @@ static int execute(void) /* Set 10 ms timer */ notification_count = 0; ret = boottime->set_timer(event_notify, EFI_TIMER_PERIODIC, 100000); - if (index != 0) { + if (ret != EFI_SUCCESS) { efi_st_error("Could not set timer\n"); return EFI_ST_FAILURE; } -- 2.20.1

1 0

[U-Boot] [PATCH 1/1] efi_selftest: events unit test, check return values
by Heinrich Schuchardt 06 Jan '19

06 Jan '19

For some API calls checks for the return values are missing. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_selftest/efi_selftest_events.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/efi_selftest/efi_selftest_events.c b/lib/efi_selftest/efi_selftest_events.c index ed99a53804..1077cbdf9e 100644 --- a/lib/efi_selftest/efi_selftest_events.c +++ b/lib/efi_selftest/efi_selftest_events.c @@ -147,20 +147,20 @@ static int execute(void) return EFI_ST_FAILURE; } ret = boottime->set_timer(event_notify, EFI_TIMER_STOP, 0); - if (index != 0) { + if (ret != EFI_SUCCESS) { efi_st_error("Could not cancel timer\n"); return EFI_ST_FAILURE; } /* Set 10 ms timer */ timer_ticks = 0; ret = boottime->set_timer(event_notify, EFI_TIMER_RELATIVE, 100000); - if (index != 0) { + if (ret != EFI_SUCCESS) { efi_st_error("Could not set timer\n"); return EFI_ST_FAILURE; } /* Set 100 ms timer */ ret = boottime->set_timer(event_wait, EFI_TIMER_PERIODIC, 1000000); - if (index != 0) { + if (ret != EFI_SUCCESS) { efi_st_error("Could not set timer\n"); return EFI_ST_FAILURE; } -- 2.20.1

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[U-Boot] [RFC PATCH 0/8] Actions S700 SoC support
by Amit Singh Tomar 06 Jan '19

06 Jan '19

Hello, This patch-set adds Cubieboard7[1] support based on Action Semi's S700 SoC[2], It's Quad-core ARMv8 SoC with Cortex-A53 cores.Most of peripherals seems to be compatible with S900 SoC(basic support for it is alreay present in u-boot). First few patches consolidates Actions Semiconductor SoCs support in u-boot((mostly insprired by SUXNI as suggested by Andre).Idea is to move every bit out from board/ucRobotics into arch/arm/mach-owl. It allows different SoCs to be driven by single "soc and Kconfig" file. It also includes common clock driver for S700 and S900.Rest of patches enables S700 SoC support alongwith Cubieboard7 board. S700 support is tested[3] on Cubieboard7 board and S900 support is just compiled tested.It would be great, if someone who has S900 based board can test S900 support. Thanks, -Amit [1]: http://www.cubietech.com/product-detail/cubieboard7/ [2]: http://www.actions-semi.com/en/productview.aspx?id=225 [3]: https://paste.ubuntu.com/p/fkCdv5nw2Q/ Amit Singh Tomar (8): arm: actions: Add common framework for Actions Semi SoCs arm: actions: Add owl memory map regions clk: actions: Add common clock driver arm: board: Remove board files for bubblegum_96 arm: actions: add S700 SoC device tree arm: add Cubieboard7 board support serial: actions: add uart support for s700 actions: add Cubieboard7 README arch/arm/Kconfig | 2 - arch/arm/dts/s700-cubieboard7.dts | 39 ++++++ arch/arm/dts/s700.dtsi | 193 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-owl/clk_owl.h | 61 +++++++++ arch/arm/include/asm/arch-owl/clk_s900.h | 57 -------- arch/arm/include/asm/arch-owl/regs_s700.h | 56 ++++++++ arch/arm/mach-owl/Kconfig | 31 ++--- arch/arm/mach-owl/Makefile | 3 +- arch/arm/mach-owl/README.cubieboard7 | 88 ++++++++++++ arch/arm/mach-owl/soc.c | 56 ++++++++ arch/arm/mach-owl/sysmap-owl.c | 32 +++++ arch/arm/mach-owl/sysmap-s900.c | 32 ----- board/ucRobotics/bubblegum_96/Kconfig | 15 --- board/ucRobotics/bubblegum_96/MAINTAINERS | 6 - board/ucRobotics/bubblegum_96/Makefile | 3 - board/ucRobotics/bubblegum_96/bubblegum_96.c | 56 -------- configs/bubblegum_96_defconfig | 3 +- configs/cubieboard7_defconfig | 22 +++ drivers/clk/owl/Kconfig | 8 +- drivers/clk/owl/Makefile | 2 +- drivers/clk/owl/clk_owl.c | 132 ++++++++++++++++++ drivers/clk/owl/clk_s900.c | 137 ------------------- drivers/serial/serial_owl.c | 1 + include/configs/bubblegum_96.h | 42 ------ include/configs/owl-common.h | 42 ++++++ include/configs/s700.h | 15 +++ include/configs/s900.h | 18 +++ include/dt-bindings/clock/actions,s700-cmu.h | 118 ++++++++++++++++ 28 files changed, 893 insertions(+), 377 deletions(-) create mode 100644 arch/arm/dts/s700-cubieboard7.dts create mode 100644 arch/arm/dts/s700.dtsi create mode 100644 arch/arm/include/asm/arch-owl/clk_owl.h delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h create mode 100644 arch/arm/mach-owl/README.cubieboard7 create mode 100644 arch/arm/mach-owl/soc.c create mode 100644 arch/arm/mach-owl/sysmap-owl.c delete mode 100644 arch/arm/mach-owl/sysmap-s900.c delete mode 100644 board/ucRobotics/bubblegum_96/Kconfig delete mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS delete mode 100644 board/ucRobotics/bubblegum_96/Makefile delete mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c create mode 100644 configs/cubieboard7_defconfig create mode 100644 drivers/clk/owl/clk_owl.c delete mode 100644 drivers/clk/owl/clk_s900.c delete mode 100644 include/configs/bubblegum_96.h create mode 100644 include/configs/owl-common.h create mode 100644 include/configs/s700.h create mode 100644 include/configs/s900.h create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h -- 2.7.4

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