January 2019 - U-Boot

[U-Boot] [PATCH] imx6q_logic: Enable MMC booting from SPL
by Adam Ford 04 Jan '19

04 Jan '19

The MMC booting wasn't previously fitting into the codespace. This patch enables MMC booting from the baseboard by reducing some DM overhead during SPL. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index ce1c8a5d6b..696f5c4183 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -60,6 +60,7 @@ static iomux_v3_cfg_t const uart3_pads[] = { MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#ifndef CONFIG_SPL_BUILD static void fixup_enet_clock(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -108,6 +109,7 @@ static void fixup_enet_clock(void) dm_gpio_set_value(&reset, 1); mdelay(50); } +#endif static void setup_iomux_uart(void) { @@ -158,7 +160,9 @@ int overwrite_console(void) int board_early_init_f(void) { +#ifndef CONFIG_SPL_BUILD fixup_enet_clock(); +#endif setup_iomux_uart(); setup_nand_pins(); return 0; @@ -200,6 +204,74 @@ int spl_start_uboot(void) } #endif +/* SD interface */ +#define USDHC_PAD_CTRL \ + (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC1_BASE_ADDR}, /* SOM */ + {USDHC2_BASE_ADDR} /* Baseboard */ +}; + +int board_mmc_init(bd_t *bis) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1-SOM + * 0x2 SD2-Baseboard + */ + + reg &= 0x3; /* Only care about bottom 2 bits */ + + switch (reg - 1) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[1].sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[reg - 1]); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} +#endif + static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 036069a437..d0362665bb 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -4,25 +4,25 @@ CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6LOGICPD=y +CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SPL=y +CONFIG_SPL_FAT_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set CONFIG_SPL_SEPARATE_BSS=y +# CONFIG_TPL_BANNER_PRINT is not set +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET_SUPPORT=y CONFIG_SPL_USB_SDP_SUPPORT=y @@ -47,11 +47,9 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)" CONFIG_CMD_UBI=y -CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd" CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_SPL_DM=y CONFIG_PCF8575_GPIO=y CONFIG_SYS_I2C_MXC=y CONFIG_LED=y @@ -64,7 +62,6 @@ CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC_PFUZE100=y CONFIG_MXC_UART=y -- 2.17.1

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[U-Boot] [PATCH] exynos: allow SPL to build in thumb mode
by Guillaume GARDET 04 Jan '19

04 Jan '19

Building peach-pi smdk5420 and peach-pit with thumb mode for SPL ends-up in the following error: Error: Thumb encoding does not support an immediate here -- `msr cpsr_c,#0x13|0xC0' Use an intermediate register to be able to use thumb for exynos5 SPL. Signed-off-by: Guillaume GARDET <guillaume.gardet(a)free.fr> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Minkyu Kang <mk7.kang(a)samsung.com> Cc: Tom Rini <trini(a)konsulko.com> --- arch/arm/mach-exynos/include/mach/system.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 4837781957..81fa9800b4 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -58,7 +58,8 @@ struct exynos5_sysreg { /* Move 0xd3 value to CPSR register to enable SVC mode */ #define svc32_mode_en() __asm__ __volatile__ \ ("@ I&F disable, Mode: 0x13 - SVC\n\t" \ - "msr cpsr_c, #0x13|0xC0\n\t" : : ) + "mov r0, #0x13|0xC0\n\t" \ + "msr cpsr_c, r0\n\t" : : ) /* Set program counter with the given value */ #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x)) -- 2.20.1

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Re: [U-Boot] [PATCH v2 3/7] riscv: use invalidate/flush_*cache_range functions in cache.c
by Rick Chen 04 Jan '19

04 Jan '19

> > From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] > > Sent: Friday, January 04, 2019 8:38 AM > > To: u-boot(a)lists.denx.de > > Cc: Anup Patel; Lukas Auer; Rick Jian-Zhi Chen(陳建志); Bin Meng; Greentime Hu > > Subject: [PATCH v2 3/7] riscv: use invalidate/flush_*cache_range functions in > > cache.c > > > > The flush_cache() function in lib/cache.c ignores its arguments and flushes the > > complete data and instruction caches. Use the > > invalidate/flush_*cache_range() functions instead to only flush the requested > > memory region. > > > > This patch does not change the current behavior of U-Boot, since the > > implementation of the invalidate/flush_*cache_range() functions flush the > > complete data and instruction caches. It is in preparation for CPUs with the > > necessary functionality for flushing a selectable memory range. > > > > Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > > --- > > > > Changes in v2: > > - New patch "riscv: use invalidate/flush_*cache_range functions in cache.c" > > > > arch/riscv/lib/cache.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index > > 78b19da2c5..5437a122a1 100644 > > --- a/arch/riscv/lib/cache.c > > +++ b/arch/riscv/lib/cache.c > > @@ -40,8 +40,8 @@ void cache_flush(void) > > > > void flush_cache(unsigned long addr, unsigned long size) { > > - invalidate_icache_all(); > > - flush_dcache_all(); > > + invalidate_icache_range(addr, addr + size); > > + flush_dcache_range(addr, addr + size); > > } > > > > __weak void icache_enable(void) > > -- Reviewed-by: Rick Chen <rick(a)andestech.com>

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Re: [U-Boot] [PATCH v2 2/7] riscv: move the AX25-specific implementation of flush_dcache_all
by Rick Chen 04 Jan '19

04 Jan '19

> > From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] > > Sent: Friday, January 04, 2019 8:37 AM > > To: u-boot(a)lists.denx.de > > Cc: Anup Patel; Lukas Auer; Rick Jian-Zhi Chen(陳建志); Bin Meng; Greentime Hu > > Subject: [PATCH v2 2/7] riscv: move the AX25-specific implementation of > > flush_dcache_all > > > > The fence instruction is used to enforce device I/O and memory ordering > > constraints in RISC-V. It can not be relied on to directly affect the data cache on > > every CPU. > > Andes' AX25 does not have a coherence agent. Its fence instruction flushes the > > data cache and is used to keep data in the system coherent. > > The implementation of flush_dcache_all in lib/cache.c is therefore specific to the > > AX25. Move it into the AX25-specific cache.c in cpu/ax25/. > > > > This also adds a missing new line between flush_dcache_all and > > flush_dcache_range in lib/cache.c. > > > > Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > > --- > > > > Changes in v2: > > - Replace patch "riscv: remove invalid dcache flush implementation" with new > > patch "riscv: move the AX25-specific implementation of flush_dcache_all" > > > > arch/riscv/cpu/ax25/cache.c | 22 ++++++++++++++++++++++ > > arch/riscv/lib/cache.c | 10 ++++------ > > 2 files changed, 26 insertions(+), 6 deletions(-) > > > > diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index > > 8d6ae170b8..228fc55f56 100644 > > --- a/arch/riscv/cpu/ax25/cache.c > > +++ b/arch/riscv/cpu/ax25/cache.c > > @@ -6,6 +6,28 @@ > > > > #include <common.h> > > > > +void flush_dcache_all(void) > > +{ > > + /* > > + * Andes' AX25 does not have a coherence agent. U-Boot must use data > > + * cache flush and invalidate functions to keep data in the system > > + * coherent. > > + * The implementation of the fence instruction in the AX25 flushes the > > + * data cache and is used for this purpose. > > + */ > > + asm volatile ("fence" ::: "memory"); > > +} > > + > > +void flush_dcache_range(unsigned long start, unsigned long end) { > > + flush_dcache_all(); > > +} > > + > > +void invalidate_dcache_range(unsigned long start, unsigned long end) { > > + flush_dcache_all(); > > +} > > + > > void icache_enable(void) > > { > > #ifndef CONFIG_SYS_ICACHE_OFF > > diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index > > ae5c60716f..78b19da2c5 100644 > > --- a/arch/riscv/lib/cache.c > > +++ b/arch/riscv/lib/cache.c > > @@ -11,13 +11,12 @@ void invalidate_icache_all(void) > > asm volatile ("fence.i" ::: "memory"); } > > > > -void flush_dcache_all(void) > > +__weak void flush_dcache_all(void) > > { > > - asm volatile ("fence" :::"memory"); > > } > > -void flush_dcache_range(unsigned long start, unsigned long end) > > + > > +__weak void flush_dcache_range(unsigned long start, unsigned long end) > > { > > - flush_dcache_all(); > > } > > > > void invalidate_icache_range(unsigned long start, unsigned long end) @@ -29,9 > > +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long end) > > invalidate_icache_all(); > > } > > > > -void invalidate_dcache_range(unsigned long start, unsigned long end) > > +__weak void invalidate_dcache_range(unsigned long start, unsigned long > > +end) > > { > > - flush_dcache_all(); > > } > > > > void cache_flush(void) > > -- Reviewed-by: Rick Chen <rick(a)andestech.com>

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Re: [U-Boot] [PATCH 2/6] riscv: remove invalid dcache flush implementation
by Rick Chen 04 Jan '19

04 Jan '19

Hi Lukas > > From: Lukas Auer [mailto:lukas.auer@aisec.fraunhofer.de] > > Sent: Monday, December 31, 2018 2:28 AM > > To: u-boot(a)lists.denx.de > > Cc: Anup Patel; Lukas Auer; Rick Jian-Zhi Chen(陳建志); Bin Meng; Greentime Hu > > Subject: [PATCH 2/6] riscv: remove invalid dcache flush implementation > > > > The fence instruction is used to enforce device I/O and memory ordering > > constraints in RISC-V. It does not directly affect the data cache and particular > > cannot be used to flush or invalidate it. RISC-V does not have instructions for > > explicit cache control. Remove the flush_dcache_all implementation and its use > > in all dcache-specific functions in lib/cache.c. > > The privileged mention that fence is for the purposes of ordering, but does not say it can not be used to flush or invalidate. Andes's ax25 have no coherence agent. So it need fence instruction to manipulate cache flush or invalidate. Or there will be some data synchronization error occurs on ae350 platform. Thanks Rick > > This also adds a missing new line between flush_dcache_all and > > flush_dcache_range in lib/cache.c. > > > > Signed-off-by: Lukas Auer <lukas.auer(a)aisec.fraunhofer.de> > > --- > > This patch only removes the implementation itself and its use in dcache-specific > > functions in lib/cache.c. There are more uses of it in arch/riscv/, which this patch > > does not remove. > > > > arch/riscv/lib/cache.c | 4 +--- > > 1 file changed, 1 insertion(+), 3 deletions(-) > > > > diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index > > ae5c60716f..203e287612 100644 > > --- a/arch/riscv/lib/cache.c > > +++ b/arch/riscv/lib/cache.c > > @@ -13,11 +13,10 @@ void invalidate_icache_all(void) > > > > void flush_dcache_all(void) > > { > > - asm volatile ("fence" :::"memory"); > > } > > + > > void flush_dcache_range(unsigned long start, unsigned long end) { > > - flush_dcache_all(); > > } > > > > void invalidate_icache_range(unsigned long start, unsigned long end) @@ -31,7 > > +30,6 @@ void invalidate_icache_range(unsigned long start, unsigned long end) > > > > void invalidate_dcache_range(unsigned long start, unsigned long end) { > > - flush_dcache_all(); > > } > > > > void cache_flush(void) > > -- > > 2.20.1

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[U-Boot] [PATCH 1/1] LX2160AQDS: Adds SECURE_BOOT defconfig.
by Udit Agarwal 04 Jan '19

04 Jan '19

Configs added to enable secure boot on LX2160AQDS board. Signed-off-by: Udit Agarwal <udit.agarwal(a)nxp.com> --- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 90 ++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 configs/lx2160aqds_tfa_SECURE_BOOT_defconfig diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 0000000000..c53a7ac350 --- /dev/null +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2160AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_SECURE_BOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-qds" +CONFIG_NR_DRAM_BANKS=3 +CONFIG_DM=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_TFABOOT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_SERIAL=y +CONFIG_SERIAL_PROBE_ALL=y +CONFIG_CONS_INDEX=0 +CONFIG_FSL_CAAM=y +CONFIG_FSL_ESDHC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MICRON=y +CONFIG_SPI_FLASH_USE_4K_SECTORS=n +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_EON=y +CONFIG_NXP_FSPI=y +CONFIG_FSL_DSPI=y +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_SYS_FSPI_AHB_INIT=y +CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_PHY_GIGE=y +CONFIG_CMD_NET=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_FAT=y +CONFIG_CMD_EXT2=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LX=y +CONFIG_E1000=y +CONFIG_NET=y +CONFIG_DM_MMC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_STORAGE=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y +# CONFIG_SYS_FSL_DDR_PHY is not set +CONFIG_SYS_GEN2_DDR_PHY=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_PHYLIB_10G=y +CONFIG_PHY_AQUANTIA=y # X-M11-USXGMII +CONFIG_PHY_CORTINA=y # X-M7-40G +CONFIG_PHY_REALTEK=y # RGMII +CONFIG_PHY_INPHI=y # X-M8-100G +CONFIG_PHY_VITESSE=y # SGMII PEX RISER +CONFIG_HUSH_PARSER=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_AHCI=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y -- 2.17.1

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[U-Boot] Entry point used by SPL for uImages
by Daniel Glöckner 04 Jan '19

04 Jan '19

Hi, is there any reason why the SPL uses the load address of a uImage as entry point instead of the entry point value from the image header if SPL_COPY_PAYLOAD_ONLY is not set? Even the very first version of the SPL that was added 7.5 years ago did it that way. The SPL_COPY_PAYLOAD_ONLY case that was added one year later behaves as I would expect. Best regards, Daniel

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[U-Boot] [PATCH v2 0/7] Small fixes for RISC-V
by Lukas Auer 04 Jan '19

04 Jan '19

This patch series contains small fixes for RISC-V. It touches three areas. - Patch 1 clarifies the error message on undefined exceptions. - Patch 2 removes the current dcache flush implementation. It uses the fence instruction, which does not directly affect the data cache and can therefore not be used to implement dcache flush and invalidation. - Patches 3-6 improve support for standalone applications. They add support for RV64I systems and fix a problem, where a callee-saved register is used without saving it beforehand. Patch 6 defines the standalone load address for qemu-riscv to allow it to run standalone applications. Changes in v2: - Replace patch "riscv: remove invalid dcache flush implementation" with new patch "riscv: move the AX25-specific implementation of flush_dcache_all" - New patch "riscv: use invalidate/flush_*cache_range functions in cache.c" Lukas Auer (7): riscv: clarify error message on undefined exceptions riscv: move the AX25-specific implementation of flush_dcache_all riscv: use invalidate/flush_*cache_range functions in cache.c riscv: remove RISC-V standalone linker script riscv: replace use of callee-saved register in standalone riscv: support standalone applications on RV64I systems riscv: qemu: define standalone load address arch/riscv/config.mk | 3 +-- arch/riscv/cpu/ax25/cache.c | 22 +++++++++++++++++++ arch/riscv/lib/cache.c | 14 ++++++------ arch/riscv/lib/interrupts.c | 3 ++- examples/standalone/riscv.lds | 40 ----------------------------------- examples/standalone/stubs.c | 21 +++++++++++++----- include/configs/qemu-riscv.h | 2 ++ 7 files changed, 49 insertions(+), 56 deletions(-) delete mode 100644 examples/standalone/riscv.lds -- 2.20.1

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[U-Boot] [PATCH] dm: usb: gadget: Fix boot breakage on sunxi platforms
by Jean-Jacques Hiblot 04 Jan '19

04 Jan '19

Fixes commit 013116243950 ("dm: usb: create a new UCLASS ID for USB gadget devices") The UCLASS_DRIVER for id UCLASS_USB_GADGET_GENERIC needs to be declared even for platforms that do not enable DM_USB_GADGET. Otherwise the driver for their usb peripheral controller fails to bind. Reported-by: Priit Laes <plaes(a)plaes.org> Reported-by: Jagan Teki <jagan(a)amarulasolutions.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot(a)ti.com> Tested-by: Priit Laes <plaes(a)plaes.org> --- build status available here: https://travis-ci.org/jjhiblot/u-boot/builds/470396811 drivers/usb/gadget/udc/Makefile | 3 ++- drivers/usb/gadget/udc/udc-uclass.c | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile index 38ac2dd..95dbf0c 100644 --- a/drivers/usb/gadget/udc/Makefile +++ b/drivers/usb/gadget/udc/Makefile @@ -6,4 +6,5 @@ ifndef CONFIG_$(SPL_)DM_USB_GADGET obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o endif -obj-$(CONFIG_$(SPL_)DM_USB_GADGET) += udc-uclass.o udc-core.o +obj-$(CONFIG_$(SPL_)DM_USB_GADGET) += udc-core.o +obj-$(CONFIG_$(SPL_)DM) += udc-uclass.o diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c index e9f8f5f..8d78647 100644 --- a/drivers/usb/gadget/udc/udc-uclass.c +++ b/drivers/usb/gadget/udc/udc-uclass.c @@ -9,6 +9,7 @@ #include <dm/device-internal.h> #include <linux/usb/gadget.h> +#if CONFIG_IS_ENABLED(DM_USB_GADGET) #define MAX_UDC_DEVICES 4 static struct udevice *dev_array[MAX_UDC_DEVICES]; int usb_gadget_initialize(int index) @@ -51,6 +52,7 @@ int usb_gadget_handle_interrupts(int index) return -EINVAL; return dm_usb_gadget_handle_interrupts(dev_array[index]); } +#endif UCLASS_DRIVER(usb_gadget_generic) = { .id = UCLASS_USB_GADGET_GENERIC, -- 2.7.4

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[U-Boot] [PATCH] fdt: Fix string property comparison overflow
by Teddy Reed 03 Jan '19

03 Jan '19

FDT property searching can overflow when comparing strings. This will result in undefined behavior. This upstream patch adds checks to assure property name lengths do not overrun the string region or the totalsize. The implementation is from upstream dtc: 70166d62a27f libfdt: Safer access to strings section Cc: Peter Robinson <pbrobinson(a)gmail.com> Cc: David Gibson <david(a)gibson.dropbear.id.au> Signed-off-by: Teddy Reed <teddy.reed(a)gmail.com> --- Note this file is not synchronized from upstream dtc when using the scripts/dtc/update-dtc-source.sh script. The file size of the ELF increases with sandbox_spl_defconfig. $ bloaty spl/u-boot-spl -- spl/u-boot-spl.bin.before VM SIZE FILE SIZE -------------- -------------- [ = ] 0 .debug_loc +948 +0.3% [ = ] 0 .debug_info +284 +0.0% +0.5% +176 .text +176 +0.5% [ = ] 0 .debug_line +150 +0.2% [ = ] 0 .debug_ranges +48 +0.2% +0.4% +40 .eh_frame +40 +0.4% [ = ] 0 .debug_str +20 +0.0% [ = ] 0 .debug_aranges +16 +0.1% +59% +16 [LOAD [RX]] +16 +59% [ = ] 0 .strtab +4 +0.0% [ = ] 0 [Unmapped] -238 -18.1% +0.3% +232 TOTAL +1.43Ki +0.1% $ du -b spl/u-boot-spl.bin spl/u-boot-spl.bin.before 2174032 spl/u-boot-spl.bin 2174032 spl/u-boot-spl.bin.before You could also apply the patch: @@ -42,6 +42,11 @@ const char *fdt_string(const void *fdt, int stroffset) static int _fdt_string_eq(const void *fdt, int stroffset, const char *s, int len) { + int total_off = fdt_off_dt_strings(fdt) + stroffset; + if (total_off + len + 1 < total_off || + total_off + len + 1 > fdt_totalsize(fdt)) + return 0; + const char *p = fdt_string(fdt, stroffset); return (strnlen(p, len + 1) == len) && (memcmp(p, s, len) == 0); To mitigate the read overflow, with minimum added bytes. I proposed this along with another change [1]. This was not a good idea since the change to scripts/dtc/libfdt/fdt.c is part of dtc synchronized from upsteam. [1] https://lists.denx.de/pipermail/u-boot/2018-June/330488.html lib/libfdt/fdt_ro.c | 61 ++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 58 insertions(+), 3 deletions(-) diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c index b6ca4e0b0c..f67dcb7fc9 100644 --- a/lib/libfdt/fdt_ro.c +++ b/lib/libfdt/fdt_ro.c @@ -34,17 +34,72 @@ static int _fdt_nodename_eq(const void *fdt, int offset, return 0; } +const char *fdt_get_string(const void *fdt, int stroffset, int *lenp) +{ + uint32_t absoffset = stroffset + fdt_off_dt_strings(fdt); + size_t len; + int err; + const char *s, *n; + + err = fdt_check_header(fdt); + if (err != 0) + goto fail; + + err = -FDT_ERR_BADOFFSET; + if (absoffset >= fdt_totalsize(fdt)) + goto fail; + len = fdt_totalsize(fdt) - absoffset; + + if (fdt_magic(fdt) == FDT_MAGIC) { + if (stroffset < 0) + goto fail; + if (fdt_version(fdt) >= 17) { + if (stroffset >= fdt_size_dt_strings(fdt)) + goto fail; + if ((fdt_size_dt_strings(fdt) - stroffset) < len) + len = fdt_size_dt_strings(fdt) - stroffset; + } + } else if (fdt_magic(fdt) == FDT_SW_MAGIC) { + if ((stroffset >= 0) + || (stroffset < -fdt_size_dt_strings(fdt))) + goto fail; + if ((-stroffset) < len) + len = -stroffset; + } else { + err = -FDT_ERR_INTERNAL; + goto fail; + } + + s = (const char *)fdt + absoffset; + n = memchr(s, '\0', len); + if (!n) { + /* missing terminating NULL */ + err = -FDT_ERR_TRUNCATED; + goto fail; + } + + if (lenp) + *lenp = n - s; + return s; + +fail: + if (lenp) + *lenp = err; + return NULL; +} + const char *fdt_string(const void *fdt, int stroffset) { - return (const char *)fdt + fdt_off_dt_strings(fdt) + stroffset; + return fdt_get_string(fdt, stroffset, NULL); } static int _fdt_string_eq(const void *fdt, int stroffset, const char *s, int len) { - const char *p = fdt_string(fdt, stroffset); + int slen; + const char *p = fdt_get_string(fdt, stroffset, &slen); - return (strnlen(p, len + 1) == len) && (memcmp(p, s, len) == 0); + return p && (slen == len) && (memcmp(p, s, len) == 0); } uint32_t fdt_get_max_phandle(const void *fdt) -- 2.17.1

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