January 2019 - U-Boot

[U-Boot] [PATCH v1 0/9] arm: Colibri iMX7 fixes and DM_MMC conversion
by Stefan Agner 07 Jan '19

07 Jan '19

From: Stefan Agner <stefan.agner(a)toradex.com> This patchset fixes some small issues with Colibri iMX7 and converts the board to use DM_MMC. It also adds the so far missing configuration for the eMMC variant. This patchset gets rid of all but one deprecation warning. The remaining warning is due to CONFIG_USB still being used. Fixing this is not entirly trivial due to missing GPIO host/ peripheral switch capabilities and will be tackled later. -- Stefan Stefan Agner (9): colibri_imx7: fix boot commands arm: dts: imx7: colibri: split dt for raw NAND and eMMC devices configs: colibri_imx7: enable DM for raw NAND devices configs: colibri_imx7: use separate device tree arm: dts: imx7: colibri: add usdhci peripherals to device tree configs: colibri_imx7: use DM_MMC colibri_imx7: drop legacy usdhc support configs: colibri_imx7: enable CAAM driver configs: add default configuraiton for Colibri iMX7 with eMMC arch/arm/dts/imx7-colibri-emmc.dts | 85 ++++++++++++++++ arch/arm/dts/imx7-colibri-rawnand.dts | 50 ++++++++++ .../{imx7-colibri.dts => imx7-colibri.dtsi} | 67 ++++++------- board/toradex/colibri_imx7/MAINTAINERS | 3 + board/toradex/colibri_imx7/colibri_imx7.c | 97 ------------------- configs/colibri_imx7_defconfig | 12 ++- configs/colibri_imx7_emmc_defconfig | 65 +++++++++++++ include/configs/colibri_imx7.h | 5 +- 8 files changed, 244 insertions(+), 140 deletions(-) create mode 100644 arch/arm/dts/imx7-colibri-emmc.dts create mode 100644 arch/arm/dts/imx7-colibri-rawnand.dts rename arch/arm/dts/{imx7-colibri.dts => imx7-colibri.dtsi} (68%) create mode 100644 configs/colibri_imx7_emmc_defconfig -- 2.20.1

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[U-Boot] [PATCH v2] spi: soft_spi: Fix for soft_spi
by Horatiu Vultur 07 Jan '19

07 Jan '19

This patch series, fix a null ptr inside soft_spi. This version address comments from Jagan Teki <jagan(a)amarulasolutions.com> v2 changes: - update soft_spi_platdata inside .set_mode. Horatiu Vultur (1): spi: soft_spi: Fix null ptr when probing soft_spi. drivers/spi/soft_spi.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) -- 2.7.4

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[U-Boot] [V3] please pull u-boot-samsung master
by Minkyu Kang 07 Jan '19

07 Jan '19

Hi, The following changes since commit 1f2e948d6d53f77a2ddb2dde3531b0d5bc2815ad: Prepare v2019.01-rc2 (2018-12-17 20:25:24 -0500) are available in the git repository at: git://git.denx.de/u-boot-samsung master for you to fetch changes up to df1ff4d6ba591a5fcb9549e895b23c781d8fda6d: exynos: Leave the compiler to choose the register to avoid possible r0 corruption (2019-01-04 17:28:50 +0900) ---------------------------------------------------------------- Anand Moon (2): exynos5-dt-types: add missing dtb file for Odroid HC1/HC2 odroid: Update README.odroid for support of Odroid HC1 Guillaume GARDET (3): exynos: imply SYS_THUMB_BUILD exynos: allow SPL to build in thumb mode exynos: Leave the compiler to choose the register to avoid possible r0 corruption Seung-Woo Kim (1): Revert "arm: config: fix default console only to specify the device" arch/arm/Kconfig | 1 + arch/arm/mach-exynos/include/mach/system.h | 2 +- doc/README.odroid | 7 +++++-- include/configs/odroid.h | 4 ++-- include/configs/odroid_xu3.h | 5 +++-- include/configs/s5p_goni.h | 4 ++-- include/configs/s5pc210_universal.h | 4 ++-- include/configs/trats.h | 4 ++-- include/configs/trats2.h | 4 ++-- 9 files changed, 20 insertions(+), 15 deletions(-) -- Thanks, Minkyu Kang.

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[U-Boot] [PULL] Please pull u-boot-rockchip
by Philipp Tomsich 07 Jan '19

07 Jan '19

The following changes since commit 53240275666acf32cb9811e44eaf2fd571a6cb75: Merge tag 'for-v2019.01' of git://git.denx.de/u-boot-video (2019-01-03 15:34:44 -0500) are available in the git repository at: git://git.denx.de/u-boot-rockchip.git tags/for-master-20190106 for you to fetch changes up to 33502f371d49161a66f7c1f3752dbfc1358129c0: rockchip: rk3399: fix missing braces in full pinctrl (2019-01-06 15:26:31 +0100) ---------------------------------------------------------------- Fixes: - rockchip: rk3399: fix missing braces in full pinctrl ---------------------------------------------------------------- Philipp Tomsich (1): rockchip: rk3399: fix missing braces in full pinctrl drivers/pinctrl/rockchip/pinctrl_rk3399.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)

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[U-Boot] [PATCH 0/2] mips: spi: mscc: Add fast bitbang SPI driver
by Lars Povlsen 07 Jan '19

07 Jan '19

These 2 patches add an optimized SPI bitbang driver for MSCC SOCs that does not sport the designware SPI hardware controller. The driver more than doubles the performance for bulk SPI transfers. This is based off the u-boot-mips/next repository. Lars Povlsen (2): mips: spi: mscc: Add fast bitbang SPI driver mips: mscc: DT: Update luton device tree to use fast SPI driver MAINTAINERS | 1 + arch/mips/dts/mscc,luton.dtsi | 15 +- configs/mscc_luton_defconfig | 3 +- drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mscc_bb_spi.c | 258 ++++++++++++++++++++++++++++++++++ 6 files changed, 271 insertions(+), 14 deletions(-) create mode 100644 drivers/spi/mscc_bb_spi.c -- 2.19.2

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[U-Boot] [GIT] Pull request: u-boot-dfu (04.01.2019)
by Lukasz Majewski 07 Jan '19

07 Jan '19

Dear Marek, The following changes since commit 7436f5e54d35bcad53befec90e2e67288071f74e: Merge tag 'for-master-20190103' of git://git.denx.de/u-boot-rockchip (2019-01-03 08:39:44 -0500) are available in the git repository at: git://git.denx.de/u-boot-dfu.git for you to fetch changes up to deb73d0aea6ca09ecb56ea3431d3151427fff4a4: dm: usb: gadget: Fix boot breakage on sunxi platforms (2019-01-03 22:43:02 +0100) ---------------------------------------------------------------- Jean-Jacques Hiblot (3): dm: usb: udc: Use SEQ_ALIAS to index the USB gadget ports ARM: dts: define USB aliases for all omap5 platforms dm: usb: gadget: Fix boot breakage on sunxi platforms arch/arm/dts/omap5-u-boot.dtsi | 5 +++++ drivers/usb/gadget/udc/Makefile | 3 ++- drivers/usb/gadget/udc/udc-uclass.c | 7 +++++-- 3 files changed, 12 insertions(+), 3 deletions(-) Travis-Ci: https://travis-ci.org/lmajewski/u-boot-dfu/builds/475053011 Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma(a)denx.de

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[U-Boot] [PATCH] mmc: fsl_esdhc: Fix wp_enable issue
by Ye Li 07 Jan '19

07 Jan '19

The wp-gpios property is used for gpio, if this is set, the WP pin is muxed to gpio function, can't be used as internal WP checking. However the codes remain to use internal WP checking. This patch changes to examine the "fsl,wp-controller" for enabling internal WP checking, and "wp-gpios" for muxing to gpio. Signed-off-by: Ye Li <ye.li(a)nxp.com> --- drivers/mmc/fsl_esdhc.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 87273c8..4e10f13 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -297,6 +297,13 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); return -ETIMEDOUT; } + } else { +#ifdef CONFIG_DM_GPIO + if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) { + printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); + return -ETIMEDOUT; + } +#endif } esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK, @@ -1455,14 +1462,15 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif } - priv->wp_enable = 1; - + if (dev_read_prop(dev, "fsl,wp-controller", NULL)) { + priv->wp_enable = 1; + } else { + priv->wp_enable = 0; #ifdef CONFIG_DM_GPIO - ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, + gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); - if (ret) - priv->wp_enable = 0; #endif + } priv->vs18_enable = 0; -- 2.7.4

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[U-Boot] [PATCH V2] i2c: xiic: Add Xilinx AXI I2C driver
by Marek Vasut 07 Jan '19

07 Jan '19

Add Xilinx AXI I2C controller driver based on the Linux i2c-xiic driver. This driver is stripped of all the IRQ handling and uses pure polling, yet tries to retain most of the structure of the Linux driver to make backporting of fixes easy. Note that the IP has a known limitation on 255 bytes read and write, according to xilinx this is still being worked on [1]. [1] https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI-IIC-V2-0-… Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Michal Simek <monstr(a)monstr.eu> Cc: Michal Simek <michal.simek(a)xilinx.com> Cc: Heiko Schocher <hs(a)denx.de> --- V2: - Sort Makefile - Fix formatting in Kconfig --- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/xilinx_xiic.c | 340 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 347 insertions(+) create mode 100644 drivers/i2c/xilinx_xiic.c diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 1ef22e6bcd..536617115a 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -450,6 +450,12 @@ config SYS_I2C_BUS_MAX help Define the maximum number of available I2C buses. +config SYS_I2C_XILINX_XIIC + bool "Xilinx AXI I2C driver" + depends on DM_I2C + help + Support for Xilinx AXI I2C controller. + config SYS_I2C_ZYNQ bool "Xilinx I2C driver" depends on ARCH_ZYNQMP || ARCH_ZYNQ diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index d3637bcd8d..ec2d1964c3 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o +obj-$(CONFIG_SYS_I2C_XILINX_XIIC) += xilinx_xiic.o obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o diff --git a/drivers/i2c/xilinx_xiic.c b/drivers/i2c/xilinx_xiic.c new file mode 100644 index 0000000000..83114ed510 --- /dev/null +++ b/drivers/i2c/xilinx_xiic.c @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Xilinx AXI I2C driver + * + * Copyright (C) 2018 Marek Vasut <marex(a)denx.de> + * + * Based on Linux 4.14.y i2c-xiic.c + * Copyright (c) 2002-2007 Xilinx Inc. + * Copyright (c) 2009-2010 Intel Corporation + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <i2c.h> +#include <wait_bit.h> +#include <asm/io.h> + +struct xilinx_xiic_priv { + void __iomem *base; + struct clk clk; +}; + +#define XIIC_MSB_OFFSET 0 +#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) + +/* + * Register offsets in bytes from RegisterBase. Three is added to the + * base offset to access LSB (IBM style) of the word + */ +#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ +#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ +#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ +#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ +#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ +#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ +#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ +#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ +#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ +#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ + +/* Control Register masks */ +#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ +#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ +#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ +#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ +#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ +#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ +#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ + +/* Status Register masks */ +#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ +#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ +#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ +#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ +#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ +#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ +#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ +#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ + +/* Interrupt Status Register masks Interrupt occurs when... */ +#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ +#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ +#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ +#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ +#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ +#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ +#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ +#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ + +/* The following constants specify the depth of the FIFOs */ +#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ +#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ + +/* + * Tx Fifo upper bit masks. + */ +#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ +#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ + +/* + * The following constants define the register offsets for the Interrupt + * registers. There are some holes in the memory map for reserved addresses + * to allow other registers to be added and still match the memory map of the + * interrupt controller registers + */ +#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ +#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ +#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ +#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ + +#define XIIC_RESET_MASK 0xAUL + +static u8 i2c_8bit_addr_from_flags(uint addr, u16 flags) +{ + return (addr << 1) | (flags & I2C_M_RD ? 1 : 0); +} + +static void xiic_irq_clr(struct xilinx_xiic_priv *priv, u32 mask) +{ + u32 isr = readl(priv->base + XIIC_IISR_OFFSET); + + writel(isr & mask, priv->base + XIIC_IISR_OFFSET); +} + +static int xiic_read_rx(struct xilinx_xiic_priv *priv, + struct i2c_msg *msg, int nmsgs) +{ + u8 bytes_in_fifo; + u32 pos = 0; + int i, ret; + + while (pos < msg->len) { + ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, + XIIC_SR_RX_FIFO_EMPTY_MASK, false, + 1000, true); + if (ret) + return ret; + + bytes_in_fifo = readb(priv->base + XIIC_RFO_REG_OFFSET) + 1; + + if (bytes_in_fifo > msg->len) + bytes_in_fifo = msg->len; + + for (i = 0; i < bytes_in_fifo; i++) { + msg->buf[pos++] = readb(priv->base + + XIIC_DRR_REG_OFFSET); + } + } + + return 0; +} + +static int xiic_tx_fifo_space(struct xilinx_xiic_priv *priv) +{ + /* return the actual space left in the FIFO */ + return IIC_TX_FIFO_DEPTH - readb(priv->base + XIIC_TFO_REG_OFFSET) - 1; +} + +static void xiic_fill_tx_fifo(struct xilinx_xiic_priv *priv, + struct i2c_msg *msg, int nmsgs) +{ + u8 fifo_space = xiic_tx_fifo_space(priv); + int len = msg->len; + u32 pos = 0; + + len = (len > fifo_space) ? fifo_space : len; + + while (len--) { + u16 data = msg->buf[pos++]; + + if (pos == len && nmsgs == 1) { + /* last message in transfer -> STOP */ + data |= XIIC_TX_DYN_STOP_MASK; + } + writew(data, priv->base + XIIC_DTR_REG_OFFSET); + } +} + +static void xilinx_xiic_set_addr(struct udevice *dev, u8 addr, + u16 flags, u32 len, u32 nmsgs) +{ + struct xilinx_xiic_priv *priv = dev_get_priv(dev); + + xiic_irq_clr(priv, XIIC_INTR_TX_ERROR_MASK); + + if (!(flags & I2C_M_NOSTART)) { + /* write the address */ + u16 data = i2c_8bit_addr_from_flags(addr, flags) | + XIIC_TX_DYN_START_MASK; + if (nmsgs == 1 && len == 0) + /* no data and last message -> add STOP */ + data |= XIIC_TX_DYN_STOP_MASK; + + writew(data, priv->base + XIIC_DTR_REG_OFFSET); + } +} + +static int xilinx_xiic_read_common(struct udevice *dev, struct i2c_msg *msg, + u32 nmsgs) +{ + struct xilinx_xiic_priv *priv = dev_get_priv(dev); + u8 rx_watermark; + + /* Clear and enable Rx full interrupt. */ + xiic_irq_clr(priv, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); + + /* we want to get all but last byte, because the TX_ERROR IRQ is used + * to inidicate error ACK on the address, and negative ack on the last + * received byte, so to not mix them receive all but last. + * In the case where there is only one byte to receive + * we can check if ERROR and RX full is set at the same time + */ + rx_watermark = msg->len; + if (rx_watermark > IIC_RX_FIFO_DEPTH) + rx_watermark = IIC_RX_FIFO_DEPTH; + + writeb(rx_watermark - 1, priv->base + XIIC_RFD_REG_OFFSET); + + xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs); + + xiic_irq_clr(priv, XIIC_INTR_BNB_MASK); + + writew((msg->len & 0xff) | ((nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0), + priv->base + XIIC_DTR_REG_OFFSET); + + if (nmsgs == 1) + /* very last, enable bus not busy as well */ + xiic_irq_clr(priv, XIIC_INTR_BNB_MASK); + + return xiic_read_rx(priv, msg, nmsgs); +} + +static int xilinx_xiic_write_common(struct udevice *dev, struct i2c_msg *msg, + int nmsgs) +{ + struct xilinx_xiic_priv *priv = dev_get_priv(dev); + int ret; + + xilinx_xiic_set_addr(dev, msg->addr, msg->flags, msg->len, nmsgs); + xiic_fill_tx_fifo(priv, msg, nmsgs); + + ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, + XIIC_SR_TX_FIFO_EMPTY_MASK, false, 1000, true); + if (ret) + return ret; + + /* Clear any pending Tx empty, Tx Error and then enable them. */ + xiic_irq_clr(priv, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | + XIIC_INTR_BNB_MASK); + + return 0; +} + +static void xiic_clear_rx_fifo(struct xilinx_xiic_priv *priv) +{ + u8 sr; + + for (sr = readb(priv->base + XIIC_SR_REG_OFFSET); + !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); + sr = readb(priv->base + XIIC_SR_REG_OFFSET)) + readb(priv->base + XIIC_DRR_REG_OFFSET); +} + +static void xiic_reinit(struct xilinx_xiic_priv *priv) +{ + writel(XIIC_RESET_MASK, priv->base + XIIC_RESETR_OFFSET); + + /* Set receive Fifo depth to maximum (zero based). */ + writeb(IIC_RX_FIFO_DEPTH - 1, priv->base + XIIC_RFD_REG_OFFSET); + + /* Reset Tx Fifo. */ + writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); + + /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ + writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); + + /* make sure RX fifo is empty */ + xiic_clear_rx_fifo(priv); + + /* Disable interrupts */ + writel(0, priv->base + XIIC_DGIER_OFFSET); + + xiic_irq_clr(priv, XIIC_INTR_ARB_LOST_MASK); +} + +static int xilinx_xiic_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) +{ + int ret = 0; + + for (; nmsgs > 0; nmsgs--, msg++) { + if (msg->flags & I2C_M_RD) + ret = xilinx_xiic_read_common(dev, msg, nmsgs); + else + ret = xilinx_xiic_write_common(dev, msg, nmsgs); + + if (ret) + return -EREMOTEIO; + } + + return ret; +} + +static int xilinx_xiic_probe_chip(struct udevice *dev, uint addr, uint flags) +{ + struct xilinx_xiic_priv *priv = dev_get_priv(dev); + u32 reg; + int ret; + + xiic_reinit(priv); + + xilinx_xiic_set_addr(dev, addr, 0, 0, 1); + ret = wait_for_bit_8(priv->base + XIIC_SR_REG_OFFSET, + XIIC_SR_BUS_BUSY_MASK, false, 1000, true); + if (ret) + return ret; + + reg = readl(priv->base + XIIC_IISR_OFFSET); + if (reg & XIIC_INTR_TX_ERROR_MASK) + return -ENODEV; + + return 0; +} + +static int xilinx_xiic_set_speed(struct udevice *dev, uint speed) +{ + return 0; +} + +static int xilinx_xiic_probe(struct udevice *dev) +{ + struct xilinx_xiic_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); + xiic_reinit(priv); + + return 0; +} + +static const struct dm_i2c_ops xilinx_xiic_ops = { + .xfer = xilinx_xiic_xfer, + .probe_chip = xilinx_xiic_probe_chip, + .set_bus_speed = xilinx_xiic_set_speed, +}; + +static const struct udevice_id xilinx_xiic_ids[] = { + { .compatible = "xlnx,xps-iic-2.00.a" }, + { } +}; + +U_BOOT_DRIVER(xilinx_xiic) = { + .name = "xilinx_axi_i2c", + .id = UCLASS_I2C, + .of_match = xilinx_xiic_ids, + .probe = xilinx_xiic_probe, + .priv_auto_alloc_size = sizeof(struct xilinx_xiic_priv), + .ops = &xilinx_xiic_ops, +}; -- 2.18.0

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[U-Boot] [PATCH v2 00/14] efi: make efi and bootmgr more usable
by AKASHI Takahiro 07 Jan '19

07 Jan '19

This patch set is a collection of patches to enhance efi user interfaces /commands. It will help improve user experience on efi boot and make it more usable *without* edk2's shell utility. Let's see how it works: => efishell boot add 1 SHELL mmc 0:1 /Shell.efi "" => efishell boot add 2 HELLO mmc 0:1 /hello.efi "" => efishell boot dump Boot0001: attributes: A-- (0x00000001) label: SHELL file_path: /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/SD(0)/SD(0)/HD(1,MBR,0x086246ba,0x800,0x40000)/\\Shell.efi data: Boot0002: attributes: A-- (0x00000001) label: HELLO file_path: /VenHw(e61d73b9-a384-4acc-aeab-82e828f3628b)/SD(0)/SD(0)/HD(1,MBR,0x086246ba,0x800,0x40000)/\\hello.efi data: => efishell boot order 1 2 => efishell boot order 1: Boot0001: SHELL 2: Boot0002: HELLO => run -e Boot0002 (or bootefi bootmgr - 2) ; '-' means no dtb specified WARNING: booting without device tree Booting: HELLO ## Starting EFI application at 000000007db8b040 ... Hello, world! ## Application terminated, r = 0 => env set -e PlatformLang en ; important! (or you can do "efishell setvar PlatformLang en") => env print -e Boot0001: {boot,run}(blob) 00000000: 01 00 00 00 68 00 53 00 ....h.S. 00000010: 48 00 45 00 4c 00 4c 00 H.E.L.L. 00000020: 00 00 01 04 14 00 b9 73 .......s 00000030: 1d e6 84 a3 cc 4a ae ab .....J.. 00000040: 82 e8 28 f3 62 8b 03 1a ..(.b... 00000050: 05 00 00 03 1a 05 00 00 ........ 00000060: 04 01 2a 00 01 00 00 00 ..*..... 00000070: 00 08 00 00 00 00 00 00 ........ 00000080: 00 00 04 00 00 00 00 00 ........ 00000090: ba 46 62 08 00 00 00 00 .Fb..... 000000a0: 00 00 00 00 00 00 00 00 ........ 000000b0: 01 01 04 04 1c 00 5c 00 ......\. 000000c0: 5c 00 53 00 68 00 65 00 \.S.h.e. 000000d0: 6c 00 6c 00 2e 00 65 00 l.l...e. 000000e0: 66 00 69 00 00 00 7f ff f.i.... 000000f0: 04 00 00 ... Boot0002: {boot,run}(blob) 00000000: 01 00 00 00 68 00 48 00 ....h.H. 00000010: 45 00 4c 00 4c 00 4f 00 E.L.L.O. 00000020: 00 00 01 04 14 00 b9 73 .......s 00000030: 1d e6 84 a3 cc 4a ae ab .....J.. 00000040: 82 e8 28 f3 62 8b 03 1a ..(.b... 00000050: 05 00 00 03 1a 05 00 00 ........ 00000060: 04 01 2a 00 01 00 00 00 ..*..... 00000070: 00 08 00 00 00 00 00 00 ........ 00000080: 00 00 04 00 00 00 00 00 ........ 00000090: ba 46 62 08 00 00 00 00 .Fb..... 000000a0: 00 00 00 00 00 00 00 00 ........ 000000b0: 01 01 04 04 1c 00 5c 00 ......\. 000000c0: 5c 00 68 00 65 00 6c 00 \.h.e.l. 000000d0: 6c 00 6f 00 2e 00 65 00 l.o...e. 000000e0: 66 00 69 00 00 00 7f ff f.i.... 000000f0: 04 00 00 ... BootOrder: {boot,run}(blob) 00000000: 01 00 02 00 .... OsIndicationsSupported: {ro,boot}(blob) 00000000: 00 00 00 00 00 00 00 00 ........ PlatformLang: {boot,run}(blob) 00000000: 65 6e en => run -e Boot0001 or bootefi bootmgr (shell ...) "setvar" command now supports efi shell-like syntax: => env set -e foo =S\"akashi\" =0x012345 =Habcdef => env print -e foo foo: {boot,run}(blob) 00000000: 61 6b 61 73 68 69 45 23 akashiE# 00000010: 01 00 ab cd ef ..... Other useful sub commands are: => efishell devices ; print uefi devices => efishell drivers ; print uefi drivers => efishell images ; print loaded images => efishell dh ; print uefi handles => efishell memmap ; dump uefi memory map # I admit there is some room to improve the output from those commands. Enjoy! -Takahiro Akashi Changes in v2 (Nov 5, 2018) * modify efi_dp_from_name() for use in efishell * rename efi_marshal_load_option() to efi_serialize_load_option(), taking a "struct efi_load_option" as an argument * improve a format in dumping uefi variables * enhance a setvar syntax as efi's shell does * change a syntax from "bootefi bootmgr -2" to "bootefi bootmgr - 2" * add -e option to run command * add -e option to env command * add more sub-commands AKASHI Takahiro (14): efi_loader: allow device == NULL in efi_dp_from_name() efi_loader: bootmgr: add load option helper functions efi_loader: bootmgr: allow for running a given load option cmd: add efishell command cmd: efishell: add devices command cmd: efishell: add drivers command cmd: efishell: add images command cmd: efishell: add memmap command cmd: efishell: add dh command cmd: bootefi: carve out fdt parameter handling cmd: bootefi: run an EFI application of a specific load option cmd: run: add "-e" option to run an EFI application cmd: efishell: export uefi variable helper functions cmd: env: add "-e" option for handling UEFI variables cmd/Makefile | 2 +- cmd/bootefi.c | 71 ++- cmd/efishell.c | 970 +++++++++++++++++++++++++++++++ cmd/efishell.h | 6 + cmd/nvedit.c | 63 +- common/cli.c | 30 + include/command.h | 5 + include/efi_loader.h | 26 +- lib/efi_loader/efi_bootmgr.c | 101 ++-- lib/efi_loader/efi_device_path.c | 11 +- 10 files changed, 1223 insertions(+), 62 deletions(-) create mode 100644 cmd/efishell.c create mode 100644 cmd/efishell.h -- 2.19.0

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[U-Boot] [PATCH 1/1] efi_loader: CMD_BOOTEFI_HELLO_COMPILE in configs
by Heinrich Schuchardt 07 Jan '19

07 Jan '19

It should not be necessary to adjust CMD_BOOTEFI_HELLO_COMPILE in config files. arch/arm/lib/crt0_arm_efi.S cannot be compiled in thumbs mode. We can disable CMD_BOOTEFI_HELLO_COMPILE for CONFIG_CPU_V7M. So there is no longer a need to disable it in stm32 configs. helloworld.efi can be built without problems on x86_64. So there is no need to disable it in chromebook_link64_defconfig and qemu-x86_64_defconfig. Same is true for ARM V7A. So do not disable CMD_BOOTEFI_HELLO_COMPILE in kp_imx6q_tpc_defconfig. Some architecture checks are already make for EFI_LOADER. There is no need to repeat them for CMD_BOOTEFI_HELLO_COMPILE Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- cmd/Kconfig | 2 +- configs/chromebook_link64_defconfig | 1 - configs/kp_imx6q_tpc_defconfig | 1 - configs/qemu-x86_64_defconfig | 1 - configs/stm32f429-discovery_defconfig | 1 - configs/stm32f429-evaluation_defconfig | 1 - configs/stm32f469-discovery_defconfig | 1 - 7 files changed, 1 insertion(+), 7 deletions(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index ea1a325eb3..3ea42e4256 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -226,7 +226,7 @@ config CMD_BOOTEFI config CMD_BOOTEFI_HELLO_COMPILE bool "Compile a standard EFI hello world binary for testing" - depends on CMD_BOOTEFI && (ARM || X86 || RISCV) + depends on CMD_BOOTEFI && !CPU_V7M && !SANDBOX default y help This compiles a standard EFI hello world application with U-Boot so diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig index 074d333dd4..12f26570af 100644 --- a/configs/chromebook_link64_defconfig +++ b/configs/chromebook_link64_defconfig @@ -38,7 +38,6 @@ CONFIG_SPL_PCH_SUPPORT=y CONFIG_SPL_RTC_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y -# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_SF=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 5ebbe1dc7c..7689f71101 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -20,7 +20,6 @@ CONFIG_SPL_RAW_IMAGE_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR="." -# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set # CONFIG_CMD_ELF is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig index 8d43acd480..34acc09317 100644 --- a/configs/qemu-x86_64_defconfig +++ b/configs/qemu-x86_64_defconfig @@ -36,7 +36,6 @@ CONFIG_SPL_PCH_SUPPORT=y CONFIG_SPL_RTC_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y -# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_BOOTEFI_SELFTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_IDE=y diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index ef0f6f7373..52fa31ffe5 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -15,7 +15,6 @@ CONFIG_MISC_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " -# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_IMLS=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIMER=y diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig index 6a2ed2a9b0..cb11b5230d 100644 --- a/configs/stm32f429-evaluation_defconfig +++ b/configs/stm32f429-evaluation_defconfig @@ -12,7 +12,6 @@ CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="U-Boot > " -# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_IMLS=y CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig index 0b36c0fc58..5e40df225b 100644 --- a/configs/stm32f469-discovery_defconfig +++ b/configs/stm32f469-discovery_defconfig @@ -12,7 +12,6 @@ CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PROMPT="U-Boot > " -# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set CONFIG_CMD_IMLS=y CONFIG_CMD_GPT=y # CONFIG_RANDOM_UUID is not set -- 2.19.2

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