January 2019 - U-Boot

[U-Boot] [PATCH 0/2] sunxi sun6i SPI support
by Oskari Lemmela 24 Jan '19

24 Jan '19

Minimal changes to support sun6i SPI with current sun4i SPI driver. During testing I faced random spurious timeouts when reading 16MB flash device. When debugging spurious timeouts those values seems to be -1us. Because timeouts are calculated as unsigned values tiny backward timer jumps causes this kind of issues. Oskari Lemmela (2): arm: sunxi: allwinner spi driver sun6i support arm: timer: sunxi: fix spurious timeout issues arch/arm/cpu/armv8/generic_timer.c | 2 +- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 1 + drivers/spi/Kconfig | 4 +- drivers/spi/sun4i_spi.c | 116 ++++++++++++++++-- 5 files changed, 108 insertions(+), 16 deletions(-) -- 2.17.1

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[U-Boot] [GIT PULL] Xilinx patches for v2019.04
by Michal Simek 24 Jan '19

24 Jan '19

Hi Tom, Here are several patches which I have in my queue. Buildman looks good and travis is also clear. https://travis-ci.org/michalsimek/u-boot/builds/483796826 I have also sent several other patches to be able to finish transition to DM_I2C to reach the state that I can enable it for all boards and I2C will be described based on DT. This is not reviewed yet but hopefully this can go to this release too. In changes below there is nothing crucial. Boards which could be converted are converted to DM_I2C and OF_SEPARATE. Thanks, Michal The following changes since commit aff66f22d6eeb27c6329c0a3c1ebc52914c8affa: Merge tag 'mips-pull-2019-01-23' of git://git.denx.de/u-boot-mips (2019-01-23 17:24:31 -0500) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2019.04 for you to fetch changes up to 4efdbc88b79bd8bd3e285cd238e1942d669a7088: ARM: zynq: Convert Topic Miami to DM_I2C (2019-01-24 10:03:45 +0100) ---------------------------------------------------------------- Xilinx changes for v2019.04 tools: - Fix zynqmpimage generation zynq: - Some configs/Kconfig/DT updates - Enable REMAKE_ELF and OF_SEPARATE - Topic boards update - i2c cleanups and conversion to DM_I2C zynqmp: - Some configs/Kconfig/DT updates - Board config cleanup - Move arch folder to mach-zynqmp versal: - Enable DM_I2C, CMD_DM zynq-gem: - Fix driver cache handling i2c: - Live tree simple update phy: - Fixed phy cleanup travis: - Wire Versal SoC ---------------------------------------------------------------- Anton Gerasimov (1): zynq: Kconfig: extend the bootstrap malloc() pool Luca Ceresoli (1): fpga: zynqmp: show an error message when FPGA programming fails Michael Tretter (1): tools: zynqmpimage: round up partition size Michal Simek (26): arm64: zynqmp: Enable 2 NAND chips for zc1751 dc2 mmc: zynq: Remove unused pwrseq variable arm64: zynqmp: Do not protect zynqmp_pmufw_version() arm64: zynqmp: Protect board_late_init function arm64: zynqmp: Fix tcminit help text alignment arm64: versal: Setup DM_ETH/MMC if NET/MMC is enabled arm64: zynqmp: Setup DM_ETH/MMC if NET/MMC is enabled ARM: zynqmp_r5: Setup DM_ETH/MMC if NET/MMC is enabled arm64: zynqmp: Setup proper SPI dependency arm64: zynqmp: Enable SPI on several boards arm64: zynqmp: Enable ISSI flash for some platforms arm64: zynqmp: Enable FPGA_LOAD_SECURE command arm64: zynqmp: Disable MMC for for zc12xx_revA boards travis: Wire Xilinx Versal Virt platform tools: zynqmpimage: Align image_size/image_stored_size arm64: zynqmp: Align u-boot-spl.bin for boot.bin creation arm64: zynqmp: Convert all reference boards to OF_SEPARATE ARM: zynq: Convert all boards to OF_SEPARATE arm64: zynqmp: Move SoC sources to mach-zynqmp arm64: versal: Enable i2c cadence controller and i2c command arm64: versal: Enable dm command i2c: cdns: Convert to livetree function arm64: zynqmp: Remove unused GEM addresses ARM: zynq: Remove unused GEM addresses ARM: zynq: Disable i2c for Zybo/Zybo Z7 ARM: zynq: Convert Topic Miami to DM_I2C Mike Looijmans (2): topic-miamiplus: Run CPU at 800MHz for speedgrade-2 board: topic-miamiplus: Run IO PLL at 1000 MHz Siva Durga Prasad Paladugu (4): arm64: zynqmp: Fix mmc node names to be in sync with kernel net: phy: Move fixed link code to separate routine arm64: zynqmp: Enable net configs for zc1275 arm: zynq: Enable CONFIG_REMAKE_ELF Stefan Theil (1): zynq-gem: Use appropriate cache flush/invalidate for RX and TX T Karthik Reddy (1): mtd: nand: arasan_nfc: Add support for nand multi chip select .travis.yml | 7 +++++++ MAINTAINERS | 2 +- arch/arm/Kconfig | 12 ++++++++++-- arch/arm/Makefile | 1 + arch/arm/cpu/armv8/Makefile | 1 - arch/arm/dts/zynq-topic-miamiplus.dts | 9 +++++++++ arch/arm/dts/zynqmp.dtsi | 4 ++-- arch/arm/mach-k3/arm64-mmu.c | 2 +- arch/arm/mach-tegra/arm64-mmu.c | 2 +- arch/arm/mach-zynq/Kconfig | 2 +- arch/arm/mach-zynq/include/mach/hardware.h | 2 -- arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/Kconfig | 0 arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/Makefile | 0 arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/clk.c | 0 arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/cpu.c | 4 +--- arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/handoff.c | 0 arch/arm/{include/asm/arch-zynqmp => mach-zynqmp/include/mach}/clk.h | 0 arch/arm/{include/asm/arch-zynqmp => mach-zynqmp/include/mach}/gpio.h | 0 arch/arm/{include/asm/arch-zynqmp => mach-zynqmp/include/mach}/hardware.h | 5 ----- arch/arm/{include/asm/arch-zynqmp => mach-zynqmp/include/mach}/psu_init_gpl.h | 0 arch/arm/{include/asm/arch-zynqmp => mach-zynqmp/include/mach}/sys_proto.h | 0 arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/mp.c | 0 arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/psu_spl_init.c | 0 arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/spl.c | 0 board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c | 34 ++++++++++++++++------------------ board/xilinx/zynqmp/cmds.c | 10 +++++----- board/xilinx/zynqmp/zynqmp.c | 6 ++++++ configs/avnet_ultra96_rev1_defconfig | 6 +----- configs/syzygy_hub_defconfig | 1 - configs/topic_miami_defconfig | 5 ++--- configs/topic_miamilite_defconfig | 5 ++--- configs/topic_miamiplus_defconfig | 5 ++--- configs/xilinx_versal_virt_defconfig | 6 ++++-- configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 - configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 - configs/xilinx_zynqmp_mini_qspi_defconfig | 3 +-- configs/xilinx_zynqmp_zc1232_revA_defconfig | 9 ++++++--- configs/xilinx_zynqmp_zc1254_revA_defconfig | 9 ++++++--- configs/xilinx_zynqmp_zc1275_revA_defconfig | 9 ++++++--- configs/xilinx_zynqmp_zc1275_revB_defconfig | 11 +++++++++-- configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 9 ++++++--- configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 5 +++-- configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig | 5 ++--- configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 9 ++++++--- configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig | 5 ++--- configs/xilinx_zynqmp_zcu100_revC_defconfig | 6 +----- configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 9 ++++----- configs/xilinx_zynqmp_zcu102_revA_defconfig | 10 +++++----- configs/xilinx_zynqmp_zcu102_revB_defconfig | 10 +++++----- configs/xilinx_zynqmp_zcu104_revA_defconfig | 8 +++++--- configs/xilinx_zynqmp_zcu104_revC_defconfig | 8 +++++--- configs/xilinx_zynqmp_zcu106_revA_defconfig | 10 +++++++--- configs/xilinx_zynqmp_zcu111_revA_defconfig | 8 +++++--- configs/zynq_dlc20_rev1_0_defconfig | 1 - configs/zynq_zybo_defconfig | 6 ------ configs/zynq_zybo_z7_defconfig | 4 ---- drivers/fpga/zynqmppl.c | 2 +- drivers/i2c/i2c-cdns.c | 2 +- drivers/mmc/zynq_sdhci.c | 1 - drivers/mtd/nand/raw/Kconfig | 7 +++++++ drivers/mtd/nand/raw/arasan_nfc.c | 27 +++++++++++++-------------- drivers/net/phy/phy.c | 34 +++++++++++++++++++++++++++------- drivers/net/zynq_gem.c | 11 ++++++----- include/configs/zynq-common.h | 2 ++ include/configs/zynq_zybo.h | 18 ------------------ scripts/Makefile.spl | 5 ++++- tools/zynqmpbif.c | 19 ++++++++++++++----- 67 files changed, 231 insertions(+), 184 deletions(-) rename arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/Kconfig (100%) rename arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/Makefile (100%) rename arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/clk.c (100%) rename arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/cpu.c (98%) rename arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/handoff.c (100%) rename arch/arm/{include/asm/arch-zynqmp => mach-zynqmp/include/mach}/clk.h (100%) rename arch/arm/{include/asm/arch-zynqmp => mach-zynqmp/include/mach}/gpio.h (100%) rename arch/arm/{include/asm/arch-zynqmp => mach-zynqmp/include/mach}/hardware.h (96%) rename arch/arm/{include/asm/arch-zynqmp => mach-zynqmp/include/mach}/psu_init_gpl.h (100%) rename arch/arm/{include/asm/arch-zynqmp => mach-zynqmp/include/mach}/sys_proto.h (100%) rename arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/mp.c (100%) rename arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/psu_spl_init.c (100%) rename arch/arm/{cpu/armv8/zynqmp => mach-zynqmp}/spl.c (100%) delete mode 100644 include/configs/zynq_zybo.h -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

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[U-Boot] [PATCH] RFC: dfu: mmc: call fs functions instead of run_command
by Simon Goldschmidt 24 Jan '19

24 Jan '19

This unbreaks dfu mmc_file_op which is currently broken since using the load cmd on a buffer from heap is not allowed. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- drivers/dfu/dfu_mmc.c | 67 ++++++++++++++++++++----------------------- 1 file changed, 31 insertions(+), 36 deletions(-) diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index b45e6dc54c..2585b14328 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -108,17 +108,17 @@ static int mmc_file_buffer(struct dfu_entity *dfu, void *buf, long *len) static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, void *buf, u64 *len) { - const char *fsname, *opname; - char cmd_buf[DFU_CMD_BUF_SIZE]; - char *str_env; + char dev_part_str[DFU_CMD_BUF_SIZE]; int ret; + int fstype; + loff_t size = 0; switch (dfu->layout) { case DFU_FS_FAT: - fsname = "fat"; + fstype = FS_TYPE_FAT; break; case DFU_FS_EXT4: - fsname = "ext4"; + fstype = FS_TYPE_EXT; break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -126,48 +126,43 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, return -1; } + snprintf(dev_part_str, DFU_CMD_BUF_SIZE, "%d:%d", dfu->data.mmc.dev, + dfu->data.mmc.part); + + ret = fs_set_blk_dev("mmc", dev_part_str, fstype); + if (ret) { + puts("dfu: fs_set_blk_dev error!\n"); + return ret; + } + switch (op) { case DFU_OP_READ: - opname = "load"; + ret = fs_read(dfu->name, (size_t)buf, 0, 0, &size); + if (ret) { + puts("dfu: fs_read error!\n"); + return ret; + } + *len = size; break; case DFU_OP_WRITE: - opname = "write"; + ret = fs_write(dfu->name, (size_t)buf, 0, *len, &size); + if (ret) { + puts("dfu: fs_write error!\n"); + return ret; + } break; case DFU_OP_SIZE: - opname = "size"; + ret = fs_size(dfu->name, &size); + if (ret) { + puts("dfu: fs_size error!\n"); + return ret; + } + *len = size; break; default: return -1; } - sprintf(cmd_buf, "%s%s mmc %d:%d", fsname, opname, - dfu->data.mmc.dev, dfu->data.mmc.part); - - if (op != DFU_OP_SIZE) - sprintf(cmd_buf + strlen(cmd_buf), " %p", buf); - - sprintf(cmd_buf + strlen(cmd_buf), " %s", dfu->name); - - if (op == DFU_OP_WRITE) - sprintf(cmd_buf + strlen(cmd_buf), " %llx", *len); - - debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); - - ret = run_command(cmd_buf, 0); - if (ret) { - puts("dfu: Read error!\n"); - return ret; - } - - if (op != DFU_OP_WRITE) { - str_env = env_get("filesize"); - if (str_env == NULL) { - puts("dfu: Wrong file size!\n"); - return -1; - } - *len = simple_strtoul(str_env, NULL, 16); - } - return ret; } -- 2.17.1

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[U-Boot] [PATCH v2] Aquantia: Print information about system interface and firmware version
by Valentin-catalin Neacsu 24 Jan '19

24 Jan '19

Print information about Aquantia firmware loaded on the phy. Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu(a)nxp.com> --- V2: - Fix typo in title. (Clement Peron) drivers/net/phy/aquantia.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 553069f3dc..2609664c69 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -22,6 +22,11 @@ #define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441 +#define AQUANTIA_FIRMWARE_ID 0x20 +#define AQUANTIA_RESERVED_STATUS 0xc885 +#define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00 +#define AQUANTIA_FIRMWARE_MINOR_MASK 0xff +#define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008 #define AQUANTIA_SI_IN_USE_MASK 0x0078 @@ -30,6 +35,7 @@ int aquantia_config(struct phy_device *phydev) { u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); + u32 reg_val1 = 0; if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { /* 1000BASE-T mode */ @@ -56,6 +62,11 @@ int aquantia_config(struct phy_device *phydev) phy_write(phydev, MDIO_MMD_PHYXS, AQUANTIA_VENDOR_PROVISIONING_REG, AQUANTIA_USX_AUTONEG_CONTROL_ENA); + printf("%s: system interface USXGMII\n", + phydev->dev->name); + } else { + printf("%s: system interface XFI\n", + phydev->dev->name); } } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) { @@ -73,6 +84,16 @@ int aquantia_config(struct phy_device *phydev) val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK; phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); } + + val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS); + reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID); + + printf("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name, + phydev->drv->name, + (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8, + reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK, + (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4); + return 0; } -- 2.17.1

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[U-Boot] [PATCH 1/2] AQUANTIA USXGMII autoneg enable
by Valentin-catalin Neacsu 24 Jan '19

24 Jan '19

If System interface protocol is USXGMII then enable USXGMII autoneg Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu(a)nxp.com> --- drivers/net/phy/aquantia.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 6678147545..603abb5a7f 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ * * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP */ #include <config.h> #include <common.h> @@ -20,6 +21,13 @@ #define AQUNTIA_SPEED_LSB_MASK 0x2000 #define AQUNTIA_SPEED_MSB_MASK 0x40 +#define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812 +#define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441 + +#define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008 +#define AQUANTIA_SI_IN_USE_MASK 0x0078 +#define AQUANTIA_SI_USXGMII 0x0018 + int aquantia_config(struct phy_device *phydev) { u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); @@ -41,6 +49,16 @@ int aquantia_config(struct phy_device *phydev) phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, AQUNTIA_SPEED_LSB_MASK | AQUNTIA_SPEED_MSB_MASK); + + val = phy_read(phydev, MDIO_MMD_PHYXS, + AQUANTIA_SYSTEM_INTERFACE_SR); + /* If SI is USXGMII then start USXGMII autoneg*/ + if ((val & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) { + phy_write(phydev, MDIO_MMD_PHYXS, + AQUANTIA_VENDOR_PROVISIONING_REG, + AQUANTIA_USX_AUTONEG_CONTROL_ENA); + } + } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) { /* 2.5GBASE-T mode */ phydev->advertising = SUPPORTED_1000baseT_Full; -- 2.17.1

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[U-Boot] [PATCH 1/2] net: move ether_crc to tsec driver
by Chris Packham 24 Jan '19

24 Jan '19

ether_crc was added to the core net code in commit 53a5c424bf86 ("multicast tftp: RFC2090") so that other drivers could use it. However the only current user of it is tsec.c so move it there. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- drivers/net/tsec.c | 25 +++++++++++++++++++++++++ include/net.h | 1 - net/eth_legacy.c | 24 ------------------------ 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 03a46da2f8a1..9a4fab85e928 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -80,6 +80,31 @@ static void tsec_configure_serdes(struct tsec_private *priv) #ifdef CONFIG_MCAST_TFTP +/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c + * and this is the ethernet-crc method needed for TSEC -- and perhaps + * some other adapter -- hash tables + */ +#define CRCPOLY_LE 0xedb88320 +static u32 ether_crc(size_t len, unsigned char const *p) +{ + int i; + u32 crc; + + crc = ~0; + while (len--) { + crc ^= *p++; + for (i = 0; i < 8; i++) + crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); + } + /* an reverse the bits, cuz of way they arrive -- last-first */ + crc = (crc >> 16) | (crc << 16); + crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00); + crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0); + crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc); + crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa); + return crc; +} + /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */ /* Set the appropriate hash bit for the given addr */ diff --git a/include/net.h b/include/net.h index 51c099dae2e5..359bfb5ef69f 100644 --- a/include/net.h +++ b/include/net.h @@ -289,7 +289,6 @@ const char *eth_get_name(void); /* get name of current device */ #ifdef CONFIG_MCAST_TFTP int eth_mcast_join(struct in_addr mcast_addr, int join); -u32 ether_crc(size_t len, unsigned char const *p); #endif diff --git a/net/eth_legacy.c b/net/eth_legacy.c index 2a9caa3509b0..d2e16b8fa3da 100644 --- a/net/eth_legacy.c +++ b/net/eth_legacy.c @@ -310,30 +310,6 @@ int eth_mcast_join(struct in_addr mcast_ip, int join) return eth_current->mcast(eth_current, mcast_mac, join); } -/* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c - * and this is the ethernet-crc method needed for TSEC -- and perhaps - * some other adapter -- hash tables - */ -#define CRCPOLY_LE 0xedb88320 -u32 ether_crc(size_t len, unsigned char const *p) -{ - int i; - u32 crc; - crc = ~0; - while (len--) { - crc ^= *p++; - for (i = 0; i < 8; i++) - crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0); - } - /* an reverse the bits, cuz of way they arrive -- last-first */ - crc = (crc >> 16) | (crc << 16); - crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00); - crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0); - crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc); - crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa); - return crc; -} - #endif -- 2.19.2

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[U-Boot] [PATCH u-boot] net: phy: realtek: Add functions to read PHY's extended registers
by Carlo Caione 24 Jan '19

24 Jan '19

According to the datasheet to access the extended registers we have to: 1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ) 2. Read/Write the target Register Data 3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE Standard Registers) Hook the missing functions so that we can use the `mdio rx/wx` command to easily access the extended registers. Signed-off-by: Carlo Caione <ccaione(a)baylibre.com> --- drivers/net/phy/realtek.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index b3e6578df9..3bea1fa9d0 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -57,6 +57,31 @@ #define MIIM_RTL8211F_TX_DELAY 0x100 #define MIIM_RTL8211F_LCR 0x10 +static int rtl8211f_phy_extread(struct phy_device *phydev, int addr, + int devaddr, int regnum) +{ + int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT); + int val; + + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr); + val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage); + + return val; +} + +static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr, + int devaddr, int regnum, u16 val) +{ + int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT); + + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr); + phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage); + + return 0; +} + static int rtl8211b_probe(struct phy_device *phydev) { #ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER @@ -336,6 +361,8 @@ static struct phy_driver RTL8211F_driver = { .config = &rtl8211f_config, .startup = &rtl8211f_startup, .shutdown = &genphy_shutdown, + .readext = &rtl8211f_phy_extread, + .writeext = &rtl8211f_phy_extwrite, }; int phy_realtek_init(void) -- 2.19.1

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[U-Boot] [PATCH v2] net: macb: fix mapping of registers
by Ramon Fried 24 Jan '19

24 Jan '19

Some architectures (MIPS) needs mapping to access IOMEM. Fix that. Fixes: f1dcc19b213d ("net: macb: Convert to driver model") Signed-off-by: Ramon Fried <ramon.fried(a)gmail.com> --- v2: add casting to phys_addr_t to prevent warning from compiler. drivers/net/macb.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 94c89c762b..c9ee22279a 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -1151,7 +1151,9 @@ static int macb_eth_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); - pdata->iobase = devfdt_get_addr(dev); + pdata->iobase = (phys_addr_t)dev_remap_addr(dev); + if (!pdata->iobase) + return -EINVAL; return macb_late_eth_ofdata_to_platdata(dev); } -- 2.19.2

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[U-Boot] [PATCH 1/1] net: mvneta: Add GPIO configuration support
by Aditya Prayoga 24 Jan '19

24 Jan '19

This patch add GPIO configuration support in mvneta driver. Driver will handle PHY reset. GPIO pins should be set in device tree. Ported from mvpp2x [https://patchwork.ozlabs.org/patch/799654/] Initial discussion to port the changes into mvneta [https://patchwork.ozlabs.org/patch/1005765/] Signed-off-by: Aditya Prayoga <aditya(a)kobol.io> --- drivers/net/mvneta.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 8cb04b5..333be8f 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -27,6 +27,7 @@ #include <asm/arch/soc.h> #include <linux/compat.h> #include <linux/mbus.h> +#include <asm-generic/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -274,6 +275,9 @@ struct mvneta_port { int init; int phyaddr; struct phy_device *phydev; +#ifdef CONFIG_DM_GPIO + struct gpio_desc phy_reset_gpio; +#endif struct mii_dev *bus; }; @@ -1749,6 +1753,17 @@ static int mvneta_probe(struct udevice *dev) if (ret) return ret; +#ifdef CONFIG_DM_GPIO + gpio_request_by_name(dev, "phy-reset-gpios", 0, + &pp->phy_reset_gpio, GPIOD_IS_OUT); + + if (dm_gpio_is_valid(&pp->phy_reset_gpio)) { + dm_gpio_set_value(&pp->phy_reset_gpio, 1); + mdelay(10); + dm_gpio_set_value(&pp->phy_reset_gpio, 0); + } +#endif + return board_network_enable(bus); } -- 2.7.4

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[U-Boot] [PATCH] net: mvgbe: fallback phy-mode to GMII
by Chris Packham 24 Jan '19

24 Jan '19

Some existing device trees don't specify a phy-mode so fallback to GMII when a phy-mode is not provided. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- This is similar to what the Linux mv643xx_eth.c network driver does to handle the same case. drivers/net/mvgbe.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 74fed7abd837..037e59ec6e3c 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -1005,10 +1005,8 @@ static int mvgbe_ofdata_to_platdata(struct udevice *dev) phy_mode = fdt_getprop(gd->fdt_blob, pnode, "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); - if (pdata->phy_interface == -1) { - debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); - return -EINVAL; - } + else + pdata->phy_interface = PHY_INTERFACE_MODE_GMII; dmvgbe->phy_interface = pdata->phy_interface; -- 2.19.2

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