June 2018 - U-Boot

[U-Boot] [PATCH] spi: mxc: Fix compilation problem of DM_SPI class driver
by Michael Trimarchi 17 Jun '18

17 Jun '18

drivers/spi/mxc_spi.c:507: undefined reference to `dev_get_addr' linux-ld.bfd: BFD (GNU Binutils) 2.29.1 assertion fail elf32-arm.c:9509 Change-Id: I1df196ed847cf06e19d3039bc4461eb8bd928a83 Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- drivers/spi/mxc_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index b77129c..fcb214a 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -504,7 +504,7 @@ static int mxc_spi_probe(struct udevice *bus) return -EINVAL; } - plat->base = dev_get_addr(bus); + plat->base = devfdt_get_addr(bus); if (plat->base == FDT_ADDR_T_NONE) return -ENODEV; -- 2.7.4

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[U-Boot] [PULL] u-boot-usb/master
by Marek Vasut 17 Jun '18

17 Jun '18

The following changes since commit 7868909ed53ed41a945f7ed95ebb88aa252142ce: Merge git://git.denx.de/u-boot-fsl-qoriq (2018-06-12 13:25:24 -0400) are available in the Git repository at: git://git.denx.de/u-boot-usb.git master for you to fetch changes up to b9f34757db5dcde9ccfa6ce35705b025bc4843fc: usb: sunxi: access ahb_reset0_cfg in CCM using its offset (2018-06-14 12:57:19 +0200) ---------------------------------------------------------------- Vasily Khoruzhick (5): sunxi: clock: Fix EHCI and OHCI clocks on A64 usb: sunxi: ehci: get rid of ifdefs usb: sunxi: ohci: get rid of ifdefs usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use usb: sunxi: access ahb_reset0_cfg in CCM using its offset arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 6 ++++-- drivers/usb/host/ehci-sunxi.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------- drivers/usb/host/ohci-sunxi.c | 109 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------------------- 3 files changed, 170 insertions(+), 43 deletions(-)

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[U-Boot] [PATCH] eth: dm: fec: Add gpio phy reset binding
by Michael Trimarchi 17 Jun '18

17 Jun '18

Add the missing gpio phy reset binding to the gpio and it's reset time configuration Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- drivers/net/fec_mxc.c | 42 ++++++++++++++++++++++++++++++++++++------ drivers/net/fec_mxc.h | 5 ++++- 2 files changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 694a0b2..9eb2693 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -15,7 +15,6 @@ #include <miiphy.h> #include <net.h> #include <netdev.h> -#include "fec_mxc.h" #include <asm/io.h> #include <linux/errno.h> @@ -24,6 +23,9 @@ #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/mach-imx/sys_proto.h> +#include <asm-generic/gpio.h> + +#include "fec_mxc.h" DECLARE_GLOBAL_DATA_PTR; @@ -1245,6 +1247,19 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) return 0; } +#ifdef CONFIG_DM_GPIO +/* FEC GPIO reset */ +static void fec_gpio_reset(struct fec_priv *priv) +{ + debug("fec_gpio_reset: fec_gpio_reset(dev)\n"); + if (dm_gpio_is_valid(&priv->phy_reset_gpio)) { + dm_gpio_set_value(&priv->phy_reset_gpio, 1); + udelay(priv->reset_delay); + dm_gpio_set_value(&priv->phy_reset_gpio, 0); + } +} +#endif + static int fecmxc_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); @@ -1257,6 +1272,9 @@ static int fecmxc_probe(struct udevice *dev) if (ret) return ret; +#ifdef CONFIG_DM_GPIO + fec_gpio_reset(priv); +#endif /* Reset chip. */ writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, &priv->eth->ecntrl); @@ -1314,6 +1332,7 @@ static int fecmxc_remove(struct udevice *dev) static int fecmxc_ofdata_to_platdata(struct udevice *dev) { + int ret = 0; struct eth_pdata *pdata = dev_get_platdata(dev); struct fec_priv *priv = dev_get_priv(dev); const char *phy_mode; @@ -1331,12 +1350,23 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev) return -EINVAL; } - /* TODO - * Need to get the reset-gpio and related properties from DT - * and implemet the enet reset code on .probe call - */ +#ifdef CONFIG_DM_GPIO + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, + &priv->phy_reset_gpio, GPIOD_IS_OUT); + if (ret == 0) { + ret = dev_read_u32_array(dev, "phy-reset-duration", + &priv->reset_delay, 1000); + } else if (ret == -ENOENT) { + ret = 0; + } - return 0; + if (priv->reset_delay > 1000) { + printf("FEX MXC: gpio reset timeout should be less the 1000\n"); + priv->reset_delay = 1000; + } +#endif + + return ret; } static const struct udevice_id fecmxc_ids[] = { diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 3b935af..fd89443 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -250,7 +250,10 @@ struct fec_priv { int phy_id; int (*mii_postcall)(int); #endif - +#ifdef CONFIG_DM_GPIO + struct gpio_desc phy_reset_gpio; + uint32_t reset_delay; +#endif #ifdef CONFIG_DM_ETH u32 interface; #endif -- 2.7.4

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[U-Boot] [PATCH] ARM: dts: rmobile: Move the PHY reset GPIO back
by Marek Vasut 17 Jun '18

17 Jun '18

The current state of RAVB driver expects the PHY reset GPIO in the RAVB mode, move it back from the PHY node to avoid breakage. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/arm/dts/salvator-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/salvator-common.dtsi b/arch/arm/dts/salvator-common.dtsi index 514c57b2c8..6b176ea36a 100644 --- a/arch/arm/dts/salvator-common.dtsi +++ b/arch/arm/dts/salvator-common.dtsi @@ -257,6 +257,7 @@ pinctrl-names = "default"; phy-handle = <&phy0>; phy-mode = "rgmii-txid"; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; status = "okay"; phy0: ethernet-phy@0 { @@ -264,7 +265,6 @@ reg = <0>; interrupt-parent = <&gpio2>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; }; }; -- 2.17.1

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[U-Boot] [PATCH] ARM: rmobile: Adjust text base on V3M Eagle
by Marek Vasut 17 Jun '18

17 Jun '18

The latest ATF puts the U-Boot at 0x50000000, just like on all the other boards. Adjust the text base to reflect that change. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- configs/r8a77970_eagle_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 889fc6e83b..abca2bf338 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0x58280000 +CONFIG_SYS_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y CONFIG_R8A77970=y -- 2.17.1

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[U-Boot] Q about ARM "boot_mode.h"
by Wis Macomson 16 Jun '18

16 Jun '18

On Github: linux-u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h contains these lines 21-26 #ifndef __ASSEMBLY__ int setup_boot_mode(void); #endif int setup_boot_mode(void); Won't this give multiple definitions of "setup_boot_mode" if __ASSEMBLY__ is not defined? -wis

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[U-Boot] sun50i: h5: Add initial Orange Pi Zero Plus support
by Hauke Mehrtens 16 Jun '18

16 Jun '18

Orange Pi Zero Plus is an open-source single-board computer using the Allwinner H5 SOC. H5 Orangepi Zero Plus has - Quad-core Cortex-A53 - 512MB DDR3 - micrSD slot - 16MBit SPI Nor flash - Debug TTL UART - 1GBit/s Ethernet (RTL8211E) - Wifi (RTL8189FTV) - USB 2.0 Host - USB 2.0 OTG + power supply The device tree file is copied from the Linux kernel 4.17. Signed-off-by: Hauke Mehrtens <hauke(a)hauke-m.de> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts | 145 ++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 + configs/orangepi_zero_plus_defconfig | 16 +++ 4 files changed, 167 insertions(+) create mode 100644 arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts create mode 100644 configs/orangepi_zero_plus_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e81a580692..3fff4c94e7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -379,6 +379,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-libretech-all-h3-cc.dtb \ sun50i-h5-nanopi-neo2.dtb \ sun50i-h5-nanopi-neo-plus2.dtb \ + sun50i-h5-orangepi-zero-plus.dtb \ sun50i-h5-orangepi-pc2.dtb \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb diff --git a/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts new file mode 100644 index 0000000000..e79cf3baf4 --- /dev/null +++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * Copyright (C) 2018 Hauke Mehrtens <hauke(a)hauke-m.de> + * + * SPDX-License-Identifier: (GPL-2.0+ OR X11) + */ + +/dts-v1/; +#include "sun50i-h5.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi Zero Plus"; + compatible = "xunlong,orangepi-zero-plus", "allwinner,sun50i-h5"; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + aliases { + ethernet0 = &emac; + ethernet1 = &rtl8189ftv; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ + default-state = "on"; + }; + + status { + label = "orangepi:red:status"; + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */ + }; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <&reg_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&external_mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <&reg_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189ftv: sdio_wifi@1 { + reg = <1>; + }; +}; + +/* +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l1606e", "winbond,w25q128"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; +*/ + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + /* USB Type-A ports' VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 6ebf612db3..db51f48ab6 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -340,6 +340,11 @@ M: Icenowy Zheng <icenowy(a)aosc.xyz> S: Maintained F: configs/orangepi_zero_defconfig +ORANGEPI ZERO PLUS BOARD +M: Hauke Mehrtens <hauke(a)hauke-m.de> +S: Maintained +F: configs/orangepi_zero_plus_defconfig + ORANGEPI ZERO PLUS 2 BOARD M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig new file mode 100644 index 0000000000..fc656ce733 --- /dev/null +++ b/configs/orangepi_zero_plus_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_DRAM_CLK=624 +CONFIG_DRAM_ZQ=3881977 +CONFIG_MMC0_CD_PIN="PH13" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-zero-plus" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -- 2.11.0

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[U-Boot] sun8i: h2: Add initial Orange Pi R1 support
by Hauke Mehrtens 16 Jun '18

16 Jun '18

Orange Pi R1 is an open-source single-board computer using the Allwinner H2+ SOC. H2+ Orange Pi R1 has - Quad-core Cortex-A7 - 256MB DDR3 - micrSD slot - 128MBit SPI Nor flash - Debug TTL UART - 100MBit/s Ethernet (H2+) - 100MBit/s Ethernet (RTL8152B) - Wifi (RTL8189ETV) - USB 2.0 OTG + power supply This board is very similar to the Orange Pi Zero. The device tree file is copied from the Linux kernel 4.17. Signed-off-by: Hauke Mehrtens <hauke(a)hauke-m.de> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts | 101 +++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 ++ configs/orangepi_r1_defconfig | 16 +++++ 4 files changed, 123 insertions(+) create mode 100644 arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts create mode 100644 configs/orangepi_r1_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 790571b773..e81a580692 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -355,6 +355,7 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ sun8i-a83t-tbs-a711.dts dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h2-plus-libretech-all-h3-cc.dtb \ + sun8i-h2-plus-orangepi-r1.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-libretech-all-h3-cc.dtb \ diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts new file mode 100644 index 0000000000..c652ac3b71 --- /dev/null +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-r1.dts @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2017 Icenowy Zheng <icenowy(a)aosc.xyz> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* Orange Pi R1 is based on Orange Pi Zero design */ +#include "sun8i-h2-plus-orangepi-zero.dts" + +/ { + model = "Xunlong Orange Pi R1"; + compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus"; + + /delete-node/ reg_vcc_wifi; + + /* + * Ths pin of this regulator is the same with the Wi-Fi extra + * regulator on the original Zero. However it's used for USB + * Ethernet rather than the Wi-Fi now. + */ + reg_vcc_usb_eth: reg-vcc-usb-ethernet { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-usb-ethernet"; + enable-active-high; + gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>; + }; + + aliases { + ethernet1 = &rtl8189etv; + }; +}; + +/* +&spi0 { + status = "okay"; + + flash@0 { + compatible = "mxicy,mx25l12805d", "jedec,spi-nor"; + }; +}; +*/ + +&ohci1 { + /* + * RTL8152B USB-Ethernet adapter is connected to USB1, + * and it's a USB 2.0 device. So the OHCI1 controller + * can be left disabled. + */ + status = "disabled"; +}; + +&mmc1 { + vmmc-supply = <&reg_vcc3v3>; + vqmmc-supply = <&reg_vcc3v3>; + + rtl8189etv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&usbphy { + usb1_vbus-supply = <&reg_vcc_usb_eth>; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index e90c87b560..6ebf612db3 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -355,6 +355,11 @@ M: Jagan Teki <jagan(a)amarulasolutions.com> S: Maintained F: configs/orangepi_prime_defconfig +ORANGEPI R1 BOARD +M: Hauke Mehrtens <hauke(a)hauke-m.de> +S: Maintained +F: configs/orangepi_r1_defconfig + PINE64 BOARDS M: Andre Przywara <andre.przywara(a)arm.com> S: Maintained diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig new file mode 100644 index 0000000000..8e6ee7b2db --- /dev/null +++ b/configs/orangepi_r1_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_H3=y +CONFIG_DRAM_CLK=624 +CONFIG_DRAM_ZQ=3881979 +CONFIG_DRAM_ODT_EN=y +# CONFIG_VIDEO_DE2 is not set +CONFIG_SPL_SPI_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-orangepi-r1" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +# CONFIG_CMD_FLASH is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y -- 2.11.0

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[U-Boot] Please pull ARC changes
by Alexey Brodkin 16 Jun '18

16 Jun '18

Hi Tom, The following changes since commit 606fddd76c7a045c09d544357806b0b4de4845c7: Merge branch 'master' of git://git.denx.de/u-boot-net (2018-06-14 07:20:41 -0400) are available in the Git repository at: git://git.denx.de/u-boot-arc.git tags/arc-updates-for-2018.07-rc2 for you to fetch changes up to 3b4410dde3b82c8a743fa88280b9b0cdd21b1bf3: ARC: HSDK: Add readme (2018-06-15 15:54:43 +0300) ---------------------------------------------------------------- Here we just add a tool for HSDK flashable images preparation together with extensive documentation for HSDK board. This will help real-life users to update U-Boot on the board. ---------------------------------------------------------------- Alexey Brodkin (1): ARC: HSDK: Add readme Eugeniy Paltsev (1): ARC: HSDK: Add tool and make target to generate bsp board/synopsys/hsdk/README | 121 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/synopsys/hsdk/config.mk | 11 +++++++++ board/synopsys/hsdk/headerize-hsdk.py | 149 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/hsdk.h | 6 +++++ 4 files changed, 287 insertions(+) create mode 100644 board/synopsys/hsdk/README create mode 100644 board/synopsys/hsdk/config.mk create mode 100644 board/synopsys/hsdk/headerize-hsdk.py -Alexey

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[U-Boot] [GIT PULL] Xilinx changes for v2018.07-rc2
by Michal Simek 16 Jun '18

16 Jun '18

Hi Tom, please pull these changes to your tree. Buildman and travis looks good https://travis-ci.org/michalsimek/u-boot/builds/392586380 Thanks, Michal The following changes since commit 606fddd76c7a045c09d544357806b0b4de4845c7: Merge branch 'master' of git://git.denx.de/u-boot-net (2018-06-14 07:20:41 -0400) are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git tags/xilinx-for-v2018.07-rc2 for you to fetch changes up to b729ed0d95415bd694a6b67c0761f03ef5a1e2bc: serial: zynq: Make zynq_serial_setbrg static (2018-06-15 08:54:05 +0200) ---------------------------------------------------------------- Xilinx fixes for v2018.07-rc2 Zynq: - Fix missing watchdog header - DT fixes ZynqMP: - emmc configuration split - Enable SPD - Fix PMUFW_INIT_FILE logic - Coverity fixes in SoC code timer - Add timer_get_boot_us mmc: - Fix MMC HS200 tuning command serial: - Fix scrabled chars with OF_LIVE ---------------------------------------------------------------- Luca Ceresoli (1): arm64: zynqmp: accept an absolute path for PMUFW_INIT_FILE Michal Simek (13): arm: zynq: Add missing watchdog header arm: zynq: Drop #address-cells and #size-cells from gpio-keys timer: cadence: Implement timer_get_boot_us arm64: zynqmp: Enable SPD ddr support for zcu102 targets gpio: zynq: Do not check unsigned type that is >= 0 mmc: zynq: Fix tuning_loop_counter type in arasan_sdhci_execute_tuning() arm64: zynqmp: Check return value from calloc arm64: zynqmp: Check return value in zynqmp_mmio_rawwrite() gpio: zynq_gpio: bank description should use unsigned type serial: zynq: Use BIT macros instead of shifts and full hex numbers serial: zynq: Write chars till output fifo is full serial: zynq: Initialize uart only before relocation serial: zynq: Make zynq_serial_setbrg static Siva Durga Prasad Paladugu (2): arm64: zynqmp: Split emmc configuration into emmc0 and emmc1 mmc: sdhci: Fix MMC HS200 tuning command failures arch/arm/cpu/armv8/zynqmp/cpu.c | 6 +++++- arch/arm/dts/Makefile | 3 ++- arch/arm/dts/zynq-zc702.dts | 2 -- arch/arm/dts/zynq-zturn.dts | 2 -- arch/arm/dts/{zynqmp-mini-emmc.dts => zynqmp-mini-emmc0.dts} | 20 ++++++-------------- arch/arm/dts/zynqmp-mini-emmc1.dts | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/zynqmp-zcu100-revC.dts | 2 -- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 -- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 -- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 -- board/xilinx/zynq/board.c | 1 + board/xilinx/zynqmp/zynqmp.c | 2 ++ configs/{xilinx_zynqmp_mini_emmc_defconfig => xilinx_zynqmp_mini_emmc0_defconfig} | 3 ++- configs/xilinx_zynqmp_mini_emmc1_defconfig | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ configs/xilinx_zynqmp_r5_defconfig | 2 ++ configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 + configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 + drivers/gpio/zynq_gpio.c | 10 +++++----- drivers/mmc/sdhci.c | 8 ++++---- drivers/mmc/zynq_sdhci.c | 2 +- drivers/serial/serial_zynq.c | 24 +++++++++++++++--------- drivers/timer/cadence-ttc.c | 22 ++++++++++++++++++++++ include/configs/xilinx_zynqmp_zcu102.h | 3 +++ scripts/Makefile.spl | 8 +++++++- 25 files changed, 196 insertions(+), 49 deletions(-) rename arch/arm/dts/{zynqmp-mini-emmc.dts => zynqmp-mini-emmc0.dts} (77%) create mode 100644 arch/arm/dts/zynqmp-mini-emmc1.dts rename configs/{xilinx_zynqmp_mini_emmc_defconfig => xilinx_zynqmp_mini_emmc0_defconfig} (94%) create mode 100644 configs/xilinx_zynqmp_mini_emmc1_defconfig -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs

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