June 2018 - U-Boot

[U-Boot] [PATCH 1/3] wandboard: Remove hardcoded baudrate from "console" variable
by Otavio Salvador 18 Jun '18

18 Jun '18

We should use the baudrate variable available inside U-Boot environment to allow it to be changed dynamically. Signed-off-by: Otavio Salvador <otavio(a)ossystems.com.br> --- include/configs/wandboard.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 1edd7a8827..cb32cd11f9 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -78,7 +78,7 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200\0" \ + "console=ttymxc0\0" \ "splashpos=m,m\0" \ "fdtfile=undefined\0" \ "fdt_high=0xffffffff\0" \ -- 2.17.1

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[U-Boot] [PULL] u-boot-sh/master
by Marek Vasut 18 Jun '18

18 Jun '18

The following changes since commit 813d1fb56dc0af9567feb86cd71c49f14662044b: Merge branch 'master' of git://git.denx.de/u-boot-ubi (2018-06-08 10:08:20 -0400) are available in the Git repository at: git://git.denx.de/u-boot-sh.git master for you to fetch changes up to 0a52b00627c4fb6b100745c97910b75c99f3f4a9: ARM: rmobile: Fix environment placement on Draak (2018-06-10 16:34:43 +0200) ---------------------------------------------------------------- Marek Vasut (8): pinctrl: renesas: Sync Gen2 PFC tables with Linux v4.17 pinctrl: renesas: Sync Gen3 PFC tables with Linux v4.17 ARM: rmobile: Sync Gen2 DTS with Linux v4.17 ARM: rmobile: Sync Gen3 DTS with Linux v4.17 ARM: rmobile: Zap CONFIG_SYS_CLK_FREQ where applicable ARM: rmobile: Point load address to more sane area on Gen2 ARM: rmobile: Point load address to more sane area on Gen3 ARM: rmobile: Fix environment placement on Draak arch/arm/dts/r8a7790-lager.dts | 310 +++++++++----- arch/arm/dts/r8a7790.dtsi | 2877 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------------------------- arch/arm/dts/r8a7791-koelsch.dts | 259 ++++++----- arch/arm/dts/r8a7791-porter.dts | 151 ++++--- arch/arm/dts/r8a7791.dtsi | 3008 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------------------- arch/arm/dts/r8a7792.dtsi | 587 +++++++++++++------------ arch/arm/dts/r8a7793-gose.dts | 262 +++++++----- arch/arm/dts/r8a7793.dtsi | 2409 +++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------- arch/arm/dts/r8a7794-alt.dts | 56 ++- arch/arm/dts/r8a7794-silk.dts | 189 ++++++--- arch/arm/dts/r8a7794.dtsi | 2416 +++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------- arch/arm/dts/r8a7795.dtsi | 602 +++++++++++++++++++++----- arch/arm/dts/r8a7796.dtsi | 556 ++++++++++++++++++------ arch/arm/dts/r8a77965.dtsi | 127 +++++- arch/arm/dts/r8a77970-eagle.dts | 66 +-- arch/arm/dts/r8a77970.dtsi | 328 ++++++++++++-- arch/arm/dts/r8a77995-draak.dts | 124 ++++++ arch/arm/dts/r8a77995.dtsi | 423 +++++++++++++++++- arch/arm/dts/salvator-common.dtsi | 85 +++- arch/arm/dts/ulcb.dtsi | 22 +- drivers/pinctrl/renesas/pfc-r8a7790.c | 8 +- drivers/pinctrl/renesas/pfc-r8a7791.c | 84 +++- drivers/pinctrl/renesas/pfc-r8a7794.c | 473 +++++++++++++++++++++ drivers/pinctrl/renesas/pfc-r8a7795.c | 1968 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------- drivers/pinctrl/renesas/pfc-r8a7796.c | 1048 +++++++++++++++++++++++++++++++-------------- drivers/pinctrl/renesas/pfc-r8a77970.c | 873 ++++++++++++++++--------------------- drivers/pinctrl/renesas/pfc-r8a77990.c | 3446 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/pinctrl/renesas/pfc-r8a77995.c | 695 +++++++++++++++++++++++++++++- drivers/pinctrl/renesas/sh_pfc.h | 5 +- include/configs/draak.h | 6 +- include/configs/ebisu.h | 4 - include/configs/rcar-gen2-common.h | 3 +- include/configs/rcar-gen3-common.h | 3 +- include/configs/salvator-x.h | 4 - include/configs/ulcb.h | 4 - 35 files changed, 16030 insertions(+), 7451 deletions(-)

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[U-Boot] [PATCH] imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platforms
by Fabio Estevam 18 Jun '18

18 Jun '18

From: Ye Li <ye.li(a)nxp.com> According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit is set to 1 before the caches and MMU are enabled, or any cache and TLB maintenance operations are performed". ROM sets this bit in normal boot flow, but when in serial download mode, it is not set. Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms, including mx7d, mx6ul/ull and mx7ulp. Signed-off-by: Ye Li <ye.li(a)nxp.com> [fabio: adapted to U-Boot mainline codebase and make checkpatch happy] Signed-off-by: Fabio Estevam <fabio.estevam(a)nxp.com> --- arch/arm/mach-imx/cache.c | 42 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/mx7/soc.c | 7 ------- 2 files changed, 42 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index c5279a7..86205cf 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -10,6 +10,34 @@ #include <asm/io.h> #include <asm/mach-imx/sys_proto.h> +static void enable_ca7_smp(void) +{ + u32 val; + + /* Read MIDR */ + asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val)); + val = (val >> 4); + val &= 0xf; + + /* Only set the SMP for Cortex A7 */ + if (val == 0x7) { + /* Read auxiliary control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val)); + + if (val & (1 << 6)) + return; + + /* Enable SMP */ + val |= (1 << 6); + + /* Write auxiliary control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val)); + + DSB; + ISB; + } +} + #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { @@ -21,6 +49,9 @@ void enable_caches(void) /* Avoid random hang when download by usb */ invalidate_dcache_all(); + /* Set ACTLR.SMP bit for Cortex-A7 */ + enable_ca7_smp(); + /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); @@ -32,6 +63,17 @@ void enable_caches(void) IRAM_SIZE, option); } +#else +void enable_caches(void) +{ + /* + * Set ACTLR.SMP bit for Cortex-A7, even if the caches are + * disabled by u-boot + */ + enable_ca7_smp(); + + puts("WARNING: Caches not enabled\n"); +} #endif #ifndef CONFIG_SYS_L2CACHE_OFF diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 3ceeeff..83bcd2d 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -281,13 +281,6 @@ const struct boot_mode soc_boot_modes[] = { void s_init(void) { -#if !defined CONFIG_SPL_BUILD - /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ - asm volatile( - "mrc p15, 0, r0, c1, c0, 1\n" - "orr r0, r0, #1 << 6\n" - "mcr p15, 0, r0, c1, c0, 1\n"); -#endif /* clock configuration. */ clock_init(); -- 2.7.4

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[U-Boot] Fw: make config Error
by Duncan Hare 18 Jun '18

18 Jun '18

From: Joe Hershberger <joe.hershberger(a)ni.com> To: Duncan Hare <DH(a)synoia.com> Cc: Simon Glass <sjg(a)chromium.org>; Joe Hershberger <joe.hershberger(a)ni.com>; u-boot <u-boot(a)lists.denx.de> Sent: Friday, June 15, 2018 12:54 PM Subject: Re: [U-Boot] make config Error On Fri, Jun 15, 2018 at 10:56 AM, <DH(a)synoia.com> wrote: > installed bison++ I just "sudo apt-get install flex bison" and it worked great. > > Cloned most recent u-boot 2018.06.14 > ___________________________________________________________________________________ Not so much for me: Debian, with flex ncurses5-dev and bison++ root@debian:/home/duncan/archive/u-boot# make clean root@debian:/home/duncan/archive/u-boot# make menuconfig HOSTCC scripts/basic/fixdep HOSTCC scripts/kconfig/mconf.o YACC scripts/kconfig/zconf.tab.c scripts/kconfig/zconf.y:44 parser name defined to default :"parse" <-------------------? "scripts/kconfig/zconf.y", line 97: junk after `%%' in definition section Segmentation fault scripts/Makefile.lib:228: recipe for target 'scripts/kconfig/zconf.tab.c' failed make[1]: *** [scripts/kconfig/zconf.tab.c] Error 139 Makefile:491: recipe for target 'menuconfig' failed make: *** [menuconfig] Error 2 root@debian:/home/duncan/archive/u-boot# ^C root@debian:/home/duncan/archive/u-boot# Raspbian no flex :-( pi@raspberrypi:~/server/archive/u-boot $ sudo apt install flex Reading package lists... Done Building dependency tree Reading state information... Done Package flex is not available, but is referred to by another package. This may mean that the package is missing, has been obsoleted, or is only available from another source E: Package 'flex' has no installation candidate In this repository. It might exist elsewhere. I generally use raspbian to compile u-boot for the raspberry pi, and Debian as a file server. The 06.15.2018 version works. Instead of installing bits and pieces of the toolchain, how about reverting to the previous version? Is there link to updated documentation for pre-regs? Duncan Hare 714 931 7952

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[U-Boot] DM-SERIAL-SPL on MX6
by Hannes Schmelzer 18 Jun '18

18 Jun '18

hi, i'm actually trying to convert my i.mx6 boards to DM, many things are already doing well. But I've trouble getting the console (UART) runnin SPL. The "preloader_console_init" is called very early in board_init_f, i guess that DM isn't ready at this point. has anyone experience in this? cheers, Hannes

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[U-Boot] [PATCH] configs: Lower Lamobo R1 DRAM clock rate to 384 MHz
by Paul Kocialkowski 18 Jun '18

18 Jun '18

When running at 432 MHz, the Lamobo R1 DRAM tends to get corrupted under stressing workloads. Reducing the clock rate to 384 MHz results in significantly-improved stability. One reliable way to trigger a corruption at 432 MHz is to run I/O-intensive operations on an attached SATA disk. The same operations when operating the DRAM at 384 MHz typically go fine. For some unexplained reason, running at 408 MHz worsens the situation. Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- configs/Lamobo_R1_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index 92e682128c..cf60fdfaf4 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_SYS_TEXT_BASE=0x4a000000 CONFIG_MACH_SUN7I=y -CONFIG_DRAM_CLK=432 +CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH23" CONFIG_MMC0_CD_PIN="PH10" CONFIG_SATAPWR="PB3" -- 2.17.1

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[U-Boot] Please pull ARC changes
by Alexey Brodkin 18 Jun '18

18 Jun '18

Hi Tom, The following changes since commit 606fddd76c7a045c09d544357806b0b4de4845c7: Merge branch 'master' of git://git.denx.de/u-boot-net (2018-06-14 07:20:41 -0400) are available in the Git repository at: git://git.denx.de/u-boot-arc.git tags/arc-updates-for-2018.07-rc2 for you to fetch changes up to 3b4410dde3b82c8a743fa88280b9b0cdd21b1bf3: ARC: HSDK: Add readme (2018-06-15 15:54:43 +0300) ---------------------------------------------------------------- Here we just add a tool for HSDK flashable images preparation together with extensive documentation for HSDK board. This will help real-life users to update U-Boot on the board. ---------------------------------------------------------------- Alexey Brodkin (1): ARC: HSDK: Add readme Eugeniy Paltsev (1): ARC: HSDK: Add tool and make target to generate bsp board/synopsys/hsdk/README | 121 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ board/synopsys/hsdk/config.mk | 11 +++++++++ board/synopsys/hsdk/headerize-hsdk.py | 149 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/hsdk.h | 6 +++++ 4 files changed, 287 insertions(+) create mode 100644 board/synopsys/hsdk/README create mode 100644 board/synopsys/hsdk/config.mk create mode 100644 board/synopsys/hsdk/headerize-hsdk.py -Alexey

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[U-Boot] [PATCH v3 2/4] arm: zynq: Dont define SDRAM_BASE and SDRAM_SIZE in .h
by Siva Durga Prasad Paladugu 18 Jun '18

18 Jun '18

Remove the SDRAM_BASE nad SDRAM_SIZE as it can now get these details from DT. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu(a)xilinx.com> --- Changes from v2: - None Changes from v1: - Removed commit reference from description as per comment --- include/configs/zynq_cse.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index 2f5843f..adc02f0 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -41,7 +41,4 @@ #undef CONFIG_SYS_MALLOC_LEN #define CONFIG_SYS_MALLOC_LEN 0x1000 -#define CONFIG_SYS_SDRAM_BASE 0xfffc0000 -#define CONFIG_SYS_SDRAM_SIZE 0x40000 - #endif /* __CONFIG_ZYNQ_CSE_H */ -- 2.7.4

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[U-Boot] [PATCH] ARM: dts: rmobile: Add HS200 support to E3 Ebisu
by Marek Vasut 18 Jun '18

18 Jun '18

Add regulator nodes and pinmux settings to the SDHI3 on E3 Ebisu and enable HS200 mode on it. Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- arch/arm/dts/r8a77990-ebisu.dts | 38 +++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/dts/r8a77990-ebisu.dts b/arch/arm/dts/r8a77990-ebisu.dts index e68d78678a..564240a266 100644 --- a/arch/arm/dts/r8a77990-ebisu.dts +++ b/arch/arm/dts/r8a77990-ebisu.dts @@ -28,6 +28,24 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &avb { @@ -71,6 +89,18 @@ groups = "scif_clk_a"; function = "scif_clk"; }; + + sdhi3_pins: sd2 { + groups = "sdhi3_data8", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <1800>; + }; + + sdhi3_pins_uhs: sd2_uhs { + groups = "sdhi3_data8", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <1800>; + }; }; &sdhi0 { @@ -82,7 +112,15 @@ }; &sdhi3 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&reg_3p3v>; + vqmmc-supply = <&reg_1p8v>; bus-width = <8>; + mmc-hs200-1_8v; non-removable; status = "okay"; }; -- 2.17.1

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[U-Boot] P4080DS SerDes configuration (and P4080DS memory, mabye?)
by wolfgang＠leila.ping.de 17 Jun '18

17 Jun '18

Dear QoriQ experts, I am trying to set up a P4080DS board. The manual (P4080DSUG.pdf) lists SerDes configurations with Bank 1 lanes A-H used as PCIe, and Banks 2 and 3 as SGMII (one of them configured as XAUI would be OK, too - what is important to me is 3 PCI slots and an SGMII slot). U-Boot lists valid serdes configurations matching those given in the processor reference manual P4080RM.pdf (table 3-16 on page 144) in arch/powerpc/cpu/mpc85xx/p4080_serdes.c where no such configuration is found - however, the document "PBL Configuration Tool User Guide" (QCSPBLUG.pdf) by Freescale/NXP implies some more configurations on page 12. Does anybody know about those other configurations? As I did not find any reference in the Errata I am not yet convinced to give up on them... BTW, is a pair of registered DIMMs KVR1333D3D4R9S/8G (DDR3 8GB) supposed to work in the board with current U-Boot 2018.07-rc1-00165-ga715415bb5? The memory seems to be detected vorrectly but then the console hangs at the first "Testing..." line: [...] DRAM: Initializing....using SPD Detected RDIMM 9965516-001.B00LF Detected RDIMM 9965516-001.B00LF 14 GiB left unmapped Testing 0x00000000 - 0x7fffffff 2x4GB unbuffered DIMMs seem to run smooth. Best regards, Wolfgang

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