May 2018 - U-Boot

[U-Boot] [PATCH 0/7] *** Qualcomm Snapdraon serial fixes***
by Ramon Fried 16 May '18

16 May '18

In my ongoing effort to get rid of LK (Qualcomm's bootloader) that runs before U-boot, I found that there were some problems with the uart driver of Snapdragon. It appears that the uart only worked because the initialization was previously done by LK. While fixing, I also introduced a new pinctrl driver for snapdragon (currently only enabled for APQ8016). the pinctrl driver is used for muxing the uart pins and configure the pins IO properties. Ramon Fried (7): db820c: set clk node to be probed before relocation serial: serial_msm: fail probe if settings clocks fails serial: serial_msm: initialize uart only before relocation mach-snapdragon: Fix UART clock flow mach-snapdragon: Introduce pinctrl driver db410: added pinctrl node and serial bindings serial: serial_msm: added pinmux & config arch/arm/dts/dragonboard410c.dts | 14 ++ arch/arm/dts/dragonboard820c-uboot.dtsi | 14 ++ arch/arm/mach-snapdragon/Makefile | 2 + arch/arm/mach-snapdragon/clock-apq8016.c | 23 ++- arch/arm/mach-snapdragon/clock-apq8096.c | 4 +- arch/arm/mach-snapdragon/clock-snapdragon.c | 17 ++- arch/arm/mach-snapdragon/clock-snapdragon.h | 9 +- .../mach-snapdragon/include/mach/sysmap-apq8016.h | 1 + arch/arm/mach-snapdragon/pinctrl-apq8016.c | 162 +++++++++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 118 +++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 21 +++ configs/dragonboard410c_defconfig | 5 + drivers/serial/serial_msm.c | 30 +++- include/dt-bindings/pinctrl/pinctrl-snapdragon.h | 22 +++ 14 files changed, 423 insertions(+), 19 deletions(-) create mode 100644 arch/arm/mach-snapdragon/pinctrl-apq8016.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.c create mode 100644 arch/arm/mach-snapdragon/pinctrl-snapdragon.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-snapdragon.h -- 2.14.1

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[U-Boot] [PATCH 1/2] ARM: dts: exynos5: remove the duplicated nodes
by Jaehoon Chung 16 May '18

16 May '18

Remove the duplicated gic and combiner nodes in exynos5.dtsi. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- arch/arm/dts/exynos5.dtsi | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi index 8650800f52..8b725c0ddc 100644 --- a/arch/arm/dts/exynos5.dtsi +++ b/arch/arm/dts/exynos5.dtsi @@ -45,33 +45,6 @@ #size-cells = <0>; }; - combiner: interrupt-controller@10440000 { - compatible = "samsung,exynos4210-combiner"; - #interrupt-cells = <2>; - interrupt-controller; - samsung,combiner-nr = <32>; - reg = <0x10440000 0x1000>; - interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, - <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, - <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, - <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, - <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, - <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, - <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; - }; - - gic: interrupt-controller@10481000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x10481000 0x1000>, - <0x10482000 0x1000>, - <0x10484000 0x2000>, - <0x10486000 0x2000>; - interrupts = <1 9 0xf04>; - }; - i2c_0: i2c@12C60000 { compatible = "samsung,s3c2440-i2c"; reg = <0x12C60000 0x100>; -- 2.15.1

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[U-Boot] [PATCH] net: include/phy.h: add new mode for internal phy
by Kunihiko Hayashi 15 May '18

15 May '18

Add the new mode to indicate a built-in PHY. This will be used by UniPhier AVE ethernet driver. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko(a)socionext.com> --- include/phy.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/phy.h b/include/phy.h index 0543ec1..d0f60d1 100644 --- a/include/phy.h +++ b/include/phy.h @@ -66,6 +66,7 @@ typedef enum { PHY_INTERFACE_MODE_XAUI, PHY_INTERFACE_MODE_RXAUI, PHY_INTERFACE_MODE_SFI, + PHY_INTERFACE_MODE_INTERNAL, PHY_INTERFACE_MODE_NONE, /* Must be last */ PHY_INTERFACE_MODE_COUNT, @@ -88,6 +89,7 @@ static const char *phy_interface_strings[] = { [PHY_INTERFACE_MODE_XAUI] = "xaui", [PHY_INTERFACE_MODE_RXAUI] = "rxaui", [PHY_INTERFACE_MODE_SFI] = "sfi", + [PHY_INTERFACE_MODE_INTERNAL] = "internal", [PHY_INTERFACE_MODE_NONE] = "", }; -- 2.7.4

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[U-Boot] [PATCH v3 00/11] pmic: sandbox: Add support for MC34709 PMIC
by Lukasz Majewski 15 May '18

15 May '18

Adding this device required some changes into the PMIC uclass. Most notable one was the support for 3 bytes r/w operations. Moreover, emulation and tests for this device has been added to sandbox. Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/378678458 Changes in v3: - None - None - Rename dm_pmic_info to uc_pmic_priv - Rename dm_pmic_info -> uc_pmic_priv - Replace printf() -> debug() - Use priv->trans_len instead of tx_num - Rename dm_pmic_info with uc_pmic_priv - Sort alphabetically includes - Add comment regarding MC34708 byte ordering - Replace dm_pmic_info with uc_pmic_priv - Replace pmic_info with priv - Replace pr_err() with debug() - dm_pmic_info -> uc_pmic_priv - Fix DTS property style to compy with Device Tree specification as suggested by Fabio. - Enable MC34708 PMIC support in sandbox_{flattree|spl}_defconfig - None - Fix pmic.c test code after adjusting the sandbox PMIC related dts Changes in v2: - None - None - New patch - pmic_reg_* fixes to use uclass private structure - Support for uclass private data with trasfer length - New patch - New patch - New patch - New patch - New patch - New patch Lukasz Majewski (11): pmic: fsl: Provide some more definitions for MC34708 PMIC pmic: fsl: Define number of bytes sent at once by MC34708 PMIC pmic: Add support for setting transmission length in uclass private data pmic: dm: Rewrite pmic_reg_{read|write|clrsetbits} to support 3 bytes transmissions pmic: dm: Add support for MC34708 for PMIC DM pmic: Rewrite the pmic command to not only work with single byte transmission sandbox: Rewrite i2c_pmic_emul.c to support PMIC with 3 bytes transmission sandbox: Enable support for MC34708 PMIC in DTS sandbox: Enable MC34708 PMIC support sandbox: tests: Exclude common test code (pmic_get) in test/dm/pmic.c sandbox: tests: Add tests for mc34708 PMIC device arch/sandbox/dts/sandbox.dts | 4 ++ arch/sandbox/dts/sandbox64.dts | 4 ++ arch/sandbox/dts/sandbox_pmic.dtsi | 33 ++++++++++++ arch/sandbox/dts/test.dts | 4 ++ cmd/pmic.c | 31 ++++++----- configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + drivers/power/pmic/Kconfig | 7 +++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/i2c_pmic_emul.c | 45 +++++++++++----- drivers/power/pmic/mc34708.c | 105 +++++++++++++++++++++++++++++++++++++ drivers/power/pmic/pmic-uclass.c | 52 +++++++++++++----- include/fsl_pmic.h | 41 +++++++++++++++ include/power/pmic.h | 9 ++++ test/dm/pmic.c | 68 +++++++++++++++++++++++- 16 files changed, 367 insertions(+), 40 deletions(-) create mode 100644 drivers/power/pmic/mc34708.c -- 2.11.0

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[U-Boot] [PATCH] image.h Allow booting Aarch64 from arm
by Ramon Fried 15 May '18

15 May '18

Snapdragon bootloader needs to jump from 32bit to 64bit Allow booting in these cases when CONFIG_AARCH32_SUPPORT_ARM64 is defined. Signed-off-by: Ramon Fried <ramon.fried(a)gmail.com> --- include/image.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/image.h b/include/image.h index df701e3470..598c66177d 100644 --- a/include/image.h +++ b/include/image.h @@ -817,7 +817,13 @@ static inline int image_check_type(const image_header_t *hdr, uint8_t type) static inline int image_check_arch(const image_header_t *hdr, uint8_t arch) { return (image_get_arch(hdr) == arch) || +#ifndef CONFIG_AARCH32_SUPPORT_ARM64 (image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64); +#else + (image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64) || + (image_get_arch(hdr) == IH_ARCH_ARM64 && arch == IH_ARCH_ARM); +#endif + } static inline int image_check_os(const image_header_t *hdr, uint8_t os) { -- 2.17.0

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[U-Boot] arm: Raspberry Pi Compile warnings
by Duncan Hare 15 May '18

15 May '18

Hi Simon Is this is problem? arch/arm/dts/bcm2835-rpi-a-plus.dtb: Warning (phys_property): Missing property '#phy-cells' in node /phy or bad phandle (referred from /soc/usb@7e980000:phys[0]) repeated about 6 - 8 times make[2]:'arch/arm/dts/bcm2837-rpi-3-b.dtb' is up to date.

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[U-Boot] [PATCH] ARM: mvebu: a38x: Add missing SPDX license identfier
by Chris Packham 15 May '18

15 May '18

mv_ddr_build_message.c is generated in Marvell's standalone mv_ddr code. When imported into u-boot we need to add the appropriate SPDX tag and re-format it slightly. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- drivers/ddr/marvell/a38x/mv_ddr_build_message.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c index 8e60448318f2..2b49b77f7306 100644 --- a/drivers/ddr/marvell/a38x/mv_ddr_build_message.c +++ b/drivers/ddr/marvell/a38x/mv_ddr_build_message.c @@ -1 +1,3 @@ -const char mv_ddr_build_message[] = ""; const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-17.10.4"; +// SPDX-License-Identifier: GPL-2.0 +const char mv_ddr_build_message[] = ""; +const char mv_ddr_version_string[] = "mv_ddr: mv_ddr-armada-17.10.4"; -- 2.17.0

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[U-Boot] [PATCH] image: fit: Allow booting Aarch64 from arm
by Ramon Fried 15 May '18

15 May '18

Snapdragon bootloader needs to jump from 32bit to 64bit Allow booting in these cases when CONFIG_AARCH32_SUPPORT_ARM64 is defined. Signed-off-by: Ramon Fried <ramon.fried(a)gmail.com> --- common/image-fit.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/common/image-fit.c b/common/image-fit.c index 5b93dceae1..62dbfbdd3d 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1253,17 +1253,24 @@ int fit_image_check_arch(const void *fit, int noffset, uint8_t arch) { uint8_t image_arch; int aarch32_support = 0; + int aarch64_support = 0; #ifdef CONFIG_ARM64_SUPPORT_AARCH32 aarch32_support = 1; #endif +#ifdef CONFIG_AARCH32_SUPPORT_ARM64 + aarch64_support = 1; +#endif + if (fit_image_get_arch(fit, noffset, &image_arch)) return 0; return (arch == image_arch) || (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64) || (arch == IH_ARCH_ARM64 && image_arch == IH_ARCH_ARM && - aarch32_support); + aarch32_support) || + (arch == IH_ARCH_ARM && image_arch == IH_ARCH_ARM64 && + aarch64_support); } /** -- 2.17.0

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[U-Boot] Please pull u-boot-video/master
by Anatolij Gustschin 15 May '18

15 May '18

Hi Tom, The following changes since commit db6b0281eca0dc4a1a40d9ef52d543b09979a1bf: Merge branch 'master' of git://git.denx.de/u-boot-rockchip (2018-05-14 18:13:59 -0400) are available in the git repository at: git://git.denx.de/u-boot-video.git master for you to fetch changes up to 3ecec5aadd3c3039adfde6928bbe0104af4929d5: dts: sunxi: add PWM node for sun50i (2018-05-15 08:18:14 +0200) ---------------------------------------------------------------- Vasily Khoruzhick (4): sunxi: video: HDMI: use correct bits for HSYNC and VSYNC polarity. video: dw_hdmi: fix HSYNC and VSYNC polarity settings pwm: sunxi: add support for PWM found on Allwinner A64 dts: sunxi: add PWM node for sun50i arch/arm/dts/sun50i-a64.dtsi | 9 ++ arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/include/asm/arch-sunxi/pwm.h | 12 +++ drivers/pwm/Kconfig | 7 ++ drivers/pwm/Makefile | 1 + drivers/pwm/sunxi_pwm.c | 178 +++++++++++++++++++++++++++++++++ drivers/video/dw_hdmi.c | 4 +- drivers/video/sunxi/sunxi_dw_hdmi.c | 4 +- 8 files changed, 212 insertions(+), 4 deletions(-) create mode 100644 drivers/pwm/sunxi_pwm.c Please pull. Thanks! Anatolij

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[U-Boot] [mips, usb xhci] Question / advice needed: cacheable adresses as a device output buffers?
by Yuri Frolov 15 May '18

15 May '18

Is it possible to use *cached* addresses as device's output buffer? E.g, is it a correct thing, to read an uImage from USB pen to cacheable addresses in order to boot from these cached area? U-Boot 2014.10-00051-g8cb056b-dirty / SDK (May 15 2018 - 17:11:35) CPU: MIPS32 P5600 @ 1200 MHz (Rev 1.0) FPU: Present Cores: 2 (running on CPU0) Timer: 600 MHz ECC: L1 L2 (80800ff0) PLLs: CPU: 1200MHz SATA: 600MHz ETH:1250MHz PCIE:1200MHz DDR3: 400MHz AXI: 600MHz Board: Baikal-T1 BFK3 Watchdog enabled I2C: ready DRAM: Rank = 1 highmem = 1792 MiB lowmem = 128 MiB NVRAM: ready Rev: 3.1 MIPS: SIMD ready MIPS: Write Merge enable MIPS: MAAR[0]: 0x00010000-0x07ffffff speculate MIPS: secondary cache 1024kB, 8-way, linesize 32 bytes. In: serial Out: serial Err: serial RomID: 20ba181000002360907301001500102604164781 Net: dwmac.bf05e000, dwmac.bf060000 First, read a file to cacheable adresses: # usb start; fatload usb 0:1 81000000 uimage.nfs (Re)start USB... USB0: Register 1000140 NbrPorts 1 Starting the controller USB XHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found reading uimage.nfs 4630013 bytes read in 2532 ms (1.7 MiB/s) BAIKAL # md 81000000 81000000: 00000000 ffffffff 00000000 ffffffff ................ 81000010: 00000000 ffffffff 00000000 ffffffff ................ 81000020: 00000000 ffffffff 00000000 ffffffff ................ 81000030: 00000000 ffffffff 00000000 ffffffff ................ 81000040: 00000000 ffffffff 00000000 ffffffff ................ 81000050: 00000000 ffffffff 00000000 ffffffff ................ 81000060: 00000000 ffffffff 00000000 ffffffff ................ 81000070: 00000000 ffffffff 00000000 ffffffff ................ 81000080: 00000000 ffffffff 00000000 ffffffff ................ 81000090: 00000000 ffffffff 00000000 ffffffff ................ 810000a0: 00000000 ffffffff 00000000 ffffffff ................ 810000b0: 00000000 ffffffff 00000000 ffffffff ................ 810000c0: 00000000 ffffffff 00000000 ffffffff ................ 810000d0: 00000000 ffffffff 00000000 ffffffff ................ 810000e0: 00000000 ffffffff 00000000 ffffffff ................ 810000f0: 00000000 ffffffff 00000000 ffffffff ................ Then, to the uncacheable area: # usb start; fatload usb 0:1 a1000000 uimage.nfs (Re)start USB... USB0: Register 1000140 NbrPorts 1 Starting the controller USB XHCI 1.00 scanning bus 0 for devices... 2 USB Device(s) found scanning usb for storage devices... 1 Storage Device(s) found reading uimage.nfs 4630013 bytes read in 2531 ms (1.7 MiB/s) BAIKAL # md a1000000 a1000000: 56190527 1697a1a2 0107d65a bda54600 '..V....Z....F.. a1000010: 00001080 d0618780 1644ad13 01020505 ......a...D..... a1000020: 756e694c 2e342d78 31312e34 66622d38 Linux-4.4.118-bf a1000030: 302d336b 33333335 6361672d 66623237 k3-05333-gac72bf a1000040: 00088b1f 00000000 7dec0302 655c7c7d ...........}}|\e a1000050: ce6fef9d eda6499c 69da4f40 3300be99 ..o..I..@O.i...3 a1000060: 691a49ed 880701c0 9261ca32 495d80be .I.i....2.a...]I a1000070: dd04505f 9794931d d5dbdc5d 72c4a2b2 _P......]......r a1000080: 7418a648 5a2c44cc d243745d a6430294 H..t.D,Z]tC...C. a1000090: 0af17960 74540b12 dd5652f5 12baeecb `y....Tt.RV..... a10000a0: 7c50575d 0a5655e9 fbf739b4 9273ce7d ]WP|.UV..9..}.s. a10000b0: 7ad69a69 ee3fdef7 e4f9f247 f39e7333 i..z..?.G...3s.. a10000c0: f7e7bf3c cf7fdefc f1bc88db 1bdfc6f7 <............... a10000d0: 7faa7f7f 454b9f9b f45f9fab c9665b1e ......KE.._..[f. a10000e0: ae9dcaee e3cb8d95 3395f895 653f2f62 ...........3b/?e a10000f0: d6e9dc8e f2f4b9f0 bc069153 d4f75d2f ........S.../].. and, exactly after loading/reading from uncached addresses: # md 81000000 81000000: 00000000 ffffffff 00000000 ffffffff ................ 81000010: 00000000 ffffffff 00000000 ffffffff ................ 81000020: 00000000 ffffffff 00000000 ffffffff ................ 81000030: 00000000 ffffffff 00000000 ffffffff ................ 81000040: 00000000 ffffffff 00000000 ffffffff ................ 81000050: 00000000 ffffffff 00000000 ffffffff ................ 81000060: 00000000 ffffffff 00000000 ffffffff ................ 81000070: 00000000 ffffffff 00000000 ffffffff ................ 81000080: 00000000 ffffffff 00000000 ffffffff ................ 81000090: 00000000 ffffffff 00000000 ffffffff ................ 810000a0: 7c50575d 0a5655e9 fbf739b4 9273ce7d ]WP|.UV..9..}.s. 810000b0: 7ad69a69 ee3fdef7 e4f9f247 f39e7333 i..z..?.G...3s.. 810000c0: 00000000 ffffffff 00000000 ffffffff ................ 810000d0: 00000000 ffffffff 00000000 ffffffff ................ 810000e0: 00000000 ffffffff 00000000 ffffffff ................ 810000f0: 00000000 ffffffff 00000000 ffffffff ................ From the config for the board: #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Only one bank on lower 512 MB can be reached without MMU */ #define CONFIG_SYS_SDRAM_SIZE 0x08000000 As far, as I can see, usb xhci is prepared to deal with uncached memory buffers: common/usb_storage.c: static int usb_stor_BBB_transport(ccb *srb, struct us_data *us) { /* lines were deleted */ ... /* DATA phase + error handling */ result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, &data_actlen, USB_CNTL_TIMEOUT * 5); flush_cache(srb->pdata, srb->datalen); // this is the line I've added; it's not a part of official u-boot tree /* lines were deleted */ } usb_bulk_msg -> ... -> xhci_bulk_tx (drivers/usb/host/xhci-ring.c) contains the line: /* flush the buffer before use */ xhci_flush_cache((uint32_t)buffer, length); xhci_flush_cache is: flush_dcache_range(addr & ~(CACHELINE_SIZE - 1), ALIGN(addr + len, CACHELINE_SIZE));

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