May 2018 - U-Boot

[U-Boot] [PATCH 3/4] board: ax25-ae350: Support cfi flash
by Andes 24 May '18

24 May '18

From: Rick Chen <rick(a)andestech.com> Add smc_init() to get register base from dts and deal with atfsmc020 controler initialzation job. Write protect is enabled by default. So WP shall be disabled when startup, then cfi flash can be detected and erasing and writing can be executed. Adp-ae3xx and adp-ag101p both do smc initilize job in lowlevel_init.S and get register base fron CONFIG_FTSMC020_BASE. They also can be moved those codes to board stage. Remind them as todo jobs. After that CONFIG_FTSMC020_BASE can be removed. Signed-off-by: Rick Chen <rick(a)andestech.com> Signed-off-by: Rick Chen <rickchen36(a)gmail.com> Cc: Greentime Hu <green.hu(a)gmail.com> --- board/AndesTech/ax25-ae350/ax25-ae350.c | 34 +++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index d2e9bcb..ffec1e1 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -11,6 +11,8 @@ #include <netdev.h> #endif #include <linux/io.h> +#include <faraday/ftsmc020.h> +#include <fdtdec.h> DECLARE_GLOBAL_DATA_PTR; @@ -73,3 +75,35 @@ void *board_fdt_blob_setup(void) return (void *)CONFIG_SYS_FDT_BASE; } + +int smc_init(void) +{ + int node = -1; + const char *compat = "andestech,atfsmc020"; + void *blob = (void *)gd->fdt_blob; + fdt_addr_t addr; + struct ftsmc020_bank *regs; + + node = fdt_node_offset_by_compatible(blob, -1, compat); + if (node < 0) + return -FDT_ERR_NOTFOUND; + + addr = fdtdec_get_addr(blob, node, "reg"); + + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + regs = (struct ftsmc020_bank *)addr; + regs->cr &= ~FTSMC020_BANK_WPROT; + + return 0; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + smc_init(); + + return 0; +} +#endif -- 2.7.4

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[U-Boot] [PATCH 2/4] riscv: dts: Support cfi flash
by Andes 24 May '18

24 May '18

From: Rick Chen <rick(a)andestech.com> Add nor node for cfi-flash driver and smc node for smc(aftsmc020) controller. Signed-off-by: Rick Chen <rick(a)andestech.com> Signed-off-by: Rick Chen <rickchen36(a)gmail.com> Cc: Greentime Hu <green.hu(a)gmail.com> --- arch/riscv/dts/ae350.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts index f7d4190..be72b5c 100644 --- a/arch/riscv/dts/ae350.dts +++ b/arch/riscv/dts/ae350.dts @@ -117,6 +117,18 @@ interrupt-parent = <&plic0>; }; + smc0: smc@e0400000 { + compatible = "andestech,atfsmc020"; + reg = <0x0 0xe0400000 0x0 0x1000>; + }; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x0 0x88000000 0x0 0x1000>; + bank-width = <2>; + device-width = <1>; + }; + spi: spi@f0b00000 { compatible = "andestech,atcspi200"; reg = <0x0 0xf0b00000 0x0 0x1000>; -- 2.7.4

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[U-Boot] [PATCH 1/4] configs: ax25-ae350: Support cfi flash
by Andes 24 May '18

24 May '18

From: Rick Chen <rick(a)andestech.com> Enable cfi flash driver and setup flash parameters to support parallel nor flash which type is JS28F00A-M29EWH. Verification: Size detection, data read, erase and write are all ok. Signed-off-by: Rick Chen <rick(a)andestech.com> Signed-off-by: Rick Chen <rickchen36(a)gmail.com> Cc: Greentime Hu <green.hu(a)gmail.com> --- configs/ax25-ae350_defconfig | 5 +++++ include/configs/ax25-ae350.h | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+) mode change 100644 => 100755 include/configs/ax25-ae350.h diff --git a/configs/ax25-ae350_defconfig b/configs/ax25-ae350_defconfig index 4ceccb7..59919b8 100644 --- a/configs/ax25-ae350_defconfig +++ b/configs/ax25-ae350_defconfig @@ -4,8 +4,10 @@ CONFIG_DEFAULT_DEVICE_TREE="ae350" CONFIG_TARGET_AX25_AE350=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y # CONFIG_AUTO_COMPLETE is not set CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_SF_TEST=y @@ -25,6 +27,9 @@ CONFIG_MMC=y CONFIG_DM_MMC=y CONFIG_FTSDC010=y CONFIG_FTSDC010_SDIO=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h old mode 100644 new mode 100755 index a90c75a..8ce3e6c --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -80,6 +80,44 @@ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) +/* + * FLASH and environment organization + */ + +/* use CFI framework */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL + +/* support JEDEC */ +#ifdef CONFIG_CFI_FLASH +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ +#define PHYS_FLASH_1 0x88000000 /* BANK 0 */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ + +/* max number of memory banks */ +/* + * There are 4 banks supported for this Controller, + * but we have only 1 bank connected to flash on board +*/ +#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#endif +#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} + +/* max number of sectors on one chip */ +#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) +#define CONFIG_SYS_MAX_FLASH_SECT 512 + /* environments */ #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 -- 2.7.4

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[U-Boot] [PATCH v3 00/10] Add Intel Stratix 10 SoC support
by Ley Foon Tan 24 May '18

24 May '18

This is 3rd version of patchset to adds support for Intel Stratix 10 SoC. This patchset is work on top of uboot.git/master and patchset in [1]. Changes: - rebase on uboot.git/master - update reviewed-by Patchset history: [v1]: https://patchwork.ozlabs.org/cover/900499/ [v2]: https://patchwork.ozlabs.org/cover/916060/ [1]: https://patchwork.ozlabs.org/cover/910018/ Ley Foon Tan (10): arm: socfpga: misc: Move bridge command to misc common arm: socfpga: stratix10: Add misc support for Stratix10 SoC arm: socfpga: stratix10: Add mailbox support for Stratix10 SoC arm: socfpga: stratix10: Add MMU support for Stratix10 SoC arm: socfpga: Restructure the SPL file arm: socfpga: stratix10: Add SPL driver for Stratix10 SoC arm: socfpga: stratix10: Add timer support for Stratix10 SoC ddr: altera: stratix10: Add DDR support for Stratix10 SoC board: altera: stratix10: Add socdk board support for Stratix10 SoC arm: socfpga: stratix10: Enable Stratix10 SoC build arch/arm/Kconfig | 10 +- arch/arm/mach-socfpga/Kconfig | 13 + arch/arm/mach-socfpga/Makefile | 16 +- arch/arm/mach-socfpga/include/mach/firewall_s10.h | 120 +++++++ arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 144 ++++++++ arch/arm/mach-socfpga/include/mach/misc.h | 2 + arch/arm/mach-socfpga/include/mach/sdram_s10.h | 183 ++++++++++ arch/arm/mach-socfpga/mailbox_s10.c | 380 ++++++++++++++++++++ arch/arm/mach-socfpga/misc.c | 31 ++ arch/arm/mach-socfpga/misc_gen5.c | 26 +-- arch/arm/mach-socfpga/misc_s10.c | 133 +++++++ arch/arm/mach-socfpga/mmu-arm64_s10.c | 71 ++++ arch/arm/mach-socfpga/spl_a10.c | 105 ++++++ arch/arm/mach-socfpga/{spl.c => spl_gen5.c} | 62 +--- arch/arm/mach-socfpga/spl_s10.c | 199 +++++++++++ arch/arm/mach-socfpga/timer_s10.c | 26 ++ board/altera/stratix10-socdk/MAINTAINERS | 7 + board/altera/stratix10-socdk/Makefile | 7 + board/altera/stratix10-socdk/socfpga.c | 7 + configs/socfpga_stratix10_defconfig | 56 +++ drivers/ddr/altera/Makefile | 1 + drivers/ddr/altera/sdram_s10.c | 388 +++++++++++++++++++++ include/configs/socfpga_stratix10_socdk.h | 222 ++++++++++++ 23 files changed, 2129 insertions(+), 80 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/firewall_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/mailbox_s10.h create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_s10.h create mode 100644 arch/arm/mach-socfpga/mailbox_s10.c create mode 100644 arch/arm/mach-socfpga/misc_s10.c create mode 100644 arch/arm/mach-socfpga/mmu-arm64_s10.c create mode 100644 arch/arm/mach-socfpga/spl_a10.c rename arch/arm/mach-socfpga/{spl.c => spl_gen5.c} (81%) create mode 100644 arch/arm/mach-socfpga/spl_s10.c create mode 100644 arch/arm/mach-socfpga/timer_s10.c create mode 100644 board/altera/stratix10-socdk/MAINTAINERS create mode 100644 board/altera/stratix10-socdk/Makefile create mode 100644 board/altera/stratix10-socdk/socfpga.c create mode 100644 configs/socfpga_stratix10_defconfig create mode 100644 drivers/ddr/altera/sdram_s10.c create mode 100644 include/configs/socfpga_stratix10_socdk.h

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[U-Boot] [PATCH] ehci: msm: Replace board_prepare_usb with board_usb_init
by Ramon Fried 24 May '18

24 May '18

Use standard board_usb_init() instead of the specific board_prepare_usb. Signed-off-by: Ramon Fried <ramon.fried(a)gmail.com> --- board/qualcomm/dragonboard410c/dragonboard410c.c | 4 ++-- drivers/usb/host/ehci-msm.c | 11 ++++------- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c index e7ead57f0d..679eab759a 100644 --- a/board/qualcomm/dragonboard410c/dragonboard410c.c +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -41,7 +41,7 @@ int dram_init_banksize(void) return 0; } -int board_prepare_usb(enum usb_init_type type) +int board_usb_init(int index, enum usb_init_type init) { static struct udevice *pmic_gpio; static struct gpio_desc hub_reset, usb_sel; @@ -90,7 +90,7 @@ int board_prepare_usb(enum usb_init_type type) } } - if (type == USB_INIT_HOST) { + if (init == USB_INIT_HOST) { /* Start USB Hub */ dm_gpio_set_dir_flags(&hub_reset, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c index 17bfa7c02f..9ecd8d6732 100644 --- a/drivers/usb/host/ehci-msm.c +++ b/drivers/usb/host/ehci-msm.c @@ -38,11 +38,6 @@ struct msm_ehci_priv { struct ulpi_viewport ulpi_vp; /* ULPI Viewport */ }; -int __weak board_prepare_usb(enum usb_init_type type) -{ - return 0; -} - static void setup_usb_phy(struct msm_ehci_priv *priv) { /* Select and enable external configuration with USB PHY */ @@ -102,7 +97,7 @@ static int ehci_usb_probe(struct udevice *dev) hcor = (struct ehci_hcor *)((phys_addr_t)hccr + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); - ret = board_prepare_usb(USB_INIT_HOST); + ret = board_usb_init(0, USB_INIT_HOST); if (ret < 0) return ret; @@ -124,7 +119,7 @@ static int ehci_usb_remove(struct udevice *dev) reset_usb_phy(p); - ret = board_prepare_usb(USB_INIT_DEVICE); /* Board specific hook */ + ret = board_usb_init(0, USB_INIT_DEVICE); /* Board specific hook */ if (ret < 0) return ret; @@ -150,6 +145,8 @@ static int ehci_usb_ofdata_to_platdata(struct udevice *dev) if (priv->ehci == (void *)FDT_ADDR_T_NONE) return -EINVAL; + dev->req_seq = 0; + /* Warning: this will not work if viewport address is > 64 bit due to * ULPI design. */ -- 2.17.0

2 2

[U-Boot] [PATCH 2/2] mmc: ftsdc010_mci: Sync compatible with DT mmc node
by Andes 24 May '18

24 May '18

From: Rick Chen <rick(a)andestech.com> The compatible string of ftsdc010_mci.c is different from the mmc driver in Linux Kernel. Modify it for consistency. Signed-off-by: Rick Chen <rick(a)andestech.com> Signed-off-by: Rick Chen <rickchen36(a)gmail.com> Cc: Greentime Hu <green.hu(a)gmail.com> --- drivers/mmc/ftsdc010_mci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 9de3a15..f98472c 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -464,7 +464,7 @@ int ftsdc010_mmc_bind(struct udevice *dev) } static const struct udevice_id ftsdc010_mmc_ids[] = { - { .compatible = "andestech,atsdc010" }, + { .compatible = "andestech,atfsdc010" }, { } }; -- 2.7.4

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[U-Boot] [PATCH 1/2] riscv: dts: Sync DT with Linux Kernel
by Andes 24 May '18

24 May '18

From: Rick Chen <rick(a)andestech.com> Use same dts to boot U-Boot and RISC-V Linux Kernel v4.16-rc2 in ax25-ae350 platform. Signed-off-by: Rick Chen <rick(a)andestech.com> Signed-off-by: Rick Chen <rickchen36(a)gmail.com> Cc: Greentime Hu <green.hu(a)gmail.com> --- arch/riscv/dts/ae350.dts | 204 ++++++++++++++++++++++++++++------------------- 1 file changed, 122 insertions(+), 82 deletions(-) diff --git a/arch/riscv/dts/ae350.dts b/arch/riscv/dts/ae350.dts index 4bfb876..f7d4190 100644 --- a/arch/riscv/dts/ae350.dts +++ b/arch/riscv/dts/ae350.dts @@ -1,97 +1,137 @@ /dts-v1/; + / { - compatible = "riscv32 ax25"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + compatible = "andestech,ax25"; + model = "andestech,ax25"; + + aliases { + uart0 = &serial0; + spi0 = &spi; + } ; + + chosen { + bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + }; - aliases { - uart0 = &serial0; - ethernet0 = &mac0; - spi0 = &spi; - } ; + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + clock-frequency = <60000000>; + CPU0_intc: interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; - chosen { - bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; - stdout-path = "uart0:38400n8"; - tick-timer = &timer0; - }; + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x40000000>; + }; - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "andestech,riscv-ae350-soc"; + ranges; + }; - spiclk: virt_100mhz { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; + plmt0@e6000000 { + compatible = "riscv,plmt0"; + interrupts-extended = <&CPU0_intc 7>; + reg = <0x0 0xe6000000 0x0 0x100000>; + }; - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "andestech,n13"; - reg = <0>; - /* FIXME: to fill correct frqeuency */ - clock-frequency = <60000000>; - }; - }; + plic0: interrupt-controller@e4000000 { + compatible = "riscv,plic0"; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x0 0xe4000000 0x0 0x2000000>; + riscv,ndev=<31>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>; + }; - intc: interrupt-controller { - compatible = "andestech,atnointc010"; - #interrupt-cells = <1>; - interrupt-controller; - }; + plic1: interrupt-controller@e6400000 { + compatible = "riscv,plic1"; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0x0 0xe6400000 0x0 0x400000>; + riscv,ndev=<1>; + interrupts-extended = <&CPU0_intc 3>; + }; - serial0: serial@f0300000 { - compatible = "andestech,uart16550", "ns16550a"; - reg = <0xf0300000 0x1000>; - interrupts = <7 4>; - clock-frequency = <19660800>; - reg-shift = <2>; - reg-offset = <32>; - no-loopback-test = <1>; - }; + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; - timer0: timer@f0400000 { - compatible = "andestech,atcpit100"; - reg = <0xf0400000 0x1000>; - interrupts = <2 4>; - clock-frequency = <40000000>; - }; + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0x0 0xf0400000 0x0 0x1000>; + clock-frequency = <40000000>; + interrupts = <3 4>; + interrupt-parent = <&plic0>; + }; - mac0: mac@e0100000 { - compatible = "andestech,atmac100"; - reg = <0xe0100000 0x1000>; - interrupts = <25 4>; - }; + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x0 0xf0300000 0x0 0x1000>; + interrupts = <9 4>; + clock-frequency = <19660800>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + interrupt-parent = <&plic0>; + }; - mmc0: mmc@f0e00000 { - compatible = "andestech,atsdc010"; - max-frequency = <100000000>; - fifo-depth = <0x10>; - reg = <0xf0e00000 0x1000>; - interrupts = <17 4>; - cap-sd-highspeed; - }; + mac0: mac@e0100000 { + compatible = "andestech,atmac100"; + reg = <0x0 0xe0100000 0x0 0x1000>; + interrupts = <19 4>; + interrupt-parent = <&plic0>; + }; - spi: spi@f0b00000 { - compatible = "andestech,atcspi200"; - reg = <0xf0b00000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - clocks = <&spiclk>; - interrupts = <3 4>; - flash@0 { - compatible = "spi-flash"; - spi-max-frequency = <50000000>; - reg = <0>; - spi-cpol; - spi-cpha; - }; - }; + mmc0: mmc@f0e00000 { + compatible = "andestech,atfsdc010"; + max-frequency = <100000000>; + clock-freq-min-max = <400000 100000000>; + fifo-depth = <0x10>; + reg = <0x0 0xf0e00000 0x0 0x1000>; + interrupts = <18 4>; + cap-sd-highspeed; + interrupt-parent = <&plic0>; + }; + spi: spi@f0b00000 { + compatible = "andestech,atcspi200"; + reg = <0x0 0xf0b00000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + clocks = <&spiclk>; + interrupts = <3 4>; + interrupt-parent = <&plic0>; + flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-cpol; + spi-cpha; + }; + }; }; -- 2.7.4

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[U-Boot] [PATCH] dlmalloc: ensure gd is set for early free
by Eugeniu Rosca 23 May '18

23 May '18

This fix seems to be a twin of v2015.01 commit 854d2b9753e4 ("dlmalloc: ensure gd is set for early alloc"). Here is a gdb backtrace to make them look even more similar (sandbox build): (gdb) run Starting program: /path/to/u-boot [Thread debugging using libthread_db enabled] Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1". Program received signal SIGSEGV, Segmentation fault. 0x00000000004123c0 in free (mem=0x0) at common/dlmalloc.c:2460 2460 if (mem == NULL) /* free(0) has no effect */ (gdb) where #0 0x00000000004123c0 in free (mem=0x0) at common/dlmalloc.c:2460 #1 0x00007ffff3f46cea in ?? () from /lib/x86_64-linux-gnu/libselinux.so.1 #2 0x00007ffff7de76ba in call_init (l=<optimized out>, argc=argc@entry=1, argv=argv@entry=0x7fffffffd928, env=env@entry=0x7fffffffd938) at dl-init.c:72 #3 0x00007ffff7de77cb in call_init (env=0x7fffffffd938, argv=0x7fffffffd928, argc=1, l=<optimized out>) at dl-init.c:30 #4 _dl_init (main_map=0x7ffff7ffe168, argc=1, argv=0x7fffffffd928, env=0x7fffffffd938) at dl-init.c:120 #5 0x00007ffff7dd7c6a in _dl_start_user () from /lib64/ld-linux-x86-64.so.2 #6 0x0000000000000001 in ?? () #7 0x00007fffffffddbb in ?? () #8 0x0000000000000000 in ?? () Interestingly, this issue appears on a very old v2015.04 U-boot, but not on u-boot/master (even if the fix applies cleanly to u-boot/master). With the patch applied, my ancient u-boot starts to work properly: $ ./u-boot U-Boot 2015.04-00280-g5755c9e48b83 (May 23 2018 - 20:53:31) DRAM: 128 MiB Using default environment In: serial Out: lcd Err: lcd => Signed-off-by: Eugeniu Rosca <erosca(a)de.adit-jv.com> --- common/dlmalloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/dlmalloc.c b/common/dlmalloc.c index b395eefbf862..6012f9f162c0 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1524,7 +1524,7 @@ void fREe(mem) Void_t* mem; #if CONFIG_VAL(SYS_MALLOC_F_LEN) /* free() is a no-op - all the memory will be freed on relocation */ - if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) + if (gd && !(gd->flags & GD_FLG_FULL_MALLOC_INIT)) return; #endif -- 2.17.0

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Re: [U-Boot] QUERY:U-boot DM:SERIAL:Multiple On-chip UART Controller Support
by Simon Glass 23 May '18

23 May '18

On 23 May 2018 at 11:56, Vabhav Sharma <vabhav.sharma(a)nxp.com> wrote: > Hello Everyone, > > I am working on integrating generic PL011 driver in u-boot and linux for > ARMv8 NXP SoC and facing issue with multiple UART console enablement in > u-boot using DM model > > Kindly provide your valuable feedback and experts comments. > > > > DTS require stdout-path(e.g-UART0) to the /chosen device tree node > ,Accordingly controller(UART0) is probed/initialized as boot console > > On u-boot prompt, Bootargs is modified to use UART1(ttyAMA1) console for > linux boot but kernel hangs after “Starting kernel ... print” > > > > After debugging it’s found that UART1 is not initialized and single(first) > controller is probed/initialized in u-boot (Irrespective of 4 UART nodes > are enabled in dts) > > In drivers/serial/serial-uclass.c ,gd->cur_serial_dev is updated to the DT > stdout-path or CONFIG_CONS_INDEX or platform data(first index) > > > > Does the u-boot DM model support only one or multiple UART driver > probing/initialization? Is there any configuration parameter required to > define number of UART controllers to be probed/initialized. > > This looks limitation as same boot console is used for u-boot and linux and > unable to use all available UART controllers. > > > > I am new to u-boot and please correct any misunderstanding > > Let me know If I can submit a patch for multiple UART probe in serial-uclass > or open a bug for multiple UART support in u-boot DM model > > > > PS:I am unable to find owner of serial uclass driver from MAINTAINERS file > > > > Regards, > > Vabhav > >

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[U-Boot] [PATCH] soc: zynqmp: Update required API version to 1.0
by Michal Simek 23 May '18

23 May '18

From: Rajan Vaja <rajan.vaja(a)xilinx.com> Existing EEMI version is to as 1.0 (available from xilinx v2018.1 version). Update required API version to match with EEMI API version. New PMUFW version is required for operations with programmable logic. Signed-off-by: Rajan Vaja <rajanv(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/cpu/armv8/zynqmp/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 792a3e1b655f..e122be59c747 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -173,8 +173,8 @@ int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, #define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001 -#define ZYNQMP_PM_VERSION_MAJOR 0 -#define ZYNQMP_PM_VERSION_MINOR 3 +#define ZYNQMP_PM_VERSION_MAJOR 1 +#define ZYNQMP_PM_VERSION_MINOR 0 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF -- 2.17.0

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