October 2018 - U-Boot

Re: [U-Boot] u-boot-rockchip: firefly-rk3288 hangs on: Loading Environment from MMC
by Vagrant Cascadian 27 Dec '18

27 Dec '18

On 2018-05-12, Vagrant Cascadian wrote: > On 2018-05-12, Vagrant Cascadian wrote: >> Booting firefly-rk3288 seems to hang looking for environment: >> >> U-Boot 2018.05+dfsg-1 (May 10 2018 - 20:24:57 +0000) >> >> Model: Firefly-RK3288 >> DRAM: 2 GiB >> MMC: dwmmc@ff0c0000: 1, dwmmc@ff0f0000: 0 >> Loading Environment from MMC... >> >> And just hangs there. I tried to bisect this, and got: commit 04a2ea248f58b3b6216d0cd0a6b8698df8b14355 Author: Jean-Jacques Hiblot <jjhiblot(a)ti.com> Date: Thu Sep 21 16:30:08 2017 +0200 mmc: disable UHS modes if Vcc cannot be switched on and off But it fails in a slightly different way: U-Boot 2018.01-00026-g04a2ea248f (May 21 2018 - 21:46:18 +0000) Model: Firefly-RK3288 DRAM: 2 GiB MMC: dwmmc@ff0c0000: 1, dwmmc@ff0f0000: 0 And just hangs without the "Loading Environment from MMC..." part... It is not a trivial revert on top of 2018.05, so I haven't been able to do that simple test. CONFIG_ENV_IS_IN_MMC has been enabled since at least: 5dc4dfd2a94 (Tom Rini 2017-08-28 07:16:32 -0400 36) CONFIG_ENV_IS_IN_MMC=y live well, vagrant

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[U-Boot] [PATCH] fs: cbfs: remove wrong header validation
by Christian Gmeiner 23 Dec '18

23 Dec '18

Coreboot does not contain such a check: https://github.com/coreboot/coreboot/blob/eeb4e20b2f6d786c92fe3efb30817e903… Before this change cbfsinit failed with 'Bad CBFS file'. After this change all cbfs commands are working as expected. Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- fs/cbfs/cbfs.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c index 0dce639b49..2a581f0c18 100644 --- a/fs/cbfs/cbfs.c +++ b/fs/cbfs/cbfs.c @@ -96,11 +96,7 @@ static int file_cbfs_next_file(u8 *start, u32 size, u32 align, } swap_file_header(&header, fileHeader); - if (header.offset < sizeof(struct cbfs_fileheader) || - header.offset > header.len) { - file_cbfs_result = CBFS_BAD_FILE; - return -1; - } + newNode->next = NULL; newNode->type = header.type; newNode->data = start + header.offset; -- 2.17.1

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[U-Boot] UBIFS Problems with U-boot 2018.1 & 4.14 Linux
by Otto Blom 20 Dec '18

20 Dec '18

Hi There ! I'm seeing a strange problem with u-boot 2018.1 and Linux 4.14 (Xilinx Petalinux 2018.1). If I write a ubifs image to flash using Linux 4.9 I can mount and read files from the image in both u-boot 2018.1 and Linux 4.14. However as soon as I write a new file to the file-system from Linux, U-boot can no longer read the file. The filesystem still mounts, but when I attempt to read the file I get the following error UBIFS error (ubi0:0 pid 0): read_block: bad data node (block 661, inode 5763) magic 0x6101831 crc 0x8e6aff1a node_type 1 (data node) group_type 0 (no node group) sqnum 63819 len 3075 key (5763, data, 661) size 4096 compr_typ 1 data size 3027 data: UBIFS error (ubi0:0 pid 0): do_readpage: cannot read page 661 of inode 5763, error -22 The file can still be read correctly from Linux, leading me to believe there is some form of incompatibility going on. I noticed that the ubifs version number was bumped from 4 to 5 in this commit http://git.infradead.org/linux-ubifs.git/commit/fc4b891bbefa73b496bb44b076b… Both Linux 4.9 and U-boot 18.1 still have version 4. Could that have something do to with it ? I'm running on a ZynqMP platform with Micron Flash (On-Die ECC) Thanks in advance, /Otto

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[U-Boot] [PATCH v2] syscon: update syscon_node_to_regmap to use the DM functions
by Patrick Delaunay 17 Dec '18

17 Dec '18

+ Update the function syscon_node_to_regmap() to force bound on syscon uclass and directly use the list of device from DM. + Remove the static list syscon_list. This patch avoid issue (crash) when syscon_node_to_regmap() is called before and after reallocation (list content is invalid). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> --- Hi This patch is a modified (after Simon Glass review) and rebased version on v2018.11-rc3 for [U-Boot] syscon: reset node list syscon_list after relocation http://patchwork.ozlabs.org/patch/983139/ This patch correct a crash see on v2018.11-rc1 with my board stm32mp1 for the command "reset", reproduced on v2018.11-rc3. The crash is a side effect of 2 patches 1f6ca3f42f6edf143473159297f4c515b1cf36f6 sysreset: syscon: update regmap access to syscon 23471aed5c33e104d6fa64575932577618543bec board_f: Add reset status printing With the first patch the syscon_node_to_regmap() is called each time that the class sysreset_syscon is probed. => in v2018.09 probe is done only when reset is requested NB: for stm32mp1, the node rcc_reboot in tagged pre-relocated to support reset in pre-reloc phases (allow panic). With the second patch, U-Boot probes all the sysreset uclass in preloc phase to allow to print the reset status, and the list is initialized in board_f / pre-reloc: -> print_resetinfo --> uclass_first_device_err(UCLASS_SYSRESET, &dev); ---> syscon_reboot_probe() ----> syscon_node_to_regmap(node) -----> of_syscon_register() -------> list_add_tail(&syscon->list, &syscon_list); During relocation, the content of syscon_list (static) is updated but the list use pointers allocated by malloc in pre-reloc phasis And when I execute the reset command -> do_reset() --> reset_cpu() ---> sysreset_walk_halt(SYSRESET_COLD); ----> loop on device UCLASS_SYSRESET -----> syscon_reboot_probe() ------> syscon_node_to_regmap(node) -------> list_for_each_entry(entry, &syscon_list, list) I have a crash here because the pointer syscon_list.next is invalid. This patch solves the issue by using DM list for syscon uclass. Tested on my board, the initial issue is solved and I check the behavior with dm_dump_all(): the RCC driver is not binded/probed as syscon uclass by default (checked with dm tree) and correctly bounded and probed when it is necessary (before relocation: print_resetinfo() or after relocation for command reset). Regards Patrick Changes in v2: - minor update after Simon review (remove variable ofnode and add one comment) drivers/core/syscon-uclass.c | 55 ++++++++++++++------------------------------ 1 file changed, 17 insertions(+), 38 deletions(-) diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c index 303e166..3864f13 100644 --- a/drivers/core/syscon-uclass.c +++ b/drivers/core/syscon-uclass.c @@ -123,52 +123,31 @@ U_BOOT_DRIVER(generic_syscon) = { * The syscon node can be bound to another driver, but still works * as a syscon provider. */ -static LIST_HEAD(syscon_list); - -struct syscon { - ofnode node; - struct regmap *regmap; - struct list_head list; -}; - -static struct syscon *of_syscon_register(ofnode node) +struct regmap *syscon_node_to_regmap(ofnode node) { - struct syscon *syscon; + struct udevice *dev, *parent; int ret; + if (!uclass_get_device_by_ofnode(UCLASS_SYSCON, node, &dev)) + return syscon_get_regmap(dev); + if (!ofnode_device_is_compatible(node, "syscon")) return ERR_PTR(-EINVAL); - syscon = malloc(sizeof(*syscon)); - if (!syscon) - return ERR_PTR(-ENOMEM); + /* bound to driver with same ofnode or to root if not found */ + if (device_find_global_by_ofnode(node, &parent)) + parent = dm_root(); - ret = regmap_init_mem(node, &syscon->regmap); - if (ret) { - free(syscon); + /* force bound to syscon class */ + ret = device_bind_driver_to_node(parent, "syscon", + ofnode_get_name(node), + node, &dev); + if (ret) return ERR_PTR(ret); - } - - list_add_tail(&syscon->list, &syscon_list); - - return syscon; -} -struct regmap *syscon_node_to_regmap(ofnode node) -{ - struct syscon *entry, *syscon = NULL; - - list_for_each_entry(entry, &syscon_list, list) - if (ofnode_equal(entry->node, node)) { - syscon = entry; - break; - } - - if (!syscon) - syscon = of_syscon_register(node); - - if (IS_ERR(syscon)) - return ERR_CAST(syscon); + ret = device_probe(dev); + if (ret) + return ERR_PTR(ret); - return syscon->regmap; + return syscon_get_regmap(dev); } -- 2.7.4

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[U-Boot] [PATCH v3 00/31] virtio: Introduce VirtIO driver support
by Bin Meng 13 Dec '18

13 Dec '18

This series brings in VirtIO driver support in U-Boot. The work is based on Tuomas's virtio support on QEMU ARM targets. VirtIO is a virtualization standard for network and disk device drivers where just the guest's device driver "knows" it is running in a virtual environment, and cooperates with the hypervisor. This enables guests to get high performance network and disk operations, and gives most of the performance benefits of paravirtualization. In the U-Boot case, the guest is U-Boot itself, while the virtual environment are normally QEMU targets like ARM, RISC-V and x86. Both VirtIO MMIO and PCI transport options are supported. Only VirtIO network and block device drivers are supported for now. The following QEMU targets are supported. - qemu_arm_defconfig - qemu_arm64_defconfig - qemu-riscv32_defconfig - qemu-riscv64_defconfig - qemu-x86_defconfig - qemu-x86_64_defconfig A new child_post_probe() uclass driver method is introduced to better support virtio device driver. This also changes BLK uclass driver to supply a post_probe() method which calls part_init(), so that we can avoid duplicating such call in every BLK driver. Not every checkpatch warning reported was fixed, but I tried to fix as many as possible which makes sense. travis-ci build all pass. This series is available at u-boot-x86/virtio-working for testing. Changes in v3: - Exclude VIRTIO_BLK in sandbox_noblk_defconfig build Changes in v2: - new patch to add test case for uclass driver's child_post_probe() - new patch to add dm_remove_devices_flags() call to do_bootm_linux() for riscv bootm - Added virtio spec link and a short statement of what virtio is in the header and source files - Changed to use 'transport' over 'bus' in drivers/virtio/Kconfig - Added UCLASS_VIRTIO ID in alphabetical order - Moved the header file inclusion from virtio.h to C file - Fixed code styling issue (blank line before return) in virtio_xxx() APIs - Changed virtio_init() to return int if there is an error - Added virtio_uclass_pre_probe() to check virtio transport driver ops here so that we don't need check these ops each time when the virtio_xxx APIs are called - Implemented child_post_remove() method to reset the virtio device - Changed virtio_driver_features_init() parameter 'feature' and 'feature_legacy' to const, and adjust member of 'struct virtio_dev_priv' accordingly - Initialize uc_priv->vqs in virtio_uclass_post_probe() - Changed virtio net driver feature table to const - Correct desc->vendor for PCI transport - imply VIRTIO_PCI for qemu-arm too - use an internal function _dm_pci_find_next_capability() for dm_pci_find_capability() and dm_pci_find_next_capability() - adjust swap_case driver to handle request from _dm_pci_find_next_capability() - fix compiler warnings in 64-bit build - adjust virtio_pci_find_capability() to avoid walking through capability list to find next one by ourselves - new patch to add a Sandbox transport driver - new patch to add test cases for virtio uclass - Added driver remove and flags description in the documentation Bin Meng (26): dm: core: Allow uclass to set up a device's child after it is probed test: dm: core: Add test case for uclass driver's child_post_probe() riscv: bootm: Add dm_remove_devices_flags() call to do_bootm_linux() dm: Add a new uclass driver for VirtIO transport devices virtio: Add virtio over mmio transport driver test: dm: blk: Correct blk_base test case sandbox: blk: Switch to use platdata_auto_alloc_size for the driver data efi_driver: blk: Switch to use platdata_auto_alloc_size for the driver data blk: Call part_init() in the post_probe() method blk: Drop blk_prepare_device() blk: Make blk_next_free_devnum() public riscv: qemu: Enumerate virtio bus during early boot riscv: qemu: Include some useful commands kconfig: Introduce HAVE_ARCH_IOMAP x86: Implement arch-specific io accessor routines virtio: Add virtio over pci transport driver arm: qemu: Add a Kconfig in the board directory arm: qemu: Enumerate virtio bus during early boot x86: qemu: Imply virtio PCI transport and device drivers dm: pci: Add APIs to find next capability and extended capability test: dm: pci: Add cases for finding next PCI capability APIs virtio: pci: Support non-legacy PCI transport device virtio: net: Support non-legacy device virtio: Add a Sandbox transport driver test: dm: virtio: Add test cases for virtio uclass doc: Document virtio support Tuomas Tynkkynen (5): virtio: Add codes for virtual queue/ring management virtio: Add net driver support blk: Introduce IF_TYPE_VIRTIO virtio: Add block driver support virtio: cmd: Add virtio command for virtio devices arch/Kconfig | 6 + arch/arm/Kconfig | 1 + arch/riscv/lib/bootm.c | 11 +- arch/sandbox/dts/test.dts | 8 + arch/x86/include/asm/io.h | 66 +++ board/emulation/qemu-arm/Kconfig | 13 + board/emulation/qemu-arm/qemu-arm.c | 10 + board/emulation/qemu-riscv/Kconfig | 11 + board/emulation/qemu-riscv/qemu-riscv.c | 9 + board/emulation/qemu-x86/Kconfig | 3 + cmd/Kconfig | 7 + cmd/Makefile | 1 + cmd/sata.c | 9 - cmd/virtio.c | 38 ++ common/usb_storage.c | 4 +- configs/qemu_arm64_defconfig | 1 - configs/qemu_arm_defconfig | 1 - configs/sandbox_noblk_defconfig | 1 + disk/part.c | 6 + doc/README.virtio | 253 ++++++++++++ drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/block/blk-uclass.c | 25 +- drivers/block/ide.c | 2 - drivers/block/sandbox.c | 17 +- drivers/core/uclass.c | 13 +- drivers/misc/swap_case.c | 9 + drivers/mmc/mmc.c | 3 - drivers/nvme/nvme.c | 1 - drivers/pci/pci-uclass.c | 51 ++- drivers/scsi/scsi.c | 1 - drivers/virtio/Kconfig | 62 +++ drivers/virtio/Makefile | 11 + drivers/virtio/virtio-uclass.c | 369 +++++++++++++++++ drivers/virtio/virtio_blk.c | 137 +++++++ drivers/virtio/virtio_blk.h | 129 ++++++ drivers/virtio/virtio_mmio.c | 413 +++++++++++++++++++ drivers/virtio/virtio_mmio.h | 129 ++++++ drivers/virtio/virtio_net.c | 239 +++++++++++ drivers/virtio/virtio_net.h | 268 ++++++++++++ drivers/virtio/virtio_pci.h | 173 ++++++++ drivers/virtio/virtio_pci_legacy.c | 421 +++++++++++++++++++ drivers/virtio/virtio_pci_modern.c | 609 +++++++++++++++++++++++++++ drivers/virtio/virtio_ring.c | 358 ++++++++++++++++ drivers/virtio/virtio_sandbox.c | 233 +++++++++++ include/blk.h | 22 +- include/dm/test.h | 1 + include/dm/uclass-id.h | 1 + include/dm/uclass.h | 4 +- include/linux/io.h | 4 + include/pci.h | 48 +++ include/virtio.h | 707 ++++++++++++++++++++++++++++++++ include/virtio_ring.h | 320 +++++++++++++++ include/virtio_types.h | 24 ++ lib/Kconfig | 6 + lib/efi_driver/efi_block_device.c | 26 +- test/dm/Makefile | 1 + test/dm/blk.c | 27 +- test/dm/bus.c | 45 ++ test/dm/pci.c | 20 + test/dm/test-fdt.c | 7 +- test/dm/virtio.c | 122 ++++++ 62 files changed, 5421 insertions(+), 99 deletions(-) create mode 100644 board/emulation/qemu-arm/Kconfig create mode 100644 cmd/virtio.c create mode 100644 doc/README.virtio create mode 100644 drivers/virtio/Kconfig create mode 100644 drivers/virtio/Makefile create mode 100644 drivers/virtio/virtio-uclass.c create mode 100644 drivers/virtio/virtio_blk.c create mode 100644 drivers/virtio/virtio_blk.h create mode 100644 drivers/virtio/virtio_mmio.c create mode 100644 drivers/virtio/virtio_mmio.h create mode 100644 drivers/virtio/virtio_net.c create mode 100644 drivers/virtio/virtio_net.h create mode 100644 drivers/virtio/virtio_pci.h create mode 100644 drivers/virtio/virtio_pci_legacy.c create mode 100644 drivers/virtio/virtio_pci_modern.c create mode 100644 drivers/virtio/virtio_ring.c create mode 100644 drivers/virtio/virtio_sandbox.c create mode 100644 include/virtio.h create mode 100644 include/virtio_ring.h create mode 100644 include/virtio_types.h create mode 100644 test/dm/virtio.c -- 2.7.4

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[U-Boot] [PATCH 00/13] dm: DM_FLAG_PRE_RELOC flag clean up
by Bin Meng 12 Dec '18

12 Dec '18

When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree This series should be applied on top of u-boot-dm/master, for v2018.11 release. Bin Meng (13): arm: stm32mp: Remove DM_FLAG_PRE_RELOC flag clk: Remove DM_FLAG_PRE_RELOC flag in various drivers gpio: Remove DM_FLAG_PRE_RELOC flag in various drivers i2c: omap24xx: Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check mmc: omap: Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check pinctrl: Remove DM_FLAG_PRE_RELOC flag in various drivers ram: bmips: Remove DM_FLAG_PRE_RELOC flag timer: Remove DM_FLAG_PRE_RELOC flag in various drivers serial: Remove DM_FLAG_PRE_RELOC flag in various drivers sysreset: Remove DM_FLAG_PRE_RELOC flag in various drivers video: simplefb: Remove DM_FLAG_PRE_RELOC flag watchdog: Remove DM_FLAG_PRE_RELOC flag in various drivers dm: doc: Update description of pre-relocation support arch/arm/mach-stm32mp/bsec.c | 1 - arch/x86/cpu/tangier/sysreset.c | 1 - doc/driver-model/README.txt | 16 ++++++++++++---- drivers/clk/altera/clk-arria10.c | 1 - drivers/clk/clk_pic32.c | 1 - drivers/clk/clk_zynq.c | 1 - drivers/clk/exynos/clk-exynos7420.c | 3 --- drivers/clk/owl/clk_s900.c | 1 - drivers/gpio/omap_gpio.c | 2 ++ drivers/gpio/stm32f7_gpio.c | 2 +- drivers/gpio/tegra186_gpio.c | 1 - drivers/gpio/tegra_gpio.c | 1 - drivers/i2c/omap24xx_i2c.c | 2 ++ drivers/mmc/omap_hsmmc.c | 2 ++ drivers/pinctrl/broadcom/pinctrl-bcm283x.c | 2 ++ drivers/pinctrl/exynos/pinctrl-exynos7420.c | 1 - drivers/pinctrl/nxp/pinctrl-imx5.c | 2 ++ drivers/pinctrl/nxp/pinctrl-imx6.c | 2 ++ drivers/pinctrl/nxp/pinctrl-imx7.c | 2 ++ drivers/pinctrl/nxp/pinctrl-imx7ulp.c | 2 ++ drivers/pinctrl/pinctrl-single.c | 1 - drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 2 ++ drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 2 ++ drivers/ram/bmips_ram.c | 1 - drivers/serial/altera_jtag_uart.c | 1 - drivers/serial/altera_uart.c | 1 - drivers/serial/arm_dcc.c | 1 - drivers/serial/atmel_usart.c | 2 ++ drivers/serial/ns16550.c | 2 ++ drivers/serial/serial_ar933x.c | 1 - drivers/serial/serial_arc.c | 1 - drivers/serial/serial_bcm283x_mu.c | 2 ++ drivers/serial/serial_bcm283x_pl011.c | 2 ++ drivers/serial/serial_bcm6345.c | 1 - drivers/serial/serial_efi.c | 1 - drivers/serial/serial_intel_mid.c | 1 - drivers/serial/serial_lpuart.c | 1 - drivers/serial/serial_meson.c | 1 - drivers/serial/serial_mvebu_a3700.c | 1 - drivers/serial/serial_mxc.c | 2 ++ drivers/serial/serial_omap.c | 2 ++ drivers/serial/serial_owl.c | 1 - drivers/serial/serial_pic32.c | 1 - drivers/serial/serial_pl01x.c | 2 ++ drivers/serial/serial_s5p.c | 1 - drivers/serial/serial_sh.c | 2 ++ drivers/serial/serial_sti_asc.c | 1 - drivers/serial/serial_stm32.c | 2 ++ drivers/serial/serial_xuartlite.c | 1 - drivers/serial/serial_zynq.c | 1 - drivers/sysreset/sysreset_x86.c | 1 - drivers/timer/ag101p_timer.c | 1 - drivers/timer/altera_timer.c | 1 - drivers/timer/arc_timer.c | 1 - drivers/timer/ast_timer.c | 1 - drivers/timer/atcpit100_timer.c | 1 - drivers/timer/atmel_pit_timer.c | 1 - drivers/timer/cadence-ttc.c | 1 - drivers/timer/dw-apb-timer.c | 1 - drivers/timer/mpc83xx_timer.c | 1 - drivers/timer/omap-timer.c | 1 - drivers/timer/rockchip_timer.c | 1 - drivers/timer/sti-timer.c | 1 - drivers/timer/stm32_timer.c | 1 - drivers/timer/tsc_timer.c | 1 - drivers/video/simplefb.c | 1 - drivers/watchdog/ast_wdt.c | 1 - lib/efi/efi_app.c | 1 - 68 files changed, 51 insertions(+), 54 deletions(-) -- 2.7.4

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[U-Boot] [PATCH 1/4] scsi: ceva: add ls1046a soc support
by Peng Ma 11 Dec '18

11 Dec '18

Add ahci compatible support for ls1046a soc. Signed-off-by: Peng Ma <peng.ma(a)nxp.com> --- drivers/ata/sata_ceva.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/ata/sata_ceva.c b/drivers/ata/sata_ceva.c index 65896d1..a2d21d9 100644 --- a/drivers/ata/sata_ceva.c +++ b/drivers/ata/sata_ceva.c @@ -99,6 +99,7 @@ enum ceva_soc { CEVA_LS1012A, CEVA_LS1021A, CEVA_LS1043A, + CEVA_LS1046A, }; struct ceva_sata_priv { @@ -138,6 +139,7 @@ static int ceva_init_sata(struct ceva_sata_priv *priv) case CEVA_LS1012A: case CEVA_LS1043A: + case CEVA_LS1046A: writel(ECC_DIS_ADDR_CH2, ECC_DIS_VAL_CH2); writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG); writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC); @@ -170,6 +172,7 @@ static const struct udevice_id sata_ceva_ids[] = { { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A }, { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A }, { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A }, + { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A }, { } }; -- 1.7.1

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[U-Boot] [RFC] fit: include uncompression into fit_image_load
by Simon Goldschmidt 11 Dec '18

11 Dec '18

Currently, only the kernel can be compressed in a FIT image. By moving the uncompression logic to 'fit_image_load()', all types of images can be compressed. This works perfectly for me when using a gzip'ed FPGA image in a FIT image on a cyclone5 board (socrates). Also, a gzip'ed initrd being unzipped by U-Boot (not the kernel) worked. To clean this up, the uncompression function would have to be moved from bootm.c ('bootm_decomp_image()') to a more generic location, but I decided to keep it for now to make the patch easier to read. Because of this setup, the kernel is currently uncompressed twice. which doesn't work... There are, however, some more things to discuss: - The max. size passed to gunzip() (etc.) is not known before, so we currently configure this to 8 MByte in U-Boot (via CONFIG_SYS_BOOTM_LEN), which proved too small for my initrd... - CONFIG_SYS_BOOTM_LEN is set to 64 MByte default in SPL, so it's a different default for SPL than for U-Boot !?! - CONFIG_SYS_BOOTM_LEN seemed to initially be used for kernel uncompression but is now used as a copy-only limit, too (no unzip) - Uncompression only works if a load address is given, what should happen if the FIT image does not contain a load address? - The whole memory management around FIT images is a bit messed up in that memory allocation is a mix of where U-Boot relocates itself (and which address ranges it used), the load addresses of the FIT image and the load addresses of the FIT image contents (and sizes). What's the point here to check CONFIG_SYS_BOOTM_LEN? Maybe it would be better to keep a memory map of allowed and already used data to check if we're overwriting things or to get the maximum size passed to gunzip etc.? - Some code paths (like the command 'fpga loadmk') directly use 'fit_image_get_data()'. These will have to be converted to use 'fit_image_load()' instead (which will do nothing if the subimage does not contain a load address. - 'fit_image_load()' should probably check for subimages that have a compression set but no load address... Or should we try to malloc() here? A long list of questions, hopefully someone will join me in discussing them :-) Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> --- common/bootm.c | 8 ++++---- common/image-fit.c | 17 +++++++++++++++-- 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/common/bootm.c b/common/bootm.c index 8bf84ebcb7..6b85edb80b 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -361,6 +361,9 @@ int bootm_decomp_image(int comp, ulong load, ulong image_start, int type, { int ret = 0; + if (!unc_len) + unc_len = CONFIG_SYS_BOOTM_LEN; + *load_end = load; print_decomp_msg(comp, type, load == image_start); @@ -373,10 +376,7 @@ int bootm_decomp_image(int comp, ulong load, ulong image_start, int type, case IH_COMP_NONE: if (load == image_start) break; - if (image_len <= unc_len) - memmove_wd(load_buf, image_buf, image_len, CHUNKSZ); - else - ret = 1; + memmove_wd(load_buf, image_buf, image_len, CHUNKSZ); break; #ifdef CONFIG_GZIP case IH_COMP_GZIP: { diff --git a/common/image-fit.c b/common/image-fit.c index 8d39a243f8..030f0098c7 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -23,6 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif /* !USE_HOSTCC*/ #include <image.h> +#include <bootm.h> #include <bootstage.h> #include <u-boot/crc.h> #include <u-boot/md5.h> @@ -1969,8 +1970,9 @@ int fit_image_load(bootm_headers_t *images, ulong addr, } } else if (load_op != FIT_LOAD_OPTIONAL_NON_ZERO || load) { ulong image_start, image_end; - ulong load_end; + ulong load_end, uncomp_len; void *dst; + u8 image_comp; /* * move image data to the load address, @@ -1986,11 +1988,22 @@ int fit_image_load(bootm_headers_t *images, ulong addr, return -EXDEV; } + if (fit_image_get_comp(fit, noffset, &image_comp)) { + puts("Can't get image compression!\n"); + return -EINVAL; + } printf(" Loading %s from 0x%08lx to 0x%08lx\n", prop_name, data, load); dst = map_sysmem(load, len); - memmove(dst, buf, len); + ret = bootm_decomp_image(image_comp, load, image_start, + image_type, dst, (void *)buf, len, 0, + &load_end); + if (ret) { + bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE); + return ret; + } + len = load_end - load; data = load; } bootstage_mark(bootstage_id + BOOTSTAGE_SUB_LOAD); -- 2.17.1

3 10

[U-Boot] [PATCH][v3] armv8: lx2160a: Add LX2160A SoC Support
by Priyanka Jain 10 Dec '18

10 Dec '18

LX2160A Soc is based on Layerscape Chassis Generation 3.2 Architecture. Features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, two 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao(a)nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou(a)nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal(a)nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma(a)nxp.com> Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v3: Add CONFIG_SYS_FSL_RST_ADDR define Changes for v2: Add CCN508 define Rebased on TF-A Boot support for NXP Chassis 2 platforms Removed eSDHC nodes from dts, will be send in separate patch. Add reset related changes arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 52 +++++++- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 6 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 15 ++- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 57 +++++++++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 36 ++++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 132 +++++++++++++++++++++ arch/arm/dts/fsl-lx2160a.dtsi | 118 ++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 56 +++++++++ .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 28 +++++ .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 26 ++++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 6 + .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 9 +- drivers/ddr/fsl/Kconfig | 1 + drivers/net/ldpaa_eth/Makefile | 3 +- drivers/net/ldpaa_eth/lx2160a.c | 107 +++++++++++++++++ 16 files changed, 644 insertions(+), 10 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c create mode 100644 arch/arm/dts/fsl-lx2160a.dtsi create mode 100644 drivers/net/ldpaa_eth/lx2160a.c diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 650ac94..2b086da 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -170,6 +170,42 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2160A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_NXP_SRDS_3 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select SYS_I2C_MXC_I2C1 + select SYS_I2C_MXC_I2C2 + select SYS_I2C_MXC_I2C3 + select SYS_I2C_MXC_I2C4 + select SYS_I2C_MXC_I2C5 + select SYS_I2C_MXC_I2C6 + select SYS_I2C_MXC_I2C7 + select SYS_I2C_MXC_I2C8 + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config FSL_LSCH2 bool select SYS_FSL_HAS_CCI400 @@ -185,7 +221,7 @@ config NXP_LSCH3_2 config FSL_MC_ENET bool "Management Complex network" - depends on ARCH_LS2080A || ARCH_LS1088A + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A default y select RESV_RAM help @@ -202,6 +238,7 @@ config FSL_PCIE_COMPAT default "fsl,ls1046a-pcie" if ARCH_LS1046A default "fsl,ls2080a-pcie" if ARCH_LS2080A default "fsl,ls1088a-pcie" if ARCH_LS1088A + default "fsl,lx2160a-pcie" if ARCH_LX2160A help This compatible is used to find pci controller node in Kernel DT to complete fixup. @@ -300,6 +337,7 @@ config MAX_CPUS default 4 if ARCH_LS1046A default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A + default 16 if ARCH_LX2160A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -342,6 +380,9 @@ config SYS_FSL_HAS_CCI400 config SYS_FSL_HAS_CCN504 bool +config SYS_FSL_HAS_CCN508 + bool + config SYS_FSL_HAS_DP_DDR bool @@ -404,6 +445,7 @@ config SYS_FSL_DSPI_CLK_DIV config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A + default 4 if ARCH_LX2160A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -464,13 +506,15 @@ config RESV_RAM config SYS_FSL_EC1 bool help - Ethernet controller 1, this is connected to MAC3. + Ethernet controller 1, this is connected to + MAC17 for LX2160A or to MAC3 for other SoCs Provides DPAA2 capabilities config SYS_FSL_EC2 bool help - Ethernet controller 2, this is connected to MAC4. + Ethernet controller 2, this is connected to + MAC18 for LX2160A or to MAC4 for other SoCs Provides DPAA2 capabilities config SYS_FSL_ERRATUM_A008336 @@ -506,7 +550,7 @@ config SYS_FSL_HAS_RGMII config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 91fdbad..e9bc987 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2016-2018 NXP # Copyright 2014-2015, Freescale Semiconductor obj-y += cpu.o @@ -22,6 +22,10 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o endif endif +ifneq ($(CONFIG_ARCH_LX2160A),) +obj-$(CONFIG_SYS_HAS_SERDES) += lx2160a_serdes.o +endif + ifneq ($(CONFIG_ARCH_LS2080A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 60b0575..a35958a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -60,6 +60,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), CPU_TYPE_ENTRY(LS1048A, LS1048A, 4), CPU_TYPE_ENTRY(LS1044A, LS1044A, 4), + CPU_TYPE_ENTRY(LX2160A, LX2160A, 16), + CPU_TYPE_ENTRY(LX2120A, LX2120A, 12), + CPU_TYPE_ENTRY(LX2080A, LX2080A, 8), }; #define EARLY_PGTABLE_SIZE 0x5000 @@ -246,7 +249,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_ARCH_LS2080A +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | @@ -366,6 +369,10 @@ void cpu_name(char *name) for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { strcpy(name, cpu_type_list[i].name); +#ifdef CONFIG_ARCH_LX2160A + if (IS_C_PROCESSOR(svr)) + strcat(name, "C"); +#endif if (IS_E_PROCESSOR(svr)) strcat(name, "E"); @@ -1165,10 +1172,16 @@ void __efi_runtime reset_cpu(ulong addr) { u32 val; +#ifdef CONFIG_ARCH_LX2160A + val = in_le32(rstcr); + val |= 0x01; + out_le32(rstcr, val); +#else /* Raise RESET_REQ_B */ val = scfg_in32(rstcr); val |= 0x02; scfg_out32(rstcr, val); +#endif } #ifdef CONFIG_EFI_LOADER diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index 276ab90..a0e2621 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -7,6 +7,7 @@ SoC overview 5. LS1046A 6. LS2088A 7. LS2081A + 8. LX2160A LS1043A --------- @@ -271,3 +272,59 @@ Refer to LS2084A(LS2088A) section above for details. It has one more similar SoC personality 1)LS2041A, few difference w.r.t. LS2081A: a) Four 64-bit ARM v8 Cortex-A72 CPUs + +LX2160A +-------- +The QorIQ LX2160A processor is built in the 16FFC process on +the Layerscape architecture combining sixteen ARM A72 processor +cores with advanced, high-performance datapath acceleration and +network, peripheral interfaces required for networking, wireless +infrastructure, storage, and general-purpose embedded applications. + +LX2160A is compliant with the Layerscape Chassis Generation 3.2. + +The LX2160A SoC includes the following function and features: + Sixteen 32-bit / 64-bit ARM v8 A72 CPUs + Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”) + Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC. + Data path acceleration architecture (DPAA2) + 24 Serdes lanes at up to 25 GHz + Ethernet interfaces + Single WRIOP tile supporting 130Gbps using 18 MACs + Support for 10G-SXGMII (aka USXGMII). + Support for SGMII (and 1000Base-KX) + Support for XFI (and 10GBase-KR) + Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). + Support for XLAUI (and 40GBase-KR4) for 40G. + Support for two RGMII parallel interfaces. + Energy efficient Ethernet support (802.3az) + IEEE 1588 support. + High-speed peripheral interfaces + Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV, + Four PCIe Gen 4.0 4-lane controllers. + Four serial ATA (SATA 3.0) controllers. + Two USB 3.0 controllers with integrated PHY + Two Enhanced secure digital host controllers + Two Controller Area Network (CAN) modules + Flexible Serial peripheral interface (FlexSPI) controller. + Three Serial peripheral interface (SPI) controllers. + Eight I2C Controllers. + Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports. + General Purpose IO (GPIO) + Support for hardware virtualization and partitioning (ARM MMU-500) + Support for GIC (ARM GIC-500) + QorIQ platform Trust Architecture 3.0 + One Secure WatchDog timer and one Non-Secure Watchdog timer. + ARM Generic Timer + Two Flextimers + Debug supporting run control, data acquisition, high-speed trace, + performance/event monitoring + Thermal Monitor Unit (TMU) with +/- 2C accuracy + Support for Voltage ID (VID) for yield improvement + +LX2160A SoC has 2 more similar SoC personalities +1)LX2120A, few difference w.r.t. LX2160A: + a) Twelve 64-bit ARM v8 Cortex-A72 CPUs + +2)LX2080A, few difference w.r.t. LX2160A: + a) Eight 64-bit ARM v8 Cortex-A72 CPUs diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index bb50e3d..ab1be3f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -22,9 +22,18 @@ static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A +int xfi_dpmac[XFI14 + 1]; +int sgmii_dpmac[SGMII18 + 1]; +int a25gaui_dpmac[_25GE10 + 1]; +int xlaui_dpmac[_40GE2 + 1]; +int caui2_dpmac[_50GE2 + 1]; +int caui4_dpmac[_100GE2 + 1]; +#else int xfi_dpmac[XFI8 + 1]; int sgmii_dpmac[SGMII16 + 1]; #endif +#endif __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) { @@ -146,6 +155,32 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, else { serdes_prtcl_map[lane_prtcl] = 1; #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#ifdef CONFIG_ARCH_LX2160A + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl], + (int)lane_prtcl); + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl], + (int)lane_prtcl); + +#else switch (lane_prtcl) { case QSGMII_A: case QSGMII_B: @@ -167,6 +202,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, break; } #endif +#endif } } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index cbc9112..6721a57 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -354,7 +354,7 @@ get_svr: ret #endif -#ifdef CONFIG_SYS_FSL_HAS_CCN504 +#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508) hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c new file mode 100644 index 0000000..a04a370 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x02, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII6, SGMII5, SGMII4, SGMII3 } }, + {0x03, {PCIE2, PCIE2, PCIE2, PCIE2, XFI6, XFI5, XFI4, + XFI3 } }, + {0x04, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, + SGMII3 } }, + {0x05, {XFI10, XFI9, XFI8, XFI7, PCIE1, PCIE1, PCIE1, + PCIE1 } }, + {0x06, {SGMII10, SGMII9, SGMII8, SGMII7, SGMII6, SGMII5, XFI4, + XFI3 } }, + {0x07, {SGMII10, SGMII9, SGMII8, SGMII7, XFI6, XFI5, XFI4, + XFI3 } }, + {0x08, {XFI10, XFI9, XFI8, XFI7, XFI6, XFI5, XFI4, XFI3 } }, + {0x09, {SGMII10, SGMII9, SGMII8, PCIE2, SGMII6, SGMII5, SGMII4, + PCIE1 } }, + {0x0A, {XFI10, XFI9, XFI8, PCIE2, XFI6, XFI5, XFI4, PCIE1 } }, + {0x0B, {SGMII10, SGMII9, PCIE2, PCIE2, SGMII6, SGMII5, PCIE1, PCIE1 } }, + {0x0C, {SGMII10, SGMII9, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x0D, {_100GE2, _100GE2, _100GE2, _100GE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0E, {PCIE2, PCIE2, PCIE2, PCIE2, _100GE1, _100GE1, _100GE1, + _100GE1 } }, + {0x0F, {PCIE2, PCIE2, PCIE2, PCIE2, _50GE2, _50GE2, _50GE1, _50GE1 } }, + {0x10, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _50GE1, _50GE1 } }, + {0x11, {PCIE2, PCIE2, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, _25GE3 } }, + {0x12, {XFI10, XFI9, XFI8, XFI7, _25GE6, _25GE5, XFI4, + XFI3 } }, + {0x13, {_40GE2, _40GE2, _40GE2, _40GE2, _25GE6, _25GE5, XFI4, XFI3 } }, + {0x14, {_40GE2, _40GE2, _40GE2, _40GE2, _40GE1, _40GE1, _40GE1, + _40GE1 } }, + {0x15, {_25GE10, _25GE9, PCIE2, PCIE2, _25GE6, _25GE5, _25GE4, + _25GE3 } }, + {0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } }, + {} +}; + +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x01, {PCIE3, PCIE3, SATA1, SATA2, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x02, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } }, + {0x03, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } }, + {0x04, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } }, + {0x05, {PCIE3, PCIE3, PCIE3, PCIE3, SATA3, SATA4, SATA1, SATA2 } }, + {0x06, {PCIE3, PCIE3, PCIE3, PCIE3, SGMII15, SGMII16, XFI13, + XFI14 } }, + {0x07, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, XFI13, + XFI14 } }, + {0x08, {NONE, NONE, SATA1, SATA2, SATA3, SATA4, XFI13, XFI14 } }, + {0x09, {SGMII11, SGMII12, SGMII17, SGMII18, SGMII15, SGMII16, SGMII13, + SGMII14} }, + {0x0A, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, PCIE4, + PCIE4 } }, + {0x0B, {PCIE3, SGMII12, SGMII17, SGMII18, PCIE4, SGMII16, SGMII13, + SGMII14 } }, + {0x0C, {SGMII11, SGMII12, SGMII17, SGMII18, PCIE4, PCIE4, SATA1, + SATA2 } }, + {0x0D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SGMII13, SGMII14 } }, + {0x0E, {PCIE3, PCIE3, SGMII17, SGMII18, PCIE4, PCIE4, SGMII13, + SGMII14 } }, + {} +}; + +static struct serdes_config serdes3_cfg_tbl[] = { + /* SerDes 3 */ + {0x02, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5, PCIE5 } }, + {0x03, {PCIE5, PCIE5, PCIE5, PCIE5, PCIE6, PCIE6, PCIE6, PCIE6 } }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, + serdes3_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi new file mode 100644 index 0000000..b407dc6 --- /dev/null +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP lx2160a SOC common device tree source + * + * Copyright 2018 NXP + * + */ + +/ { + compatible = "fsl,lx2160a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>; + /* DRAM space - 1, size : 2 GB DRAM */ + }; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + + clockgen: clocking@1300000 { + compatible = "fsl,ls2080a-clockgen"; + reg = <0 0x1300000 0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + }; + + gic: interrupt-controller@6000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06200000 0 0x100000>; /* GICR */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <1 9 0x4>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ + <1 14 0x8>, /* Physical NS PPI, active-low */ + <1 11 0x8>, /* Virtual PPI, active-low */ + <1 10 0x8>; /* Hypervisor PPI, active-low */ + }; + + uart0: serial@21c0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21c0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart1: serial@21d0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21d0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + }; + + uart2: serial@21e0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21e0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + uart3: serial@21f0000 { + compatible = "arm,pl011"; + reg = <0x0 0x21f0000 0x0 0x1000>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <0 26 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <0 240 0x4>; /* Level high type */ + num-cs = <6>; + }; + + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <0 241 0x4>; /* Level high type */ + num-cs = <6>; + }; + + usb0: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index bd4ca88..d4f80a2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2016-2018 NXP * Copyright 2015, Freescale Semiconductor */ @@ -176,6 +177,61 @@ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ +/* LX2160A Soc Support */ +#elif defined(CONFIG_ARCH_LX2160A) +#define TZPC_BASE 0x02200000 +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_EARLY_INIT +#define SRDS_MAX_LANES 8 +#ifndef L1_CACHE_BYTES +#define L1_CACHE_SHIFT 6 +#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) +#endif +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 + +#define CONFIG_SYS_PAGE_SIZE 0x10000 + +#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ + +/* DDR */ +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE + +#define CONFIG_SYS_FSL_CCSR_GUR_LE +#define CONFIG_SYS_FSL_CCSR_SCFG_LE +#define CONFIG_SYS_FSL_ESDHC_LE +#define CONFIG_SYS_FSL_PEX_LUT_LE + +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x06000000 +#define GICR_BASE 0x06200000 + +/* SMMU Definitions */ +#define SMMU_BASE 0x05000000 /* GR0 Base */ + +/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE +#define CONFIG_SYS_FSL_SRK_LE + +/* Security Monitor */ +#define CONFIG_SYS_FSL_SEC_MON_LE + +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS + +/* DCFG - GUR */ +#define CONFIG_SYS_FSL_CCSR_GUR_LE + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index c041a31..68354ff 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -20,8 +20,12 @@ enum srds_prtcl { PCIE2, PCIE3, PCIE4, + PCIE5, + PCIE6, SATA1, SATA2, + SATA3, + SATA4, XAUI1, XAUI2, XFI1, @@ -32,6 +36,12 @@ enum srds_prtcl { XFI6, XFI7, XFI8, + XFI9, + XFI10, + XFI11, + XFI12, + XFI13, + XFI14, SGMII1, SGMII2, SGMII3, @@ -48,10 +58,28 @@ enum srds_prtcl { SGMII14, SGMII15, SGMII16, + SGMII17, + SGMII18, QSGMII_A, QSGMII_B, QSGMII_C, QSGMII_D, + _25GE1, + _25GE2, + _25GE3, + _25GE4, + _25GE5, + _25GE6, + _25GE7, + _25GE8, + _25GE9, + _25GE10, + _40GE1, + _40GE2, + _50GE1, + _50GE2, + _100GE1, + _100GE2, SERDES_PRCTL_COUNT }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 4e01781..2ed6b99 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -15,7 +15,11 @@ #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#ifdef CONFIG_ARCH_LX2160A +#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) +#else #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) +#endif #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) @@ -324,6 +328,28 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 +#elif defined(CONFIG_ARCH_LX2160A) +#define FSL_CHASSIS3_EC1_REGSR 27 +#define FSL_CHASSIS3_EC2_REGSR 27 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK 0x00000003 +#define FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT 2 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x001F0000 +#define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0x03E00000 +#define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 21 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK 0x7C000000 +#define FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT 26 +#define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK +#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK +#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS3_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK +#define FSL_CHASSIS3_SRDS3_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT +#define FSL_CHASSIS3_SRDS1_REGSR 29 +#define FSL_CHASSIS3_SRDS2_REGSR 29 +#define FSL_CHASSIS3_SRDS3_REGSR 29 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_CHASSIS3_EC1_REGSR 26 #define FSL_CHASSIS3_EC2_REGSR 26 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index daa1c70..f5bef6d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -96,12 +96,18 @@ enum boot_src get_boot_src(void); #define SVR_LS2044A 0x870930 #define SVR_LS2081A 0x870918 #define SVR_LS2041A 0x870914 +#define SVR_LX2160A 0x873601 +#define SVR_LX2120A 0x873621 +#define SVR_LX2080A 0x873603 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_REV(svr) (((svr) >> 0) & 0xff) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) +#ifdef CONFIG_ARCH_LX2160A +#define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1)) +#endif #define IS_SVR_REV(svr, maj, min) \ ((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min))) #define SVR_DEV(svr) ((svr) >> 8) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 8d002da..e017d8b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright 2015-2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. * */ @@ -69,11 +70,11 @@ #define FSL_SDMMC_STREAM_ID 3 #define FSL_SATA1_STREAM_ID 4 -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_SATA2_STREAM_ID 5 #endif -#if defined(CONFIG_ARCH_LS2080A) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_DMA_STREAM_ID 6 #elif defined(CONFIG_ARCH_LS1088A) #define FSL_DMA_STREAM_ID 5 @@ -82,6 +83,10 @@ /* PCI - programmed in PEXn_LUT */ #define FSL_PEX_STREAM_ID_START 7 +#ifdef CONFIG_ARCH_LX2160A +#define FSL_PEX_STREAM_ID_NUM (0x100) +#endif + #if defined(CONFIG_ARCH_LS2080A) #define FSL_PEX_STREAM_ID_END 22 #elif defined(CONFIG_ARCH_LS1088A) diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index a3d2bd5..c5bd8a8 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -34,6 +34,7 @@ config SYS_NUM_DDR_CTLRS ARCH_P4080 || \ ARCH_P5020 || \ ARCH_P5040 || \ + ARCH_LX2160A || \ ARCH_T4160 default 1 diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 477ee4f..1d85b2c 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -# +# Copyright 2015-2018 NXP # Copyright 2014 Freescale Semiconductor, Inc. obj-y += ldpaa_wriop.o obj-y += ldpaa_eth.o obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o +obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c new file mode 100644 index 0000000..7dd46c0 --- /dev/null +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ +#include <common.h> +#include <phy.h> +#include <fsl-mc/ldpaa_wriop.h> +#include <asm/io.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> + +u32 dpmac_to_devdisr[] = { + [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, + [WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2, + [WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3, + [WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4, + [WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5, + [WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6, + [WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7, + [WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8, + [WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9, + [WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10, + [WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11, + [WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12, + [WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13, + [WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14, + [WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15, + [WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16, + [WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17, + [WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18, +}; + +static int is_device_disabled(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 devdisr2 = in_le32(&gur->devdisr2); + + return dpmac_to_devdisr[dpmac_id] & devdisr2; +} + +void wriop_dpmac_disable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +void wriop_dpmac_enable(int dpmac_id) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); +} + +phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) +{ + enum srds_prtcl; + + if (is_device_disabled(dpmac_id + 1)) + return PHY_INTERFACE_MODE_NONE; + + if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18) + return PHY_INTERFACE_MODE_SGMII; + + if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14) + return PHY_INTERFACE_MODE_XGMII; + + if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10) + return PHY_INTERFACE_MODE_25G_AUI; + + if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2) + return PHY_INTERFACE_MODE_XLAUI; + + if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2) + return PHY_INTERFACE_MODE_CAUI2; + + if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2) + return PHY_INTERFACE_MODE_CAUI4; + + return PHY_INTERFACE_MODE_NONE; +} + +#ifdef CONFIG_SYS_FSL_HAS_RGMII +void fsl_rgmii_init(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 ec; + +#ifdef CONFIG_SYS_FSL_EC1 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) + & FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID); +#endif + +#ifdef CONFIG_SYS_FSL_EC2 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) + & FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK; + ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID); +#endif +} +#endif -- 2.7.4

2 1

[U-Boot] [PATCH][v2] armv8:fsl-layerscape: Add support for Chassis 3.2
by Priyanka Jain 10 Dec '18

10 Dec '18

NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash(a)nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain(a)nxp.com> --- Changes for v2: Rebased on top of test_qoriq branch of u-boot-fsl-qoriq.git arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 3 +++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 18 +++++++++++++-- .../cpu/armv8/fsl-layerscape/doc/README.lsch3_2 | 27 ++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 13 ++++++++++- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 ++++++++-- 5 files changed, 68 insertions(+), 5 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 2d1946c..650ac94 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -180,6 +180,9 @@ config FSL_LSCH2 config FSL_LSCH3 bool +config NXP_LSCH3_2 + bool + config FSL_MC_ENET bool "Management Complex network" depends on ARCH_LS2080A || ARCH_LS1088A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index f2ac1a1..60b0575 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -120,6 +120,13 @@ static struct mm_region early_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_SIZE, @@ -266,6 +273,13 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_SYS_FSL_DRAM_BASE3 + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, +#endif #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_SIZE, @@ -595,13 +609,13 @@ enum boot_src __get_boot_src(u32 porsr1) { enum boot_src src = BOOT_SOURCE_RESERVED; uint32_t rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT; -#if !defined(CONFIG_FSL_LSCH3_2) +#if !defined(CONFIG_NXP_LSCH3_2) uint32_t val; #endif debug("%s: rcw_src 0x%x\n", __func__, rcw_src); #if defined(CONFIG_FSL_LSCH3) -#if defined(CONFIG_FSL_LSCH3_2) +#if defined(CONFIG_NXP_LSCH3_2) switch (rcw_src) { case RCW_SRC_SDHC1_VAL: src = BOOT_SOURCE_SD_MMC; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 new file mode 100644 index 0000000..6d4bd0b --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3_2 @@ -0,0 +1,27 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +NXP LayerScape with Chassis Generation 3.2 + +This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2 +for example LX2160A. + +This architecture is enhancement over Chassis Generation 3 with +few differences mentioned below + +1)DDR Layout +============ +Entire DDR region splits into three regions. + - Region 1 is at address 0x8000_0000 to 0xffff_ffff. + - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff, + - Region 3 is at address 0x60_0000_0000 to the top of memory, + for example 140GB, 0x63_7fff_ffff. + +All DDR memory is marked as cache-enabled. + +2)IFC is removed + +3)Number of I2C controllers increased to 8 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 3926aa3..eaa9ed2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017 NXP + * Copyright 2017-2018 NXP * Copyright 2014-2015, Freescale Semiconductor */ @@ -12,15 +12,19 @@ #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 +#endif #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 +#endif #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000 @@ -40,8 +44,15 @@ #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 +#ifdef CONFIG_NXP_LSCH3_2 +#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000 +#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000 +#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000 +#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000 +#else #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 +#endif #elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 816d960..4e01781 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -2,7 +2,7 @@ /* * LayerScape Internal Memory Map * - * Copyright (C) 2017 NXP Semiconductors + * Copyright 2017-2018 NXP * Copyright 2014 Freescale Semiconductor, Inc. */ @@ -21,7 +21,9 @@ #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) +#endif #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 @@ -45,6 +47,12 @@ #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +#ifdef CONFIG_NXP_LSCH3_2 +#define I2C5_BASE_ADDR (CONFIG_SYS_IMMR + 0x01040000) +#define I2C6_BASE_ADDR (CONFIG_SYS_IMMR + 0x01050000) +#define I2C7_BASE_ADDR (CONFIG_SYS_IMMR + 0x01060000) +#define I2C8_BASE_ADDR (CONFIG_SYS_IMMR + 0x01070000) +#endif #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000) #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0) #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8) @@ -83,7 +91,7 @@ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) #ifdef CONFIG_TFABOOT -#ifdef CONFIG_FSL_LSCH3_2 +#ifdef CONFIG_NXP_LSCH3_2 /* RCW_SRC field in Power-On Reset Control Register 1 */ #define RCW_SRC_MASK 0x07800000 #define RCW_SRC_BIT 23 -- 2.7.4

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